1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ALPHAINSTRUCTIONINFO_H
15 #define ALPHAINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "AlphaRegisterInfo.h"
22 class AlphaInstrInfo : public TargetInstrInfo {
23 const AlphaRegisterInfo RI;
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
31 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
39 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
40 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
42 virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
43 MachineBasicBlock *FBB,
44 const std::vector<MachineOperand> &Cond) const;
45 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
46 MachineBasicBlock *&FBB,
47 std::vector<MachineOperand> &Cond) const;
48 void RemoveBranch(MachineBasicBlock &MBB) const;
49 void insertNoop(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI) const;
51 bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
52 bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;