1 //===- AlphaInstrInfo.td - The Alpha Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 include "AlphaInstrFormats.td"
15 //********************
17 //********************
19 def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
20 SDTCisFP<1>, SDTCisFP<0>
22 def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
23 def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
24 def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
25 def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>;
26 def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>;
27 def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
28 def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
29 def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
31 def retflag : SDNode<"AlphaISD::RET_FLAG", SDTRet,
32 [SDNPHasChain, SDNPOptInFlag]>;
34 // These are target-independent nodes, but have target-specific formats.
35 def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
36 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeq,
37 [SDNPHasChain, SDNPOutFlag]>;
38 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_AlphaCallSeq,
39 [SDNPHasChain, SDNPOutFlag]>;
41 //********************
42 //Paterns for matching
43 //********************
44 def invX : SDNodeXForm<imm, [{ //invert
45 return getI64Imm(~N->getValue());
47 def negX : SDNodeXForm<imm, [{ //negate
48 return getI64Imm(~N->getValue() + 1);
50 def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
51 return getI64Imm(((int64_t)N->getValue() << 32) >> 32);
53 def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
54 return getI64Imm(((int64_t)N->getValue() << 48) >> 48);
56 def LL16 : SDNodeXForm<imm, [{ //lda part of constant
57 return getI64Imm(get_lda16(N->getValue()));
59 def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
60 return getI64Imm(get_ldah16(N->getValue()));
62 def iZAPX : SDNodeXForm<imm, [{ // get imm to ZAPi
63 return getI64Imm(get_zapImm((uint64_t)N->getValue()));
65 def nearP2X : SDNodeXForm<imm, [{
66 return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getValue())));
68 def nearP2RemX : SDNodeXForm<imm, [{
69 uint64_t x = abs(N->getValue() - getNearPower2((uint64_t)N->getValue()));
70 return getI64Imm(Log2_64(x));
73 def immUExt8 : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
74 return (uint64_t)N->getValue() == (uint8_t)N->getValue();
76 def immUExt8inv : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
77 return (uint64_t)~N->getValue() == (uint8_t)~N->getValue();
79 def immUExt8neg : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
80 return ((uint64_t)~N->getValue() + 1) == (uint8_t)((uint64_t)~N->getValue() + 1);
82 def immSExt16 : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
83 return ((int64_t)N->getValue() << 48) >> 48 == (int64_t)N->getValue();
85 def immSExt16int : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
86 return ((int64_t)N->getValue() << 48) >> 48 == ((int64_t)N->getValue() << 32) >> 32;
88 def immZAP : PatLeaf<(imm), [{ //imm is good for zapi
89 uint64_t build = get_zapImm((uint64_t)N->getValue());
92 def immFPZ : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
95 def immRem1 : PatLeaf<(imm), [{
96 return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 1;
98 def immRem3 : PatLeaf<(imm), [{
99 return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 3;
101 def immRem4 : PatLeaf<(imm), [{
102 return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 4;
104 def immRem5 : PatLeaf<(imm), [{
105 return N->getValue() - getNearPower2((uint64_t)N->getValue()) == 5;
107 def immRem1n : PatLeaf<(imm), [{
108 return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 1;
110 def immRem3n : PatLeaf<(imm), [{
111 return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 3;
113 def immRem4n : PatLeaf<(imm), [{
114 return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 4;
116 def immRem5n : PatLeaf<(imm), [{
117 return getNearPower2((uint64_t)N->getValue()) - N->getValue() == 5;
119 def immRemP2n : PatLeaf<(imm), [{
120 return isPowerOf2_64(getNearPower2((uint64_t)N->getValue()) - N->getValue());
122 def immRemP2 : PatLeaf<(imm), [{
123 return isPowerOf2_64(N->getValue() - getNearPower2((uint64_t)N->getValue()));
125 def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
126 int64_t d = abs((int64_t)N->getValue() - (int64_t)getNearPower2((uint64_t)N->getValue()));
127 if (isPowerOf2_64(d)) return false;
129 case 1: case 3: case 5: return false;
130 default: return (uint64_t)N->getValue() == (uint8_t)N->getValue();
134 def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
135 def add4 : PatFrag<(ops node:$op1, node:$op2),
136 (add (shl node:$op1, 2), node:$op2)>;
137 def sub4 : PatFrag<(ops node:$op1, node:$op2),
138 (sub (shl node:$op1, 2), node:$op2)>;
139 def add8 : PatFrag<(ops node:$op1, node:$op2),
140 (add (shl node:$op1, 3), node:$op2)>;
141 def sub8 : PatFrag<(ops node:$op1, node:$op2),
142 (sub (shl node:$op1, 3), node:$op2)>;
145 //Pseudo ops for selection
147 def IDEF_I : PseudoInstAlpha<(ops GPRC:$RA), "#idef $RA",
148 [(set GPRC:$RA, (undef))], s_pseudo>;
149 def IDEF_F32 : PseudoInstAlpha<(ops F4RC:$RA), "#idef $RA",
150 [(set F4RC:$RA, (undef))], s_pseudo>;
151 def IDEF_F64 : PseudoInstAlpha<(ops F8RC:$RA), "#idef $RA",
152 [(set F8RC:$RA, (undef))], s_pseudo>;
154 def WTF : PseudoInstAlpha<(ops variable_ops), "#wtf", [], s_pseudo>;
156 let isLoad = 1, hasCtrlDep = 1 in {
157 def ADJUSTSTACKUP : PseudoInstAlpha<(ops s64imm:$amt), "; ADJUP $amt",
158 [(callseq_start imm:$amt)], s_pseudo>;
159 def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops s64imm:$amt), "; ADJDOWN $amt",
160 [(callseq_end imm:$amt)], s_pseudo>;
162 def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
163 def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
164 def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
165 "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>;
168 //***********************
170 //***********************
174 //conditional moves, int
176 def CMOVLBC : OForm4< 0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
177 [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
178 def CMOVLBS : OForm4< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
179 [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
180 def CMOVEQ : OForm4< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST",
181 [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
182 def CMOVGE : OForm4< 0x11, 0x46, "cmovge $RCOND,$RTRUE,$RDEST",
183 [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
184 def CMOVGT : OForm4< 0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
185 [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
186 def CMOVLE : OForm4< 0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
187 [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
188 def CMOVLT : OForm4< 0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
189 [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
190 def CMOVNE : OForm4< 0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
191 [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
193 def CMOVEQi : OForm4L< 0x11, 0x24, "cmoveq $RCOND,$RTRUE,$RDEST",
194 [(set GPRC:$RDEST, (select (setne GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
195 def CMOVGEi : OForm4L< 0x11, 0x46, "cmovge $RCOND,$RTRUE,$RDEST",
196 [(set GPRC:$RDEST, (select (setlt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
197 def CMOVGTi : OForm4L< 0x11, 0x66, "cmovgt $RCOND,$RTRUE,$RDEST",
198 [(set GPRC:$RDEST, (select (setle GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
199 def CMOVLEi : OForm4L< 0x11, 0x64, "cmovle $RCOND,$RTRUE,$RDEST",
200 [(set GPRC:$RDEST, (select (setgt GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
201 def CMOVLTi : OForm4L< 0x11, 0x44, "cmovlt $RCOND,$RTRUE,$RDEST",
202 [(set GPRC:$RDEST, (select (setge GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
203 def CMOVNEi : OForm4L< 0x11, 0x26, "cmovne $RCOND,$RTRUE,$RDEST",
204 [(set GPRC:$RDEST, (select (seteq GPRC:$RCOND, 0), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
205 def CMOVLBCi : OForm4L< 0x11, 0x16, "cmovlbc $RCOND,$RTRUE,$RDEST",
206 [(set GPRC:$RDEST, (select (and GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
207 def CMOVLBSi : OForm4L< 0x11, 0x14, "cmovlbs $RCOND,$RTRUE,$RDEST",
208 [(set GPRC:$RDEST, (select (xor GPRC:$RCOND, 1), GPRC:$RFALSE, immUExt8:$RTRUE))], s_cmov>;
211 //General pattern for cmov
212 def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
213 (CMOVNE GPRC:$src2, GPRC:$src1, GPRC:$which)>;
214 def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
215 (CMOVEQi GPRC:$src1, immUExt8:$src2, GPRC:$which)>;
217 //Invert sense when we can for constants:
218 def : Pat<(select (seteq GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
219 (CMOVEQi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
220 def : Pat<(select (setne GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
221 (CMOVNEi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
222 def : Pat<(select (setgt GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
223 (CMOVGTi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
224 def : Pat<(select (setge GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
225 (CMOVGEi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
226 def : Pat<(select (setlt GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
227 (CMOVLTi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
228 def : Pat<(select (setle GPRC:$RCOND, 0), immUExt8:$RFALSE, GPRC:$RTRUE),
229 (CMOVLEi GPRC:$RTRUE, immUExt8:$RFALSE, GPRC:$RCOND)>;
232 def ADDL : OForm< 0x10, 0x00, "addl $RA,$RB,$RC",
233 [(set GPRC:$RC, (intop (add GPRC:$RA, GPRC:$RB)))], s_iadd>;
234 def ADDLi : OFormL<0x10, 0x00, "addl $RA,$L,$RC",
235 [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8:$L)))], s_iadd>;
236 def ADDQ : OForm< 0x10, 0x20, "addq $RA,$RB,$RC",
237 [(set GPRC:$RC, (add GPRC:$RA, GPRC:$RB))], s_iadd>;
238 def ADDQi : OFormL<0x10, 0x20, "addq $RA,$L,$RC",
239 [(set GPRC:$RC, (add GPRC:$RA, immUExt8:$L))], s_iadd>;
240 def AND : OForm< 0x11, 0x00, "and $RA,$RB,$RC",
241 [(set GPRC:$RC, (and GPRC:$RA, GPRC:$RB))], s_ilog>;
242 def ANDi : OFormL<0x11, 0x00, "and $RA,$L,$RC",
243 [(set GPRC:$RC, (and GPRC:$RA, immUExt8:$L))], s_ilog>;
244 def BIC : OForm< 0x11, 0x08, "bic $RA,$RB,$RC",
245 [(set GPRC:$RC, (and GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
246 def BICi : OFormL<0x11, 0x08, "bic $RA,$L,$RC",
247 [(set GPRC:$RC, (and GPRC:$RA, immUExt8inv:$L))], s_ilog>;
248 def BIS : OForm< 0x11, 0x20, "bis $RA,$RB,$RC",
249 [(set GPRC:$RC, (or GPRC:$RA, GPRC:$RB))], s_ilog>;
250 def BISi : OFormL<0x11, 0x20, "bis $RA,$L,$RC",
251 [(set GPRC:$RC, (or GPRC:$RA, immUExt8:$L))], s_ilog>;
252 def CTLZ : OForm2<0x1C, 0x32, "CTLZ $RB,$RC",
253 [(set GPRC:$RC, (ctlz GPRC:$RB))], s_imisc>;
254 def CTPOP : OForm2<0x1C, 0x30, "CTPOP $RB,$RC",
255 [(set GPRC:$RC, (ctpop GPRC:$RB))], s_imisc>;
256 def CTTZ : OForm2<0x1C, 0x33, "CTTZ $RB,$RC",
257 [(set GPRC:$RC, (cttz GPRC:$RB))], s_imisc>;
258 def EQV : OForm< 0x11, 0x48, "eqv $RA,$RB,$RC",
259 [(set GPRC:$RC, (xor GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
260 def EQVi : OFormL<0x11, 0x48, "eqv $RA,$L,$RC",
261 [(set GPRC:$RC, (xor GPRC:$RA, immUExt8inv:$L))], s_ilog>;
262 def EXTBL : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC",
263 [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))], s_ishf>;
264 def EXTWL : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC",
265 [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))], s_ishf>;
266 def EXTLL : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC",
267 [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))], s_ishf>;
269 //def EXTBLi : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
270 //def EXTLH : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
271 //def EXTLHi : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
272 //def EXTLLi : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
273 //def EXTQH : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
274 //def EXTQHi : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
275 //def EXTQ : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low
276 //def EXTQi : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
277 //def EXTWH : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
278 //def EXTWHi : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
279 //def EXTWLi : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low
281 //def IMPLVER : OForm< 0x11, 0x6C, "IMPLVER $RA,$RB,$RC", []>; //Implementation version
282 //def IMPLVERi : OFormL<0x11, 0x6C, "IMPLVER $RA,$L,$RC", []>; //Implementation version
283 //def INSBL : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
284 //def INSBLi : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low
285 //def INSLH : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high
286 //def INSLHi : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high
287 //def INSLL : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low
288 //def INSLLi : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low
289 //def INSQH : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high
290 //def INSQHi : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high
291 //def INSQL : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low
292 //def INSQLi : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low
293 //def INSWH : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high
294 //def INSWHi : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high
295 //def INSWL : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Insert word low
296 //def INSWLi : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC", []>; //Insert word low
297 //def MSKBL : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC", []>; //Mask byte low
298 //def MSKBLi : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC", []>; //Mask byte low
299 //def MSKLH : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC", []>; //Mask longword high
300 //def MSKLHi : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC", []>; //Mask longword high
301 //def MSKLL : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC", []>; //Mask longword low
302 //def MSKLLi : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC", []>; //Mask longword low
303 //def MSKQH : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC", []>; //Mask quadword high
304 //def MSKQHi : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC", []>; //Mask quadword high
305 //def MSKQL : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC", []>; //Mask quadword low
306 //def MSKQLi : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC", []>; //Mask quadword low
307 //def MSKWH : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC", []>; //Mask word high
308 //def MSKWHi : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC", []>; //Mask word high
309 //def MSKWL : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC", []>; //Mask word low
310 //def MSKWLi : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low
312 def MULL : OForm< 0x13, 0x00, "mull $RA,$RB,$RC",
313 [(set GPRC:$RC, (intop (mul GPRC:$RA, GPRC:$RB)))], s_imul>;
314 def MULLi : OFormL<0x13, 0x00, "mull $RA,$L,$RC",
315 [(set GPRC:$RC, (intop (mul GPRC:$RA, immUExt8:$L)))], s_imul>;
316 def MULQ : OForm< 0x13, 0x20, "mulq $RA,$RB,$RC",
317 [(set GPRC:$RC, (mul GPRC:$RA, GPRC:$RB))], s_imul>;
318 def MULQi : OFormL<0x13, 0x20, "mulq $RA,$L,$RC",
319 [(set GPRC:$RC, (mul GPRC:$RA, immUExt8ME:$L))], s_imul>;
320 def ORNOT : OForm< 0x11, 0x28, "ornot $RA,$RB,$RC",
321 [(set GPRC:$RC, (or GPRC:$RA, (not GPRC:$RB)))], s_ilog>;
322 def ORNOTi : OFormL<0x11, 0x28, "ornot $RA,$L,$RC",
323 [(set GPRC:$RC, (or GPRC:$RA, immUExt8inv:$L))], s_ilog>;
324 def S4ADDL : OForm< 0x10, 0x02, "s4addl $RA,$RB,$RC",
325 [(set GPRC:$RC, (intop (add4 GPRC:$RA, GPRC:$RB)))], s_iadd>;
326 def S4ADDLi : OFormL<0x10, 0x02, "s4addl $RA,$L,$RC",
327 [(set GPRC:$RC, (intop (add4 GPRC:$RA, immUExt8:$L)))], s_iadd>;
328 def S4ADDQ : OForm< 0x10, 0x22, "s4addq $RA,$RB,$RC",
329 [(set GPRC:$RC, (add4 GPRC:$RA, GPRC:$RB))], s_iadd>;
330 def S4ADDQi : OFormL<0x10, 0x22, "s4addq $RA,$L,$RC",
331 [(set GPRC:$RC, (add4 GPRC:$RA, immUExt8:$L))], s_iadd>;
332 def S4SUBL : OForm< 0x10, 0x0B, "s4subl $RA,$RB,$RC",
333 [(set GPRC:$RC, (intop (sub4 GPRC:$RA, GPRC:$RB)))], s_iadd>;
334 def S4SUBLi : OFormL<0x10, 0x0B, "s4subl $RA,$L,$RC",
335 [(set GPRC:$RC, (intop (sub4 GPRC:$RA, immUExt8:$L)))], s_iadd>;
336 def S4SUBQ : OForm< 0x10, 0x2B, "s4subq $RA,$RB,$RC",
337 [(set GPRC:$RC, (sub4 GPRC:$RA, GPRC:$RB))], s_iadd>;
338 def S4SUBQi : OFormL<0x10, 0x2B, "s4subq $RA,$L,$RC",
339 [(set GPRC:$RC, (sub4 GPRC:$RA, immUExt8:$L))], s_iadd>;
340 def S8ADDL : OForm< 0x10, 0x12, "s8addl $RA,$RB,$RC",
341 [(set GPRC:$RC, (intop (add8 GPRC:$RA, GPRC:$RB)))], s_iadd>;
342 def S8ADDLi : OFormL<0x10, 0x12, "s8addl $RA,$L,$RC",
343 [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8:$L)))], s_iadd>;
344 def S8ADDQ : OForm< 0x10, 0x32, "s8addq $RA,$RB,$RC",
345 [(set GPRC:$RC, (add8 GPRC:$RA, GPRC:$RB))], s_iadd>;
346 def S8ADDQi : OFormL<0x10, 0x32, "s8addq $RA,$L,$RC",
347 [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8:$L))], s_iadd>;
348 def S8SUBL : OForm< 0x10, 0x1B, "s8subl $RA,$RB,$RC",
349 [(set GPRC:$RC, (intop (sub8 GPRC:$RA, GPRC:$RB)))], s_iadd>;
350 def S8SUBLi : OFormL<0x10, 0x1B, "s8subl $RA,$L,$RC",
351 [(set GPRC:$RC, (intop (add8 GPRC:$RA, immUExt8neg:$L)))], s_iadd>;
352 def S8SUBQ : OForm< 0x10, 0x3B, "s8subq $RA,$RB,$RC",
353 [(set GPRC:$RC, (sub8 GPRC:$RA, GPRC:$RB))], s_iadd>;
354 def S8SUBQi : OFormL<0x10, 0x3B, "s8subq $RA,$L,$RC",
355 [(set GPRC:$RC, (add8 GPRC:$RA, immUExt8neg:$L))], s_iadd>;
356 def SEXTB : OForm2<0x1C, 0x00, "sextb $RB,$RC",
357 [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))], s_ishf>;
358 def SEXTW : OForm2<0x1C, 0x01, "sextw $RB,$RC",
359 [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))], s_ishf>;
360 def SL : OForm< 0x12, 0x39, "sll $RA,$RB,$RC",
361 [(set GPRC:$RC, (shl GPRC:$RA, GPRC:$RB))], s_ishf>;
362 def SLi : OFormL<0x12, 0x39, "sll $RA,$L,$RC",
363 [(set GPRC:$RC, (shl GPRC:$RA, immUExt8:$L))], s_ishf>;
364 def SRA : OForm< 0x12, 0x3C, "sra $RA,$RB,$RC",
365 [(set GPRC:$RC, (sra GPRC:$RA, GPRC:$RB))], s_ishf>;
366 def SRAi : OFormL<0x12, 0x3C, "sra $RA,$L,$RC",
367 [(set GPRC:$RC, (sra GPRC:$RA, immUExt8:$L))], s_ishf>;
368 def SRL : OForm< 0x12, 0x34, "srl $RA,$RB,$RC",
369 [(set GPRC:$RC, (srl GPRC:$RA, GPRC:$RB))], s_ishf>;
370 def SRLi : OFormL<0x12, 0x34, "srl $RA,$L,$RC",
371 [(set GPRC:$RC, (srl GPRC:$RA, immUExt8:$L))], s_ishf>;
372 def SUBL : OForm< 0x10, 0x09, "subl $RA,$RB,$RC",
373 [(set GPRC:$RC, (intop (sub GPRC:$RA, GPRC:$RB)))], s_iadd>;
374 def SUBLi : OFormL<0x10, 0x09, "subl $RA,$L,$RC",
375 [(set GPRC:$RC, (intop (add GPRC:$RA, immUExt8neg:$L)))], s_iadd>;
376 def SUBQ : OForm< 0x10, 0x29, "subq $RA,$RB,$RC",
377 [(set GPRC:$RC, (sub GPRC:$RA, GPRC:$RB))], s_iadd>;
378 def SUBQi : OFormL<0x10, 0x29, "subq $RA,$L,$RC",
379 [(set GPRC:$RC, (add GPRC:$RA, immUExt8neg:$L))], s_iadd>;
380 def UMULH : OForm< 0x13, 0x30, "umulh $RA,$RB,$RC",
381 [(set GPRC:$RC, (mulhu GPRC:$RA, GPRC:$RB))], s_imul>;
382 def UMULHi : OFormL<0x13, 0x30, "umulh $RA,$L,$RC",
383 [(set GPRC:$RC, (mulhu GPRC:$RA, immUExt8:$L))], s_imul>;
384 def XOR : OForm< 0x11, 0x40, "xor $RA,$RB,$RC",
385 [(set GPRC:$RC, (xor GPRC:$RA, GPRC:$RB))], s_ilog>;
386 def XORi : OFormL<0x11, 0x40, "xor $RA,$L,$RC",
387 [(set GPRC:$RC, (xor GPRC:$RA, immUExt8:$L))], s_ilog>;
388 //FIXME: what to do about zap? the cases it catches are very complex
389 def ZAP : OForm< 0x12, 0x30, "zap $RA,$RB,$RC", [], s_ishf>; //Zero bytes
390 //ZAPi is useless give ZAPNOTi
391 def ZAPi : OFormL<0x12, 0x30, "zap $RA,$L,$RC", [], s_ishf>; //Zero bytes
392 //FIXME: what to do about zapnot? see ZAP :)
393 def ZAPNOT : OForm< 0x12, 0x31, "zapnot $RA,$RB,$RC", [], s_ishf>; //Zero bytes not
394 def ZAPNOTi : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC",
395 [(set GPRC:$RC, (and GPRC:$RA, immZAP:$L))], s_ishf>;
398 //So this is a waste of what this instruction can do, but it still saves something
399 def CMPBGE : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC",
400 [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))], s_ilog>;
401 def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC",
402 [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), immUExt8:$L))], s_ilog>;
403 def CMPEQ : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC",
404 [(set GPRC:$RC, (seteq GPRC:$RA, GPRC:$RB))], s_iadd>;
405 def CMPEQi : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC",
406 [(set GPRC:$RC, (seteq GPRC:$RA, immUExt8:$L))], s_iadd>;
407 def CMPLE : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC",
408 [(set GPRC:$RC, (setle GPRC:$RA, GPRC:$RB))], s_iadd>;
409 def CMPLEi : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC",
410 [(set GPRC:$RC, (setle GPRC:$RA, immUExt8:$L))], s_iadd>;
411 def CMPLT : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC",
412 [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>;
413 def CMPLTi : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC",
414 [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>;
415 def CMPULE : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC",
416 [(set GPRC:$RC, (setule GPRC:$RA, GPRC:$RB))], s_iadd>;
417 def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC",
418 [(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))], s_iadd>;
419 def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC",
420 [(set GPRC:$RC, (setult GPRC:$RA, GPRC:$RB))], s_iadd>;
421 def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC",
422 [(set GPRC:$RC, (setult GPRC:$RA, immUExt8:$L))], s_iadd>;
424 //Patterns for unsupported int comparisons
425 def : Pat<(setueq GPRC:$X, GPRC:$Y), (CMPEQ GPRC:$X, GPRC:$Y)>;
426 def : Pat<(setueq GPRC:$X, immUExt8:$Y), (CMPEQi GPRC:$X, immUExt8:$Y)>;
428 def : Pat<(setugt GPRC:$X, GPRC:$Y), (CMPULT GPRC:$Y, GPRC:$X)>;
429 def : Pat<(setugt immUExt8:$X, GPRC:$Y), (CMPULTi GPRC:$Y, immUExt8:$X)>;
431 def : Pat<(setuge GPRC:$X, GPRC:$Y), (CMPULE GPRC:$Y, GPRC:$X)>;
432 def : Pat<(setuge immUExt8:$X, GPRC:$Y), (CMPULEi GPRC:$Y, immUExt8:$X)>;
434 def : Pat<(setgt GPRC:$X, GPRC:$Y), (CMPLT GPRC:$Y, GPRC:$X)>;
435 def : Pat<(setgt immUExt8:$X, GPRC:$Y), (CMPLTi GPRC:$Y, immUExt8:$X)>;
437 def : Pat<(setge GPRC:$X, GPRC:$Y), (CMPLE GPRC:$Y, GPRC:$X)>;
438 def : Pat<(setge immUExt8:$X, GPRC:$Y), (CMPLEi GPRC:$Y, immUExt8:$X)>;
440 def : Pat<(setne GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
441 def : Pat<(setne GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQi GPRC:$X, immUExt8:$Y), 0)>;
443 def : Pat<(setune GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
444 def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
447 let isReturn = 1, isTerminator = 1, noResults = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
448 def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", s_jsr>; //Return from subroutine
449 def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine
452 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1,
454 def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0",
455 [(brind GPRC:$RS)], s_jsr>; //Jump
457 let isCall = 1, noResults = 1, Ra = 26,
458 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
459 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
461 F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
462 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
463 def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", [], s_jsr>; //Branch to subroutine
465 let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
466 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
467 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
469 F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
470 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
471 def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0", s_jsr>; //Jump to subroutine
474 let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
475 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
476 def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0", s_jsr>; //Jump to div or rem
479 def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP", s_jsr>; //Jump to subroutine return
481 let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
482 def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
483 [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
484 def LDQr : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
485 [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
486 def LDL : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)",
487 [(set GPRC:$RA, (sextload (add GPRC:$RB, immSExt16:$DISP), i32))], s_ild>;
488 def LDLr : MForm<0x28, 0, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
489 [(set GPRC:$RA, (sextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32))], s_ild>;
490 def LDBU : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)",
491 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i8))], s_ild>;
492 def LDBUr : MForm<0x0A, 0, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
493 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8))], s_ild>;
494 def LDWU : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)",
495 [(set GPRC:$RA, (zextload (add GPRC:$RB, immSExt16:$DISP), i16))], s_ild>;
496 def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
497 [(set GPRC:$RA, (zextload (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16))], s_ild>;
498 def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
499 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i8)], s_ist>;
500 def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
501 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i8)], s_ist>;
502 def STW : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)",
503 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i16)], s_ist>;
504 def STWr : MForm<0x0D, 1, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
505 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i16)], s_ist>;
506 def STL : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)",
507 [(truncstore GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP), i32)], s_ist>;
508 def STLr : MForm<0x2C, 1, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
509 [(truncstore GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB), i32)], s_ist>;
510 def STQ : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)",
511 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
512 def STQr : MForm<0x2D, 1, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
513 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
516 def LDA : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)",
517 [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
518 def LDAr : MForm<0x08, 0, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
519 [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address
520 def LDAH : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)",
521 [], s_lda>; //Load address high
522 def LDAHr : MForm<0x09, 0, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
523 [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>; //Load address high
526 let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
527 def STS : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)",
528 [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
529 def STSr : MForm<0x26, 1, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
530 [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
531 def LDS : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)",
532 [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
533 def LDSr : MForm<0x22, 0, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
534 [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
536 let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
537 def STT : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)",
538 [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
539 def STTr : MForm<0x27, 1, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
540 [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
541 def LDT : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)",
542 [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
543 def LDTr : MForm<0x23, 0, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
544 [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
549 def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
550 (LDQr tconstpool:$DISP, GPRC:$RB)>;
551 def : Pat<(i64 (sextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i32)),
552 (LDLr tconstpool:$DISP, GPRC:$RB)>;
553 def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i8)),
554 (LDBUr tconstpool:$DISP, GPRC:$RB)>;
555 def : Pat<(i64 (zextload (Alpha_gprello tconstpool:$DISP, GPRC:$RB), i16)),
556 (LDWUr tconstpool:$DISP, GPRC:$RB)>;
557 def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
558 (LDAr tconstpool:$DISP, GPRC:$RB)>;
559 def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
560 (LDAHr tconstpool:$DISP, GPRC:$RB)>;
561 def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
562 (LDSr tconstpool:$DISP, GPRC:$RB)>;
563 def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
564 (LDTr tconstpool:$DISP, GPRC:$RB)>;
567 def : Pat<(i64 (Alpha_gprelhi tjumptable:$DISP, GPRC:$RB)),
568 (LDAHr tjumptable:$DISP, GPRC:$RB)>;
569 def : Pat<(i64 (Alpha_gprello tjumptable:$DISP, GPRC:$RB)),
570 (LDAr tjumptable:$DISP, GPRC:$RB)>;
574 def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i8)),
575 (LDBU immSExt16:$DISP, GPRC:$RB)>;
576 def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i16)),
577 (LDWU immSExt16:$DISP, GPRC:$RB)>;
578 def : Pat<(i64 (extload (add GPRC:$RB, immSExt16:$DISP), i32)),
579 (LDL immSExt16:$DISP, GPRC:$RB)>;
582 def : Pat<(i64 (load GPRC:$addr)),
583 (LDQ 0, GPRC:$addr)>;
584 def : Pat<(f64 (load GPRC:$addr)),
585 (LDT 0, GPRC:$addr)>;
586 def : Pat<(f32 (load GPRC:$addr)),
587 (LDS 0, GPRC:$addr)>;
588 def : Pat<(i64 (sextload GPRC:$addr, i32)),
589 (LDL 0, GPRC:$addr)>;
590 def : Pat<(i64 (zextload GPRC:$addr, i16)),
591 (LDWU 0, GPRC:$addr)>;
592 def : Pat<(i64 (zextload GPRC:$addr, i8)),
593 (LDBU 0, GPRC:$addr)>;
594 def : Pat<(i64 (extload GPRC:$addr, i8)),
595 (LDBU 0, GPRC:$addr)>;
596 def : Pat<(i64 (extload GPRC:$addr, i16)),
597 (LDWU 0, GPRC:$addr)>;
598 def : Pat<(i64 (extload GPRC:$addr, i32)),
599 (LDL 0, GPRC:$addr)>;
601 def : Pat<(store GPRC:$DATA, GPRC:$addr),
602 (STQ GPRC:$DATA, 0, GPRC:$addr)>;
603 def : Pat<(store F8RC:$DATA, GPRC:$addr),
604 (STT F8RC:$DATA, 0, GPRC:$addr)>;
605 def : Pat<(store F4RC:$DATA, GPRC:$addr),
606 (STS F4RC:$DATA, 0, GPRC:$addr)>;
607 def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i32),
608 (STL GPRC:$DATA, 0, GPRC:$addr)>;
609 def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i16),
610 (STW GPRC:$DATA, 0, GPRC:$addr)>;
611 def : Pat<(truncstore GPRC:$DATA, GPRC:$addr, i8),
612 (STB GPRC:$DATA, 0, GPRC:$addr)>;
615 //load address, rellocated gpdist form
616 let OperandList = (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in {
617 def LDAg : MForm<0x08, 0, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
618 def LDAHg : MForm<0x09, 0, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address
621 //Load quad, rellocated literal form
622 let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in
623 def LDQl : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)\t\t!literal",
624 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
625 def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
626 (LDQl texternalsym:$ext, GPRC:$RB)>;
629 def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA", s_rpcc>; //Read process cycle counter
631 //Basic Floating point ops
635 let OperandList = (ops F4RC:$RC, F4RC:$RB), Fa = 31 in
636 def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC",
637 [(set F4RC:$RC, (fsqrt F4RC:$RB))], s_fsqrts>;
639 let OperandList = (ops F4RC:$RC, F4RC:$RA, F4RC:$RB) in {
640 def ADDS : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC",
641 [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))], s_fadd>;
642 def SUBS : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC",
643 [(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))], s_fadd>;
644 def DIVS : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
645 [(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))], s_fdivs>;
646 def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
647 [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))], s_fmul>;
649 def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
650 [(set F4RC:$RC, (fcopysign F4RC:$RB, F4RC:$RA))], s_fadd>;
651 def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
652 def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
653 [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F4RC:$RA)))], s_fadd>;
658 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
659 def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC",
660 [(set F8RC:$RC, (fsqrt F8RC:$RB))], s_fsqrtt>;
662 let OperandList = (ops F8RC:$RC, F8RC:$RA, F8RC:$RB) in {
663 def ADDT : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC",
664 [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))], s_fadd>;
665 def SUBT : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC",
666 [(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))], s_fadd>;
667 def DIVT : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
668 [(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))], s_fdivt>;
669 def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
670 [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))], s_fmul>;
672 def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
673 [(set F8RC:$RC, (fcopysign F8RC:$RB, F8RC:$RA))], s_fadd>;
674 def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
675 def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
676 [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F8RC:$RA)))], s_fadd>;
678 def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", [], s_fadd>;
679 // [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
680 def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", [], s_fadd>;
681 // [(set F8RC:$RC, (setle F8RC:$RA, F8RC:$RB))]>;
682 def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", [], s_fadd>;
683 // [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>;
684 def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", [], s_fadd>;
685 // [(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))]>;
689 let OperandList = (ops F8RC:$RC, F4RC:$RA, F8RC:$RB) in {
690 def CPYSTs : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
691 [(set F8RC:$RC, (fcopysign F8RC:$RB, F4RC:$RA))], s_fadd>;
692 def CPYSNTs : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
693 [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F4RC:$RA)))], s_fadd>;
695 let OperandList = (ops F4RC:$RC, F8RC:$RA, F4RC:$RB) in {
696 def CPYSSt : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
697 [(set F4RC:$RC, (fcopysign F4RC:$RB, F8RC:$RA))], s_fadd>;
698 def CPYSESt : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
699 def CPYSNSt : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
700 [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F8RC:$RA)))], s_fadd>;
703 //conditional moves, floats
704 let OperandList = (ops F4RC:$RDEST, F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND),
705 isTwoAddress = 1 in {
706 def FCMOVEQS : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if = zero
707 def FCMOVGES : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if >= zero
708 def FCMOVGTS : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if > zero
709 def FCMOVLES : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if <= zero
710 def FCMOVLTS : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST",[], s_fcmov>; // FCMOVE if < zero
711 def FCMOVNES : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST",[], s_fcmov>; //FCMOVE if != zero
713 //conditional moves, doubles
714 let OperandList = (ops F8RC:$RDEST, F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND),
715 isTwoAddress = 1 in {
716 def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
717 def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
718 def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
719 def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
720 def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
721 def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
726 def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
727 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
728 def : Pat<(select (setoeq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
729 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
730 def : Pat<(select (setueq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
731 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
733 def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
734 (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
735 def : Pat<(select (setone F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
736 (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
737 def : Pat<(select (setune F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
738 (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
740 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
741 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
742 def : Pat<(select (setogt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
743 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
744 def : Pat<(select (setugt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
745 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
747 def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
748 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
749 def : Pat<(select (setoge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
750 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
751 def : Pat<(select (setuge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
752 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
754 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
755 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
756 def : Pat<(select (setolt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
757 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
758 def : Pat<(select (setult F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
759 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
761 def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
762 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
763 def : Pat<(select (setole F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
764 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
765 def : Pat<(select (setule F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
766 (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
769 def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
770 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
771 def : Pat<(select (setoeq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
772 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
773 def : Pat<(select (setueq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
774 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
776 def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
777 (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
778 def : Pat<(select (setone F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
779 (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
780 def : Pat<(select (setune F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
781 (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
783 def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
784 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
785 def : Pat<(select (setogt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
786 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
787 def : Pat<(select (setugt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
788 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
790 def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
791 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
792 def : Pat<(select (setoge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
793 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
794 def : Pat<(select (setuge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
795 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
797 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
798 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
799 def : Pat<(select (setolt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
800 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
801 def : Pat<(select (setult F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
802 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
804 def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
805 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
806 def : Pat<(select (setole F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
807 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
808 def : Pat<(select (setule F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
809 (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
813 let OperandList = (ops GPRC:$RC, F4RC:$RA), Fb = 31 in
814 def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[], s_ftoi>; //Floating to integer move, S_floating
815 let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in
816 def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
817 [(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))], s_ftoi>; //Floating to integer move
818 let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in
819 def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[], s_itof>; //Integer to floating move, S_floating
820 let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in
821 def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
822 [(set F8RC:$RC, (Alpha_itoft GPRC:$RA))], s_itof>; //Integer to floating move
825 let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
826 def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",
827 [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))], s_fadd>;
828 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
829 def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
830 [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))], s_fadd>;
831 let OperandList = (ops F8RC:$RC, F8RC:$RB), Fa = 31 in
832 def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
833 [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))], s_fadd>;
834 let OperandList = (ops F8RC:$RC, F4RC:$RB), Fa = 31 in
835 def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
836 [(set F8RC:$RC, (fextend F4RC:$RB))], s_fadd>;
837 let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in
838 def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
839 [(set F4RC:$RC, (fround F8RC:$RB))], s_fadd>;
842 /////////////////////////////////////////////////////////
844 /////////////////////////////////////////////////////////
845 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
847 def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;
850 def BEQ : BForm<0x39, "beq $RA,$DISP",
851 [(brcond (seteq GPRC:$RA, 0), bb:$DISP)], s_icbr>;
852 def BGE : BForm<0x3E, "bge $RA,$DISP",
853 [(brcond (setge GPRC:$RA, 0), bb:$DISP)], s_icbr>;
854 def BGT : BForm<0x3F, "bgt $RA,$DISP",
855 [(brcond (setgt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
856 def BLBC : BForm<0x38, "blbc $RA,$DISP", [], s_icbr>; //TODO: Low bit clear
857 def BLBS : BForm<0x3C, "blbs $RA,$DISP",
858 [(brcond (and GPRC:$RA, 1), bb:$DISP)], s_icbr>;
859 def BLE : BForm<0x3B, "ble $RA,$DISP",
860 [(brcond (setle GPRC:$RA, 0), bb:$DISP)], s_icbr>;
861 def BLT : BForm<0x3A, "blt $RA,$DISP",
862 [(brcond (setlt GPRC:$RA, 0), bb:$DISP)], s_icbr>;
863 def BNE : BForm<0x3D, "bne $RA,$DISP",
864 [(brcond (setne GPRC:$RA, 0), bb:$DISP)], s_icbr>;
867 def FBEQ : FBForm<0x31, "fbeq $RA,$DISP",
868 [(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
869 def FBGE : FBForm<0x36, "fbge $RA,$DISP",
870 [(brcond (setge F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
871 def FBGT : FBForm<0x37, "fbgt $RA,$DISP",
872 [(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
873 def FBLE : FBForm<0x33, "fble $RA,$DISP",
874 [(brcond (setle F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
875 def FBLT : FBForm<0x32, "fblt $RA,$DISP",
876 [(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
877 def FBNE : FBForm<0x35, "fbne $RA,$DISP",
878 [(brcond (setne F8RC:$RA, immFPZ), bb:$DISP)], s_fbr>;
881 def : Pat<(brcond GPRC:$RA, bb:$DISP), (BNE GPRC:$RA, bb:$DISP)>;
882 def : Pat<(brcond (setne GPRC:$RA, GPRC:$RB), bb:$DISP),
883 (BEQ (CMPEQ GPRC:$RA, GPRC:$RB), bb:$DISP)>;
884 def : Pat<(brcond (setne GPRC:$RA, immUExt8:$L), bb:$DISP),
885 (BEQ (CMPEQi GPRC:$RA, immUExt8:$L), bb:$DISP)>;
887 def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP),
888 (FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
889 def : Pat<(brcond (setoeq F8RC:$RA, F8RC:$RB), bb:$DISP),
890 (FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
891 def : Pat<(brcond (setueq F8RC:$RA, F8RC:$RB), bb:$DISP),
892 (FBNE (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
894 def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
895 (FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
896 def : Pat<(brcond (setolt F8RC:$RA, F8RC:$RB), bb:$DISP),
897 (FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
898 def : Pat<(brcond (setult F8RC:$RA, F8RC:$RB), bb:$DISP),
899 (FBNE (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
901 def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP),
902 (FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
903 def : Pat<(brcond (setole F8RC:$RA, F8RC:$RB), bb:$DISP),
904 (FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
905 def : Pat<(brcond (setule F8RC:$RA, F8RC:$RB), bb:$DISP),
906 (FBNE (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
908 def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),
909 (FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
910 def : Pat<(brcond (setogt F8RC:$RA, F8RC:$RB), bb:$DISP),
911 (FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
912 def : Pat<(brcond (setugt F8RC:$RA, F8RC:$RB), bb:$DISP),
913 (FBNE (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
915 def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP),
916 (FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
917 def : Pat<(brcond (setoge F8RC:$RA, F8RC:$RB), bb:$DISP),
918 (FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
919 def : Pat<(brcond (setuge F8RC:$RA, F8RC:$RB), bb:$DISP),
920 (FBNE (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
922 def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP),
923 (FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
924 def : Pat<(brcond (setone F8RC:$RA, F8RC:$RB), bb:$DISP),
925 (FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
926 def : Pat<(brcond (setune F8RC:$RA, F8RC:$RB), bb:$DISP),
927 (FBEQ (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
930 def : Pat<(brcond (setoeq F8RC:$RA, immFPZ), bb:$DISP),
931 (FBEQ F8RC:$RA,bb:$DISP)>;
932 def : Pat<(brcond (setueq F8RC:$RA, immFPZ), bb:$DISP),
933 (FBEQ F8RC:$RA,bb:$DISP)>;
935 def : Pat<(brcond (setoge F8RC:$RA, immFPZ), bb:$DISP),
936 (FBGE F8RC:$RA,bb:$DISP)>;
937 def : Pat<(brcond (setuge F8RC:$RA, immFPZ), bb:$DISP),
938 (FBGE F8RC:$RA,bb:$DISP)>;
940 def : Pat<(brcond (setogt F8RC:$RA, immFPZ), bb:$DISP),
941 (FBGT F8RC:$RA,bb:$DISP)>;
942 def : Pat<(brcond (setugt F8RC:$RA, immFPZ), bb:$DISP),
943 (FBGT F8RC:$RA,bb:$DISP)>;
945 def : Pat<(brcond (setole F8RC:$RA, immFPZ), bb:$DISP),
946 (FBLE F8RC:$RA,bb:$DISP)>;
947 def : Pat<(brcond (setule F8RC:$RA, immFPZ), bb:$DISP),
948 (FBLE F8RC:$RA,bb:$DISP)>;
950 def : Pat<(brcond (setolt F8RC:$RA, immFPZ), bb:$DISP),
951 (FBLT F8RC:$RA,bb:$DISP)>;
952 def : Pat<(brcond (setult F8RC:$RA, immFPZ), bb:$DISP),
953 (FBLT F8RC:$RA,bb:$DISP)>;
955 def : Pat<(brcond (setone F8RC:$RA, immFPZ), bb:$DISP),
956 (FBNE F8RC:$RA,bb:$DISP)>;
957 def : Pat<(brcond (setune F8RC:$RA, immFPZ), bb:$DISP),
958 (FBNE F8RC:$RA,bb:$DISP)>;
962 //S_floating : IEEE Single
963 //T_floating : IEEE Double
965 //Unused instructions
966 //Mnemonic Format Opcode Description
967 //CALL_PAL Pcd 00 Trap to PALcode
968 //ECB Mfc 18.E800 Evict cache block
969 //EXCB Mfc 18.0400 Exception barrier
970 //FETCH Mfc 18.8000 Prefetch data
971 //FETCH_M Mfc 18.A000 Prefetch data, modify intent
972 //LDL_L Mem 2A Load sign-extended longword locked
973 //LDQ_L Mem 2B Load quadword locked
974 //LDQ_U Mem 0B Load unaligned quadword
975 //MB Mfc 18.4000 Memory barrier
976 //STL_C Mem 2E Store longword conditional
977 //STQ_C Mem 2F Store quadword conditional
978 //STQ_U Mem 0F Store unaligned quadword
979 //TRAPB Mfc 18.0000 Trap barrier
980 //WH64 Mfc 18.F800 Write hint
\14 64 bytes
981 //WMB Mfc 18.4400 Write memory barrier
982 //MF_FPCR F-P 17.025 Move from FPCR
983 //MT_FPCR F-P 17.024 Move to FPCR
984 //There are in the Multimedia extentions, so let's not use them yet
985 //def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
986 //def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
987 //def MAXUB8 : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
988 //def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
989 //def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
990 //def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
991 //def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
992 //def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
993 //def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
994 //def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
995 //def PKWB : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
996 //def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
997 //def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
998 //CVTLQ F-P 17.010 Convert longword to quadword
999 //CVTQL F-P 17.030 Convert quadword to longword
1000 //def AMASK : OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture mask
1001 //def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture mask
1006 def immConst2Part : PatLeaf<(imm), [{
1007 //true if imm fits in a LDAH LDA pair
1008 int64_t val = (int64_t)N->getValue();
1009 return (val <= IMM_FULLHIGH && val >= IMM_FULLLOW);
1011 def immConst2PartInt : PatLeaf<(imm), [{
1012 //true if imm fits in a LDAH LDA pair with zeroext
1013 uint64_t uval = N->getValue();
1014 int32_t val32 = (int32_t)uval;
1015 return ((uval >> 32) == 0 && //empty upper bits
1016 val32 <= IMM_FULLHIGH);
1017 // val32 >= IMM_FULLLOW + IMM_LOW * IMM_MULT); //Always True
1020 def : Pat<(i64 immConst2Part:$imm),
1021 (LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>;
1023 def : Pat<(i64 immSExt16:$imm),
1024 (LDA immSExt16:$imm, R31)>;
1026 def : Pat<(i64 immSExt16int:$imm),
1027 (ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15)>;
1028 def : Pat<(i64 immConst2PartInt:$imm),
1029 (ZAPNOTi (LDA (LL16 (SExt32 immConst2PartInt:$imm)),
1030 (LDAH (LH16 (SExt32 immConst2PartInt:$imm)), R31)), 15)>;
1033 //TODO: I want to just define these like this!
1034 //def : Pat<(i64 0),
1036 //def : Pat<(f64 0.0),
1038 //def : Pat<(f64 -0.0),
1039 // (CPYSNT F31, F31)>;
1040 //def : Pat<(f32 0.0),
1042 //def : Pat<(f32 -0.0),
1043 // (CPYSNS F31, F31)>;
1047 def : Pat<(sext_inreg GPRC:$RB, i32),
1048 (ADDLi GPRC:$RB, 0)>;
1050 def : Pat<(fabs F8RC:$RB),
1051 (CPYST F31, F8RC:$RB)>;
1052 def : Pat<(fabs F4RC:$RB),
1053 (CPYSS F31, F4RC:$RB)>;
1054 def : Pat<(fneg F8RC:$RB),
1055 (CPYSNT F8RC:$RB, F8RC:$RB)>;
1056 def : Pat<(fneg F4RC:$RB),
1057 (CPYSNS F4RC:$RB, F4RC:$RB)>;
1059 def : Pat<(fcopysign F4RC:$A, (fneg F4RC:$B)),
1060 (CPYSNS F4RC:$B, F4RC:$A)>;
1061 def : Pat<(fcopysign F8RC:$A, (fneg F8RC:$B)),
1062 (CPYSNT F8RC:$B, F8RC:$A)>;
1063 def : Pat<(fcopysign F4RC:$A, (fneg F8RC:$B)),
1064 (CPYSNSt F8RC:$B, F4RC:$A)>;
1065 def : Pat<(fcopysign F8RC:$A, (fneg F4RC:$B)),
1066 (CPYSNTs F4RC:$B, F8RC:$A)>;
1068 //Yes, signed multiply high is ugly
1069 def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
1070 (SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
1071 (CMOVGE GPRC:$RA, R31, GPRC:$RB)))>;
1073 //Stupid crazy arithmetic stuff:
1074 def : Pat<(mul GPRC:$RA, 5), (S4ADDQ GPRC:$RA, GPRC:$RA)>;
1075 def : Pat<(mul GPRC:$RA, 3), (S4SUBQ GPRC:$RA, GPRC:$RA)>;
1077 def : Pat<(mul GPRC:$RA, immRem1:$imm),
1078 (ADDQ (SL GPRC:$RA, (nearP2X immRem1:$imm)), GPRC:$RA)>;
1079 def : Pat<(mul GPRC:$RA, immRem3:$imm),
1080 (ADDQ (SL GPRC:$RA, (nearP2X immRem3:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
1081 def : Pat<(mul GPRC:$RA, immRem5:$imm),
1082 (ADDQ (SL GPRC:$RA, (nearP2X immRem5:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
1083 def : Pat<(mul GPRC:$RA, immRem4:$imm),
1084 (S4ADDQ GPRC:$RA, (SL GPRC:$RA, (nearP2X immRem4:$imm)))>;
1085 def : Pat<(mul GPRC:$RA, immRemP2:$imm),
1086 (ADDQ (SL GPRC:$RA, (nearP2X immRemP2:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2:$imm)))>;
1088 def : Pat<(mul GPRC:$RA, immRem1n:$imm),
1089 (SUBQ (SL GPRC:$RA, (nearP2X immRem1n:$imm)), GPRC:$RA)>;
1090 def : Pat<(mul GPRC:$RA, immRem3n:$imm),
1091 (SUBQ (SL GPRC:$RA, (nearP2X immRem3n:$imm)), (S4SUBQ GPRC:$RA, GPRC:$RA))>;
1092 def : Pat<(mul GPRC:$RA, immRem5n:$imm),
1093 (SUBQ (SL GPRC:$RA, (nearP2X immRem5n:$imm)), (S4ADDQ GPRC:$RA, GPRC:$RA))>;
1094 def : Pat<(mul GPRC:$RA, immRemP2n:$imm),
1095 (SUBQ (SL GPRC:$RA, (nearP2X immRemP2n:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2n:$imm)))>;