1 //===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Here we check for potential replay traps introduced by the spiller
11 // We also align some branch targets if we can do so for free
12 //===----------------------------------------------------------------------===//
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/ADT/SetOperations.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/CommandLine.h"
24 Statistic<> nopintro("alpha-nops", "Number of nops inserted");
25 Statistic<> nopalign("alpha-nops-align",
26 "Number of nops inserted for alignment");
29 AlignAll("alpha-align-all", cl::Hidden,
30 cl::desc("Align all blocks"));
32 struct AlphaLLRPPass : public MachineFunctionPass {
33 /// Target machine description which we query for reg. names, data
36 AlphaTargetMachine &TM;
38 AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
40 virtual const char *getPassName() const {
41 return "Alpha NOP inserter";
44 bool runOnMachineFunction(MachineFunction &F) {
46 MachineInstr* prev[3] = {0,0,0};
48 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
50 MachineBasicBlock& MBB = *FI;
52 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
54 prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
56 MachineInstr *MI = I++;
57 switch (MI->getOpcode()) {
58 case Alpha::LDQ: case Alpha::LDL:
59 case Alpha::LDWU: case Alpha::LDBU:
60 case Alpha::LDT: case Alpha::LDS:
62 case Alpha::STQ: case Alpha::STL:
63 case Alpha::STW: case Alpha::STB:
64 case Alpha::STT: case Alpha::STS:
65 if (MI->getOperand(2).getReg() == Alpha::R30) {
67 && prev[0]->getOperand(2).getReg() ==
68 MI->getOperand(2).getReg()
69 && prev[0]->getOperand(1).getImmedValue() ==
70 MI->getOperand(1).getImmedValue()) {
74 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
76 Changed = true; nopintro += 1;
79 && prev[1]->getOperand(2).getReg() ==
80 MI->getOperand(2).getReg()
81 && prev[1]->getOperand(1).getImmedValue() ==
82 MI->getOperand(1).getImmedValue()) {
84 prev[1] = prev[2] = 0;
85 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
87 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
89 Changed = true; nopintro += 2;
92 && prev[2]->getOperand(2).getReg() ==
93 MI->getOperand(2).getReg()
94 && prev[2]->getOperand(1).getImmedValue() ==
95 MI->getOperand(1).getImmedValue()) {
96 prev[0] = prev[1] = prev[2] = 0;
97 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
99 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
101 BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
103 Changed = true; nopintro += 3;
123 if (ub || AlignAll) {
124 //we can align stuff for free at this point
126 BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
127 .addReg(Alpha::R31).addReg(Alpha::R31);
139 } // end of anonymous namespace
141 FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
142 return new AlphaLLRPPass(tm);