1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
37 static const int IMM_LOW = -32768;
38 static const int IMM_HIGH = 32767;
39 static const int IMM_MULT = 65536;
41 static long getUpper16(long l)
43 long y = l / IMM_MULT;
44 if (l % IMM_MULT > IMM_HIGH)
49 static long getLower16(long l)
51 long h = getUpper16(l);
52 return l - h * IMM_MULT;
55 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
56 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
62 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MI,
64 unsigned SrcReg, int FrameIdx,
65 const TargetRegisterClass *RC) const {
66 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
67 // << FrameIdx << "\n";
68 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
69 if (RC == Alpha::F4RCRegisterClass)
70 BuildMI(MBB, MI, TII.get(Alpha::STS))
71 .addReg(SrcReg, false, false, true)
72 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
73 else if (RC == Alpha::F8RCRegisterClass)
74 BuildMI(MBB, MI, TII.get(Alpha::STT))
75 .addReg(SrcReg, false, false, true)
76 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
77 else if (RC == Alpha::GPRCRegisterClass)
78 BuildMI(MBB, MI, TII.get(Alpha::STQ))
79 .addReg(SrcReg, false, false, true)
80 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
86 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 unsigned DestReg, int FrameIdx,
89 const TargetRegisterClass *RC) const {
90 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
91 // << FrameIdx << "\n";
92 if (RC == Alpha::F4RCRegisterClass)
93 BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
94 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
95 else if (RC == Alpha::F8RCRegisterClass)
96 BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
97 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
98 else if (RC == Alpha::GPRCRegisterClass)
99 BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
100 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
105 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
107 int FrameIndex) const {
108 // Make sure this is a reg-reg copy.
109 unsigned Opc = MI->getOpcode();
111 MachineInstr *NewMI = NULL;
118 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
119 if (OpNum == 0) { // move -> store
120 unsigned InReg = MI->getOperand(1).getReg();
121 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
122 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
123 NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
125 } else { // load -> move
126 unsigned OutReg = MI->getOperand(0).getReg();
127 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
128 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
129 NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
136 NewMI->copyKillDeadInfo(MI);
141 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
142 MachineBasicBlock::iterator MI,
143 unsigned DestReg, unsigned SrcReg,
144 const TargetRegisterClass *RC) const {
145 //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
146 if (RC == Alpha::GPRCRegisterClass) {
147 BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
148 } else if (RC == Alpha::F4RCRegisterClass) {
149 BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
150 } else if (RC == Alpha::F8RCRegisterClass) {
151 BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
153 cerr << "Attempt to copy register that is not GPR or FPR";
158 void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator I,
161 const MachineInstr *Orig) const {
162 MachineInstr *MI = Orig->clone();
163 MI->getOperand(0).setReg(DestReg);
167 const unsigned* AlphaRegisterInfo::getCalleeSavedRegs() const {
168 static const unsigned CalleeSavedRegs[] = {
169 Alpha::R9, Alpha::R10,
170 Alpha::R11, Alpha::R12,
171 Alpha::R13, Alpha::R14,
172 Alpha::F2, Alpha::F3,
173 Alpha::F4, Alpha::F5,
174 Alpha::F6, Alpha::F7,
175 Alpha::F8, Alpha::F9, 0
177 return CalleeSavedRegs;
180 const TargetRegisterClass* const*
181 AlphaRegisterInfo::getCalleeSavedRegClasses() const {
182 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
183 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
184 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
185 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
186 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
187 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
188 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
189 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
191 return CalleeSavedRegClasses;
194 BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
195 BitVector Reserved(getNumRegs());
196 Reserved.set(Alpha::R15);
197 Reserved.set(Alpha::R30);
198 Reserved.set(Alpha::R31);
202 //===----------------------------------------------------------------------===//
203 // Stack Frame Processing methods
204 //===----------------------------------------------------------------------===//
206 // hasFP - Return true if the specified function should have a dedicated frame
207 // pointer register. This is true if the function has variable sized allocas or
208 // if frame pointer elimination is disabled.
210 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
211 MachineFrameInfo *MFI = MF.getFrameInfo();
212 return MFI->hasVarSizedObjects();
215 void AlphaRegisterInfo::
216 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
217 MachineBasicBlock::iterator I) const {
219 // If we have a frame pointer, turn the adjcallstackup instruction into a
220 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
222 MachineInstr *Old = I;
223 uint64_t Amount = Old->getOperand(0).getImmedValue();
225 // We need to keep the stack aligned properly. To do this, we round the
226 // amount of space needed for the outgoing arguments up to the next
227 // alignment boundary.
228 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
229 Amount = (Amount+Align-1)/Align*Align;
232 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
233 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
234 .addImm(-Amount).addReg(Alpha::R30);
236 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
237 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
238 .addImm(Amount).addReg(Alpha::R30);
241 // Replace the pseudo instruction with a new instruction...
249 //Alpha has a slightly funny stack:
252 //fixed locals (and spills, callee saved, etc)
257 void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
258 RegScavenger *RS) const {
260 MachineInstr &MI = *II;
261 MachineBasicBlock &MBB = *MI.getParent();
262 MachineFunction &MF = *MBB.getParent();
265 while (!MI.getOperand(i).isFrameIndex()) {
267 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
270 int FrameIndex = MI.getOperand(i).getFrameIndex();
272 // Add the base register of R30 (SP) or R15 (FP).
273 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
275 // Now add the frame object offset to the offset from the virtual frame index.
276 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
278 DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
280 Offset += MF.getFrameInfo()->getStackSize();
282 DOUT << "Corrected Offset " << Offset
283 << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
285 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
286 DOUT << "Unconditionally using R28 for evil purposes Offset: "
288 //so in this case, we need to use a temporary register, and move the
289 //original inst off the SP/FP
291 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
292 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
294 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
295 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
298 MI.getOperand(i).ChangeToImmediate(Offset);
303 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
304 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
305 MachineBasicBlock::iterator MBBI = MBB.begin();
306 MachineFrameInfo *MFI = MF.getFrameInfo();
309 static int curgpdist = 0;
312 BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
313 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
314 .addReg(Alpha::R27).addImm(++curgpdist);
315 BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
316 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
317 .addReg(Alpha::R29).addImm(curgpdist);
319 //evil const_cast until MO stuff setup to handle const
320 BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
321 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
323 // Get the number of bytes to allocate from the FrameInfo
324 long NumBytes = MFI->getStackSize();
327 NumBytes += 8; //reserve space for the old FP
329 // Do we need to allocate space on the stack?
330 if (NumBytes == 0) return;
332 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
333 NumBytes = (NumBytes+Align-1)/Align*Align;
335 // Update frame info to pretend that this is part of the stack...
336 MFI->setStackSize(NumBytes);
338 // adjust stack pointer: r30 -= numbytes
339 NumBytes = -NumBytes;
340 if (NumBytes >= IMM_LOW) {
341 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
343 } else if (getUpper16(NumBytes) >= IMM_LOW) {
344 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
346 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
349 cerr << "Too big a stack frame at " << NumBytes << "\n";
353 //now if we need to, save the old FP and set the new
356 BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
357 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
358 //this must be the last instr in the prolog
359 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
360 .addReg(Alpha::R30).addReg(Alpha::R30);
365 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
366 MachineBasicBlock &MBB) const {
367 const MachineFrameInfo *MFI = MF.getFrameInfo();
368 MachineBasicBlock::iterator MBBI = prior(MBB.end());
369 assert(MBBI->getOpcode() == Alpha::RETDAG ||
370 MBBI->getOpcode() == Alpha::RETDAGp
371 && "Can only insert epilog into returning blocks");
375 // Get the number of bytes allocated from the FrameInfo...
376 long NumBytes = MFI->getStackSize();
378 //now if we need to, restore the old FP
381 //copy the FP into the SP (discards allocas)
382 BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
385 BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
390 if (NumBytes <= IMM_HIGH) {
391 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
393 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
394 BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
395 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
396 BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
397 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
399 cerr << "Too big a stack frame at " << NumBytes << "\n";
405 unsigned AlphaRegisterInfo::getRARegister() const {
406 assert(0 && "What is the return address register");
410 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
411 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
414 unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
415 assert(0 && "What is the exception register");
419 unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
420 assert(0 && "What is the exception handler register");
424 #include "AlphaGenRegisterInfo.inc"
426 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
428 std::string s(RegisterDescriptors[reg].Name);