1 //===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Alpha implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "AlphaRegisterInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/Type.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/STLExtras.h"
36 static const int IMM_LOW = -32768;
37 static const int IMM_HIGH = 32767;
38 static const int IMM_MULT = 65536;
40 static long getUpper16(long l)
42 long y = l / IMM_MULT;
43 if (l % IMM_MULT > IMM_HIGH)
48 static long getLower16(long l)
50 long h = getUpper16(l);
51 return l - h * IMM_MULT;
60 AlphaRegisterInfo::AlphaRegisterInfo()
61 : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP)
66 AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator MI,
68 unsigned SrcReg, int FrameIdx,
69 const TargetRegisterClass *RC) const {
70 //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
71 //<< FrameIdx << "\n";
72 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
73 if (RC == Alpha::F4RCRegisterClass)
74 BuildMI(MBB, MI, Alpha::STS, 3)
75 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
76 else if (RC == Alpha::F8RCRegisterClass)
77 BuildMI(MBB, MI, Alpha::STT, 3)
78 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
79 else if (RC == Alpha::GPRCRegisterClass)
80 BuildMI(MBB, MI, Alpha::STQ, 3)
81 .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
87 AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI,
89 unsigned DestReg, int FrameIdx,
90 const TargetRegisterClass *RC) const {
91 //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
92 //<< FrameIdx << "\n";
93 if (RC == Alpha::F4RCRegisterClass)
94 BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
95 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
96 else if (RC == Alpha::F8RCRegisterClass)
97 BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
98 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
99 else if (RC == Alpha::GPRCRegisterClass)
100 BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
101 .addFrameIndex(FrameIdx).addReg(Alpha::F31);
106 MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
108 int FrameIndex) const {
109 // Make sure this is a reg-reg copy.
110 unsigned Opc = MI->getOpcode();
118 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
119 if (OpNum == 0) { // move -> store
120 unsigned InReg = MI->getOperand(1).getReg();
121 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
122 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
123 return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
125 } else { // load -> move
126 unsigned OutReg = MI->getOperand(0).getReg();
127 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
128 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
129 return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex)
139 void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator MI,
141 unsigned DestReg, unsigned SrcReg,
142 const TargetRegisterClass *RC) const {
143 // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
144 if (RC == Alpha::GPRCRegisterClass) {
145 BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
146 } else if (RC == Alpha::F4RCRegisterClass) {
147 BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
148 } else if (RC == Alpha::F8RCRegisterClass) {
149 BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
151 std::cerr << "Attempt to copy register that is not GPR or FPR";
156 const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
157 static const unsigned CalleeSaveRegs[] = {
158 Alpha::R9, Alpha::R10,
159 Alpha::R11, Alpha::R12,
160 Alpha::R13, Alpha::R14,
161 Alpha::F2, Alpha::F3,
162 Alpha::F4, Alpha::F5,
163 Alpha::F6, Alpha::F7,
164 Alpha::F8, Alpha::F9, 0
166 return CalleeSaveRegs;
169 const TargetRegisterClass* const*
170 AlphaRegisterInfo::getCalleeSaveRegClasses() const {
171 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
172 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
173 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
174 &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
175 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
176 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
177 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
178 &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
180 return CalleeSaveRegClasses;
183 //===----------------------------------------------------------------------===//
184 // Stack Frame Processing methods
185 //===----------------------------------------------------------------------===//
187 // hasFP - Return true if the specified function should have a dedicated frame
188 // pointer register. This is true if the function has variable sized allocas or
189 // if frame pointer elimination is disabled.
191 static bool hasFP(const MachineFunction &MF) {
192 MachineFrameInfo *MFI = MF.getFrameInfo();
193 return MFI->hasVarSizedObjects();
196 void AlphaRegisterInfo::
197 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
198 MachineBasicBlock::iterator I) const {
200 // If we have a frame pointer, turn the adjcallstackup instruction into a
201 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
203 MachineInstr *Old = I;
204 uint64_t Amount = Old->getOperand(0).getImmedValue();
206 // We need to keep the stack aligned properly. To do this, we round the
207 // amount of space needed for the outgoing arguments up to the next
208 // alignment boundary.
209 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
210 Amount = (Amount+Align-1)/Align*Align;
213 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
214 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
215 .addImm(-Amount).addReg(Alpha::R30);
217 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
218 New=BuildMI(Alpha::LDA, 2, Alpha::R30)
219 .addImm(Amount).addReg(Alpha::R30);
222 // Replace the pseudo instruction with a new instruction...
230 //Alpha has a slightly funny stack:
233 //fixed locals (and spills, callee saved, etc)
239 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
241 MachineInstr &MI = *II;
242 MachineBasicBlock &MBB = *MI.getParent();
243 MachineFunction &MF = *MBB.getParent();
246 while (!MI.getOperand(i).isFrameIndex()) {
248 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
251 int FrameIndex = MI.getOperand(i).getFrameIndex();
253 // Add the base register of R30 (SP) or R15 (FP).
254 MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
256 // Now add the frame object offset to the offset from the virtual frame index.
257 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
259 DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
261 Offset += MF.getFrameInfo()->getStackSize();
263 DEBUG(std::cerr << "Corrected Offset " << Offset <<
264 " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
266 if (Offset > IMM_HIGH || Offset < IMM_LOW) {
267 DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
269 //so in this case, we need to use a temporary register, and move the
270 //original inst off the SP/FP
272 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
273 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
275 MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
276 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
279 MI.getOperand(i).ChangeToImmediate(Offset);
284 void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
285 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
286 MachineBasicBlock::iterator MBBI = MBB.begin();
287 MachineFrameInfo *MFI = MF.getFrameInfo();
290 static int curgpdist = 0;
293 BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
294 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
295 .addReg(Alpha::R27).addImm(++curgpdist);
296 BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
297 .addGlobalAddress(const_cast<Function*>(MF.getFunction()))
298 .addReg(Alpha::R29).addImm(curgpdist);
300 //evil const_cast until MO stuff setup to handle const
301 BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
302 .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
304 // Get the number of bytes to allocate from the FrameInfo
305 long NumBytes = MFI->getStackSize();
307 if (MFI->hasCalls() && !FP) {
308 // We reserve argument space for call sites in the function immediately on
309 // entry to the current function. This eliminates the need for add/sub
310 // brackets around call sites.
311 //If there is a frame pointer, then we don't do this
312 NumBytes += MFI->getMaxCallFrameSize();
313 DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
314 << " to the stack due to calls\n");
318 NumBytes += 8; //reserve space for the old FP
320 // Do we need to allocate space on the stack?
321 if (NumBytes == 0) return;
323 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
324 NumBytes = (NumBytes+Align-1)/Align*Align;
326 // Update frame info to pretend that this is part of the stack...
327 MFI->setStackSize(NumBytes);
329 // adjust stack pointer: r30 -= numbytes
330 NumBytes = -NumBytes;
331 if (NumBytes >= IMM_LOW) {
332 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
334 } else if (getUpper16(NumBytes) >= IMM_LOW) {
335 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
337 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
340 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
344 //now if we need to, save the old FP and set the new
347 BuildMI(MBB, MBBI, Alpha::STQ, 3)
348 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
349 //this must be the last instr in the prolog
350 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15)
351 .addReg(Alpha::R30).addReg(Alpha::R30);
356 void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
357 MachineBasicBlock &MBB) const {
358 const MachineFrameInfo *MFI = MF.getFrameInfo();
359 MachineBasicBlock::iterator MBBI = prior(MBB.end());
360 assert(MBBI->getOpcode() == Alpha::RETDAG ||
361 MBBI->getOpcode() == Alpha::RETDAGp
362 && "Can only insert epilog into returning blocks");
366 // Get the number of bytes allocated from the FrameInfo...
367 long NumBytes = MFI->getStackSize();
369 //now if we need to, restore the old FP
372 //copy the FP into the SP (discards allocas)
373 BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15)
376 BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
381 if (NumBytes <= IMM_HIGH) {
382 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
384 } else if (getUpper16(NumBytes) <= IMM_HIGH) {
385 BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
386 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
387 BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
388 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
390 std::cerr << "Too big a stack frame at " << NumBytes << "\n";
396 unsigned AlphaRegisterInfo::getRARegister() const {
397 assert(0 && "What is the return address register");
401 unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
402 return hasFP(MF) ? Alpha::R15 : Alpha::R30;
405 #include "AlphaGenRegisterInfo.inc"
407 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
409 std::string s(RegisterDescriptors[reg].Name);