1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "BPFISelLowering.h"
17 #include "BPFTargetMachine.h"
18 #include "BPFSubtarget.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
35 #define DEBUG_TYPE "bpf-lower"
39 // Diagnostic information for unimplemented or unsupported feature reporting.
40 class DiagnosticInfoUnsupported : public DiagnosticInfo {
42 // Debug location where this diagnostic is triggered.
44 const Twine &Description;
50 static int getKindID() {
52 KindID = llvm::getNextAvailablePluginDiagnosticKind();
57 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
59 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
60 Description(Desc), Fn(Fn), Value(Value) {}
62 void print(DiagnosticPrinter &DP) const override {
64 raw_string_ostream OS(Str);
67 auto DIL = DLoc.get();
68 StringRef Filename = DIL->getFilename();
69 unsigned Line = DIL->getLine();
70 unsigned Column = DIL->getColumn();
71 OS << Filename << ':' << Line << ':' << Column << ' ';
74 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
83 static bool classof(const DiagnosticInfo *DI) {
84 return DI->getKind() == getKindID();
88 int DiagnosticInfoUnsupported::KindID = 0;
91 BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
92 const BPFSubtarget &STI)
93 : TargetLowering(TM) {
95 // Set up the register classes.
96 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
98 // Compute derived properties from the register classes
99 computeRegisterProperties(STI.getRegisterInfo());
101 setStackPointerRegisterToSaveRestore(BPF::R11);
103 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
104 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
105 setOperationAction(ISD::BRIND, MVT::Other, Expand);
106 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
107 setOperationAction(ISD::SETCC, MVT::i64, Expand);
108 setOperationAction(ISD::SELECT, MVT::i64, Expand);
109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
111 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
113 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
114 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
115 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
119 setOperationAction(ISD::SREM, MVT::i64, Expand);
120 setOperationAction(ISD::UREM, MVT::i64, Expand);
122 setOperationAction(ISD::MULHU, MVT::i64, Expand);
123 setOperationAction(ISD::MULHS, MVT::i64, Expand);
124 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
127 setOperationAction(ISD::ADDC, MVT::i64, Expand);
128 setOperationAction(ISD::ADDE, MVT::i64, Expand);
129 setOperationAction(ISD::SUBC, MVT::i64, Expand);
130 setOperationAction(ISD::SUBE, MVT::i64, Expand);
132 setOperationAction(ISD::ROTR, MVT::i64, Expand);
133 setOperationAction(ISD::ROTL, MVT::i64, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
136 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
138 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
139 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
140 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
141 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
142 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
149 // Extended load operations for i1 types must be promoted
150 for (MVT VT : MVT::integer_valuetypes()) {
151 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
152 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
153 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
155 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
156 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
160 setBooleanContents(ZeroOrOneBooleanContent);
162 // Function alignments (log2)
163 setMinFunctionAlignment(3);
164 setPrefFunctionAlignment(3);
166 // inline memcpy() for kernel to see explicit copy
167 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
168 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
169 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
172 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
173 switch (Op.getOpcode()) {
175 return LowerBR_CC(Op, DAG);
176 case ISD::GlobalAddress:
177 return LowerGlobalAddress(Op, DAG);
179 return LowerSELECT_CC(Op, DAG);
181 llvm_unreachable("unimplemented operand");
185 // Calling Convention Implementation
186 #include "BPFGenCallingConv.inc"
188 SDValue BPFTargetLowering::LowerFormalArguments(
189 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
191 SmallVectorImpl<SDValue> &InVals) const {
194 llvm_unreachable("Unsupported calling convention");
196 case CallingConv::Fast:
200 MachineFunction &MF = DAG.getMachineFunction();
201 MachineRegisterInfo &RegInfo = MF.getRegInfo();
203 // Assign locations to all of the incoming arguments.
204 SmallVector<CCValAssign, 16> ArgLocs;
205 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
206 CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
208 for (auto &VA : ArgLocs) {
210 // Arguments passed in registers
211 EVT RegVT = VA.getLocVT();
212 switch (RegVT.getSimpleVT().SimpleTy) {
214 errs() << "LowerFormalArguments Unhandled argument type: "
215 << RegVT.getSimpleVT().SimpleTy << '\n';
219 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
220 RegInfo.addLiveIn(VA.getLocReg(), VReg);
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
223 // If this is an 8/16/32-bit value, it is really passed promoted to 64
224 // bits. Insert an assert[sz]ext to capture this, then truncate to the
226 if (VA.getLocInfo() == CCValAssign::SExt)
227 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
228 DAG.getValueType(VA.getValVT()));
229 else if (VA.getLocInfo() == CCValAssign::ZExt)
230 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
231 DAG.getValueType(VA.getValVT()));
233 if (VA.getLocInfo() != CCValAssign::Full)
234 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
236 InVals.push_back(ArgValue);
239 DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
240 "defined with too many args", SDValue());
241 DAG.getContext()->diagnose(Err);
245 if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
246 DiagnosticInfoUnsupported Err(
247 DL, *MF.getFunction(),
248 "functions with VarArgs or StructRet are not supported", SDValue());
249 DAG.getContext()->diagnose(Err);
255 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
256 SmallVectorImpl<SDValue> &InVals) const {
257 SelectionDAG &DAG = CLI.DAG;
258 auto &Outs = CLI.Outs;
259 auto &OutVals = CLI.OutVals;
261 SDValue Chain = CLI.Chain;
262 SDValue Callee = CLI.Callee;
263 bool &IsTailCall = CLI.IsTailCall;
264 CallingConv::ID CallConv = CLI.CallConv;
265 bool IsVarArg = CLI.IsVarArg;
266 MachineFunction &MF = DAG.getMachineFunction();
268 // BPF target does not support tail call optimization.
273 report_fatal_error("Unsupported calling convention");
274 case CallingConv::Fast:
279 // Analyze operands of the call, assigning locations to each operand.
280 SmallVector<CCValAssign, 16> ArgLocs;
281 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
283 CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
285 unsigned NumBytes = CCInfo.getNextStackOffset();
287 if (Outs.size() >= 6) {
288 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
289 "too many args to ", Callee);
290 DAG.getContext()->diagnose(Err);
293 for (auto &Arg : Outs) {
294 ISD::ArgFlagsTy Flags = Arg.Flags;
295 if (!Flags.isByVal())
298 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(),
299 "pass by value not supported ", Callee);
300 DAG.getContext()->diagnose(Err);
303 auto PtrVT = getPointerTy(MF.getDataLayout());
304 Chain = DAG.getCALLSEQ_START(
305 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
307 SmallVector<std::pair<unsigned, SDValue>, 5> RegsToPass;
309 // Walk arg assignments
310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
311 CCValAssign &VA = ArgLocs[i];
312 SDValue Arg = OutVals[i];
314 // Promote the value if needed.
315 switch (VA.getLocInfo()) {
317 llvm_unreachable("Unknown loc info");
318 case CCValAssign::Full:
320 case CCValAssign::SExt:
321 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
323 case CCValAssign::ZExt:
324 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
326 case CCValAssign::AExt:
327 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
331 // Push arguments into RegsToPass vector
333 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
335 llvm_unreachable("call arg pass bug");
340 // Build a sequence of copy-to-reg nodes chained together with token chain and
341 // flag operands which copy the outgoing args into registers. The InFlag in
342 // necessary since all emitted instructions must be stuck together.
343 for (auto &Reg : RegsToPass) {
344 Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
345 InFlag = Chain.getValue(1);
348 // If the callee is a GlobalAddress node (quite common, every direct call is)
349 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
350 // Likewise ExternalSymbol -> TargetExternalSymbol.
351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
352 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
354 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
355 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
357 // Returns a chain & a flag for retval copy to use.
358 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
359 SmallVector<SDValue, 8> Ops;
360 Ops.push_back(Chain);
361 Ops.push_back(Callee);
363 // Add argument registers to the end of the list so that they are
364 // known live into the call.
365 for (auto &Reg : RegsToPass)
366 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
368 if (InFlag.getNode())
369 Ops.push_back(InFlag);
371 Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
372 InFlag = Chain.getValue(1);
374 // Create the CALLSEQ_END node.
375 Chain = DAG.getCALLSEQ_END(
376 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
377 DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
378 InFlag = Chain.getValue(1);
380 // Handle result values, copying them out of physregs into vregs that we
382 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
387 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
389 const SmallVectorImpl<ISD::OutputArg> &Outs,
390 const SmallVectorImpl<SDValue> &OutVals,
391 SDLoc DL, SelectionDAG &DAG) const {
393 // CCValAssign - represent the assignment of the return value to a location
394 SmallVector<CCValAssign, 16> RVLocs;
395 MachineFunction &MF = DAG.getMachineFunction();
397 // CCState - Info about the registers and stack slot.
398 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
400 if (MF.getFunction()->getReturnType()->isAggregateType()) {
401 DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
402 "only integer returns supported", SDValue());
403 DAG.getContext()->diagnose(Err);
406 // Analize return values.
407 CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
410 SmallVector<SDValue, 4> RetOps(1, Chain);
412 // Copy the result values into the output registers.
413 for (unsigned i = 0; i != RVLocs.size(); ++i) {
414 CCValAssign &VA = RVLocs[i];
415 assert(VA.isRegLoc() && "Can only return in registers!");
417 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
419 // Guarantee that all emitted copies are stuck together,
420 // avoiding something bad.
421 Flag = Chain.getValue(1);
422 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
425 unsigned Opc = BPFISD::RET_FLAG;
426 RetOps[0] = Chain; // Update chain.
428 // Add the flag if we have it.
430 RetOps.push_back(Flag);
432 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
435 SDValue BPFTargetLowering::LowerCallResult(
436 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
437 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
438 SmallVectorImpl<SDValue> &InVals) const {
440 MachineFunction &MF = DAG.getMachineFunction();
441 // Assign locations to each value returned by this call.
442 SmallVector<CCValAssign, 16> RVLocs;
443 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
445 if (Ins.size() >= 2) {
446 DiagnosticInfoUnsupported Err(DL, *MF.getFunction(),
447 "only small returns supported", SDValue());
448 DAG.getContext()->diagnose(Err);
451 CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
453 // Copy all of the result registers out of their specified physreg.
454 for (auto &Val : RVLocs) {
455 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
456 Val.getValVT(), InFlag).getValue(1);
457 InFlag = Chain.getValue(2);
458 InVals.push_back(Chain.getValue(0));
464 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
472 CC = ISD::getSetCCSwappedOperands(CC);
478 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
479 SDValue Chain = Op.getOperand(0);
480 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
481 SDValue LHS = Op.getOperand(2);
482 SDValue RHS = Op.getOperand(3);
483 SDValue Dest = Op.getOperand(4);
486 NegateCC(LHS, RHS, CC);
488 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
489 DAG.getConstant(CC, DL, MVT::i64), Dest);
492 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
493 SDValue LHS = Op.getOperand(0);
494 SDValue RHS = Op.getOperand(1);
495 SDValue TrueV = Op.getOperand(2);
496 SDValue FalseV = Op.getOperand(3);
497 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
500 NegateCC(LHS, RHS, CC);
502 SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
504 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
505 SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
507 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
510 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
511 switch ((BPFISD::NodeType)Opcode) {
512 case BPFISD::FIRST_NUMBER:
514 case BPFISD::RET_FLAG:
515 return "BPFISD::RET_FLAG";
517 return "BPFISD::CALL";
518 case BPFISD::SELECT_CC:
519 return "BPFISD::SELECT_CC";
521 return "BPFISD::BR_CC";
522 case BPFISD::Wrapper:
523 return "BPFISD::Wrapper";
528 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
529 SelectionDAG &DAG) const {
531 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
532 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
534 return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
538 BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
539 MachineBasicBlock *BB) const {
540 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
541 DebugLoc DL = MI->getDebugLoc();
543 assert(MI->getOpcode() == BPF::Select && "Unexpected instr type to insert");
545 // To "insert" a SELECT instruction, we actually have to insert the diamond
546 // control-flow pattern. The incoming instruction knows the destination vreg
547 // to set, the condition code register to branch on, the true/false values to
548 // select between, and a branch opcode to use.
549 const BasicBlock *LLVM_BB = BB->getBasicBlock();
550 MachineFunction::iterator I = ++BB->getIterator();
555 // jmp_XX r1, r2 goto Copy1MBB
556 // fallthrough --> Copy0MBB
557 MachineBasicBlock *ThisMBB = BB;
558 MachineFunction *F = BB->getParent();
559 MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
560 MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
562 F->insert(I, Copy0MBB);
563 F->insert(I, Copy1MBB);
564 // Update machine-CFG edges by transferring all successors of the current
565 // block to the new block which will contain the Phi node for the select.
566 Copy1MBB->splice(Copy1MBB->begin(), BB,
567 std::next(MachineBasicBlock::iterator(MI)), BB->end());
568 Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
569 // Next, add the true and fallthrough blocks as its successors.
570 BB->addSuccessor(Copy0MBB);
571 BB->addSuccessor(Copy1MBB);
573 // Insert Branch if Flag
574 unsigned LHS = MI->getOperand(1).getReg();
575 unsigned RHS = MI->getOperand(2).getReg();
576 int CC = MI->getOperand(3).getImm();
579 BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
585 BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
591 BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
597 BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
603 BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
609 BuildMI(BB, DL, TII.get(BPF::JNE_rr))
615 report_fatal_error("unimplemented select CondCode " + Twine(CC));
620 // # fallthrough to Copy1MBB
623 // Update machine-CFG edges
624 BB->addSuccessor(Copy1MBB);
627 // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
630 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI->getOperand(0).getReg())
631 .addReg(MI->getOperand(5).getReg())
633 .addReg(MI->getOperand(4).getReg())
636 MI->eraseFromParent(); // The pseudo instruction is gone now.