1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the BPF instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "BPFInstrFormats.td"
16 // Instruction Operands and Patterns
18 // These are target-independent nodes, but have target-specific formats.
19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
26 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27 SDTCisVT<3, OtherVT>]>;
28 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
31 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
34 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
37 [SDNPHasChain, SDNPOutGlue]>;
38 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
39 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
40 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
41 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
43 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
44 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
46 def brtarget : Operand<OtherVT>;
47 def calltarget : Operand<i64>;
49 def u64imm : Operand<i64> {
50 let PrintMethod = "printImm64Operand";
53 def i64immSExt32 : PatLeaf<(imm),
54 [{return isInt<32>(N->getSExtValue()); }]>;
57 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [frameindex], []>;
60 def MEMri : Operand<i64> {
61 let PrintMethod = "printMemOperand";
62 let EncoderMethod = "getMemoryOpValue";
63 let MIOperandInfo = (ops GPR, i16imm);
66 // Conditional code predicates - used for pattern matching for jump instructions
67 def BPF_CC_EQ : PatLeaf<(imm),
68 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
69 def BPF_CC_NE : PatLeaf<(imm),
70 [{return (N->getZExtValue() == ISD::SETNE);}]>;
71 def BPF_CC_GE : PatLeaf<(imm),
72 [{return (N->getZExtValue() == ISD::SETGE);}]>;
73 def BPF_CC_GT : PatLeaf<(imm),
74 [{return (N->getZExtValue() == ISD::SETGT);}]>;
75 def BPF_CC_GTU : PatLeaf<(imm),
76 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
77 def BPF_CC_GEU : PatLeaf<(imm),
78 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
81 class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
82 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
83 !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"),
84 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
92 let Inst{59} = BPFSrc;
93 let Inst{55-52} = src;
94 let Inst{51-48} = dst;
95 let Inst{47-32} = BrDst;
99 let BPFClass = 5; // BPF_JMP
102 class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
103 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
104 !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
105 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
112 let Inst{63-60} = op;
113 let Inst{59} = BPFSrc;
114 let Inst{51-48} = dst;
115 let Inst{47-32} = BrDst;
116 let Inst{31-0} = imm;
120 let BPFClass = 5; // BPF_JMP
123 multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
124 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
125 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
128 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
129 // cmp+goto instructions
130 defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
131 defm JUGT : J<0x2, "jgt", BPF_CC_GTU>;
132 defm JUGE : J<0x3, "jge", BPF_CC_GEU>;
133 defm JNE : J<0x5, "jne", BPF_CC_NE>;
134 defm JSGT : J<0x6, "jsgt", BPF_CC_GT>;
135 defm JSGE : J<0x7, "jsge", BPF_CC_GE>;
139 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
140 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
141 !strconcat(OpcodeStr, "i\t$dst, $imm"),
142 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
148 let Inst{63-60} = op;
149 let Inst{59} = BPFSrc;
150 let Inst{51-48} = dst;
151 let Inst{31-0} = imm;
155 let BPFClass = 7; // BPF_ALU64
158 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
159 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
160 !strconcat(OpcodeStr, "\t$dst, $src"),
161 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
167 let Inst{63-60} = op;
168 let Inst{59} = BPFSrc;
169 let Inst{55-52} = src;
170 let Inst{51-48} = dst;
174 let BPFClass = 7; // BPF_ALU64
177 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
178 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
179 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
182 let Constraints = "$dst = $src2" in {
183 let isAsCheapAsAMove = 1 in {
184 defm ADD : ALU<0x0, "add", add>;
185 defm SUB : ALU<0x1, "sub", sub>;
186 defm OR : ALU<0x4, "or", or>;
187 defm AND : ALU<0x5, "and", and>;
188 defm SLL : ALU<0x6, "sll", shl>;
189 defm SRL : ALU<0x7, "srl", srl>;
190 defm XOR : ALU<0xa, "xor", xor>;
191 defm SRA : ALU<0xc, "sra", sra>;
193 defm MUL : ALU<0x2, "mul", mul>;
194 defm DIV : ALU<0x3, "div", udiv>;
197 class MOV_RR<string OpcodeStr>
198 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
199 !strconcat(OpcodeStr, "\t$dst, $src"),
206 let Inst{63-60} = op;
207 let Inst{59} = BPFSrc;
208 let Inst{55-52} = src;
209 let Inst{51-48} = dst;
211 let op = 0xb; // BPF_MOV
212 let BPFSrc = 1; // BPF_X
213 let BPFClass = 7; // BPF_ALU64
216 class MOV_RI<string OpcodeStr>
217 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
218 !strconcat(OpcodeStr, "\t$dst, $imm"),
219 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
225 let Inst{63-60} = op;
226 let Inst{59} = BPFSrc;
227 let Inst{51-48} = dst;
228 let Inst{31-0} = imm;
230 let op = 0xb; // BPF_MOV
231 let BPFSrc = 0; // BPF_K
232 let BPFClass = 7; // BPF_ALU64
234 def MOV_rr : MOV_RR<"mov">;
235 def MOV_ri : MOV_RI<"mov">;
237 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
238 : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
239 !strconcat(OpcodeStr, "\t$dst, $imm"),
240 [(set GPR:$dst, (i64 imm:$imm))]> {
247 let Inst{63-61} = mode;
248 let Inst{60-59} = size;
249 let Inst{51-48} = dst;
250 let Inst{55-52} = Pseudo;
252 let Inst{31-0} = imm{31-0};
254 let mode = 0; // BPF_IMM
255 let size = 3; // BPF_DW
256 let BPFClass = 0; // BPF_LD
258 def LD_imm64 : LD_IMM64<0, "ld_64">;
261 : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
262 "ld_pseudo\t$dst, $pseudo, $imm",
263 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
271 let Inst{63-61} = mode;
272 let Inst{60-59} = size;
273 let Inst{51-48} = dst;
274 let Inst{55-52} = pseudo;
276 let Inst{31-0} = imm{31-0};
278 let mode = 0; // BPF_IMM
279 let size = 3; // BPF_DW
280 let BPFClass = 0; // BPF_LD
283 // STORE instructions
284 class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
285 : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
286 !strconcat(OpcodeStr, "\t$addr, $src"), Pattern> {
292 let Inst{63-61} = mode;
293 let Inst{60-59} = size;
294 let Inst{51-48} = addr{19-16}; // base reg
295 let Inst{55-52} = src;
296 let Inst{47-32} = addr{15-0}; // offset
298 let mode = 3; // BPF_MEM
300 let BPFClass = 3; // BPF_STX
303 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
304 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
306 def STW : STOREi64<0x0, "stw", truncstorei32>;
307 def STH : STOREi64<0x1, "sth", truncstorei16>;
308 def STB : STOREi64<0x2, "stb", truncstorei8>;
309 def STD : STOREi64<0x3, "std", store>;
312 class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
313 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
314 !strconcat(OpcodeStr, "\t$dst, $addr"), Pattern> {
320 let Inst{63-61} = mode;
321 let Inst{60-59} = size;
322 let Inst{51-48} = dst;
323 let Inst{55-52} = addr{19-16};
324 let Inst{47-32} = addr{15-0};
326 let mode = 3; // BPF_MEM
328 let BPFClass = 1; // BPF_LDX
331 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
332 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
334 def LDW : LOADi64<0x0, "ldw", zextloadi32>;
335 def LDH : LOADi64<0x1, "ldh", zextloadi16>;
336 def LDB : LOADi64<0x2, "ldb", zextloadi8>;
337 def LDD : LOADi64<0x3, "ldd", load>;
339 class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
340 : InstBPF<(outs), (ins brtarget:$BrDst),
341 !strconcat(OpcodeStr, "\t$BrDst"), Pattern> {
346 let Inst{63-60} = op;
347 let Inst{59} = BPFSrc;
348 let Inst{47-32} = BrDst;
352 let BPFClass = 5; // BPF_JMP
355 class CALL<string OpcodeStr>
356 : InstBPF<(outs), (ins calltarget:$BrDst),
357 !strconcat(OpcodeStr, "\t$BrDst"), []> {
362 let Inst{63-60} = op;
363 let Inst{59} = BPFSrc;
364 let Inst{31-0} = BrDst;
366 let op = 8; // BPF_CALL
368 let BPFClass = 5; // BPF_JMP
372 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
373 def JMP : BRANCH<0x0, "jmp", [(br bb:$BrDst)]>;
377 let isCall=1, hasDelaySlot=0, Uses = [R11],
378 // Potentially clobbered registers
379 Defs = [R0, R1, R2, R3, R4, R5] in {
380 def JAL : CALL<"call">;
383 class NOP_I<string OpcodeStr>
384 : InstBPF<(outs), (ins i32imm:$imm),
385 !strconcat(OpcodeStr, "\t$imm"), []> {
392 let Inst{63-60} = op;
393 let Inst{59} = BPFSrc;
394 let Inst{55-52} = src;
395 let Inst{51-48} = dst;
397 let op = 0xb; // BPF_MOV
398 let BPFSrc = 1; // BPF_X
399 let BPFClass = 7; // BPF_ALU64
404 let hasSideEffects = 0 in
405 def NOP : NOP_I<"nop">;
407 class RET<string OpcodeStr>
408 : InstBPF<(outs), (ins),
409 !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
412 let Inst{63-60} = op;
416 let op = 9; // BPF_EXIT
417 let BPFClass = 5; // BPF_JMP
420 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
421 isNotDuplicable = 1 in {
422 def RET : RET<"ret">;
425 // ADJCALLSTACKDOWN/UP pseudo insns
426 let Defs = [R11], Uses = [R11] in {
427 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
428 "#ADJCALLSTACKDOWN $amt",
429 [(BPFcallseq_start timm:$amt)]>;
430 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
431 "#ADJCALLSTACKUP $amt1 $amt2",
432 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
435 let usesCustomInserter = 1 in {
436 def Select : Pseudo<(outs GPR:$dst),
437 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
438 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
440 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
443 // load 64-bit global addr into register
444 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
446 // 0xffffFFFF doesn't fit into simm32, optimize common case
447 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
448 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
451 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
452 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
455 def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>;
456 def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
457 def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
460 class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
461 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
462 !strconcat(OpcodeStr, "\t$dst, $addr, $val"),
463 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
469 let Inst{63-61} = mode;
470 let Inst{60-59} = size;
471 let Inst{51-48} = addr{19-16}; // base reg
472 let Inst{55-52} = src;
473 let Inst{47-32} = addr{15-0}; // offset
475 let mode = 6; // BPF_XADD
477 let BPFClass = 3; // BPF_STX
480 let Constraints = "$dst = $val" in {
481 def XADD32 : XADD<0, "xadd32", atomic_load_add_32>;
482 def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
483 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
484 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
487 // bswap16, bswap32, bswap64
488 class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
489 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
490 !strconcat(OpcodeStr, "\t$dst"),
497 let Inst{63-60} = op;
498 let Inst{59} = BPFSrc;
499 let Inst{51-48} = dst;
500 let Inst{31-0} = imm;
502 let op = 0xd; // BPF_END
503 let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
504 let BPFClass = 4; // BPF_ALU
508 let Constraints = "$dst = $src" in {
509 def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
510 def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
511 def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
514 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
515 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
516 class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
517 : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
518 !strconcat(OpcodeStr, "\tr0, $skb.data + $imm"),
519 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
524 let Inst{63-61} = mode;
525 let Inst{60-59} = size;
526 let Inst{31-0} = imm;
528 let mode = 1; // BPF_ABS
530 let BPFClass = 0; // BPF_LD
533 class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
534 : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
535 !strconcat(OpcodeStr, "\tr0, $skb.data + $val"),
536 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
541 let Inst{63-61} = mode;
542 let Inst{60-59} = size;
543 let Inst{55-52} = val;
545 let mode = 2; // BPF_IND
547 let BPFClass = 0; // BPF_LD
551 def LD_ABS_B : LOAD_ABS<2, "ldabs_b", int_bpf_load_byte>;
552 def LD_ABS_H : LOAD_ABS<1, "ldabs_h", int_bpf_load_half>;
553 def LD_ABS_W : LOAD_ABS<0, "ldabs_w", int_bpf_load_word>;
555 def LD_IND_B : LOAD_IND<2, "ldind_b", int_bpf_load_byte>;
556 def LD_IND_H : LOAD_IND<1, "ldind_h", int_bpf_load_half>;
557 def LD_IND_W : LOAD_IND<0, "ldind_w", int_bpf_load_word>;