1 //===-- BPFInstrInfo.td - Target Description for BPF Target ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the BPF instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 include "BPFInstrFormats.td"
16 // Instruction Operands and Patterns
18 // These are target-independent nodes, but have target-specific formats.
19 def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
20 def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
21 def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
22 def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
23 def SDT_BPFSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
26 def SDT_BPFBrCC : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
27 SDTCisVT<3, OtherVT>]>;
28 def SDT_BPFWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
31 def BPFcall : SDNode<"BPFISD::CALL", SDT_BPFCall,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
34 def BPFretflag : SDNode<"BPFISD::RET_FLAG", SDTNone,
35 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
36 def BPFcallseq_start: SDNode<"ISD::CALLSEQ_START", SDT_BPFCallSeqStart,
37 [SDNPHasChain, SDNPOutGlue]>;
38 def BPFcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_BPFCallSeqEnd,
39 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
40 def BPFbrcc : SDNode<"BPFISD::BR_CC", SDT_BPFBrCC,
41 [SDNPHasChain, SDNPOutGlue, SDNPInGlue]>;
43 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
44 def BPFWrapper : SDNode<"BPFISD::Wrapper", SDT_BPFWrapper>;
46 def brtarget : Operand<OtherVT>;
47 def calltarget : Operand<i64>;
49 def u64imm : Operand<i64> {
50 let PrintMethod = "printImm64Operand";
53 def i64immSExt32 : PatLeaf<(imm),
54 [{return isInt<32>(N->getSExtValue()); }]>;
57 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
58 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
61 def MEMri : Operand<i64> {
62 let PrintMethod = "printMemOperand";
63 let EncoderMethod = "getMemoryOpValue";
64 let MIOperandInfo = (ops GPR, i16imm);
67 // Conditional code predicates - used for pattern matching for jump instructions
68 def BPF_CC_EQ : PatLeaf<(imm),
69 [{return (N->getZExtValue() == ISD::SETEQ);}]>;
70 def BPF_CC_NE : PatLeaf<(imm),
71 [{return (N->getZExtValue() == ISD::SETNE);}]>;
72 def BPF_CC_GE : PatLeaf<(imm),
73 [{return (N->getZExtValue() == ISD::SETGE);}]>;
74 def BPF_CC_GT : PatLeaf<(imm),
75 [{return (N->getZExtValue() == ISD::SETGT);}]>;
76 def BPF_CC_GTU : PatLeaf<(imm),
77 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
78 def BPF_CC_GEU : PatLeaf<(imm),
79 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
82 class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
84 !strconcat(OpcodeStr, "\t$dst, $src goto $BrDst"),
85 [(BPFbrcc i64:$dst, i64:$src, Cond, bb:$BrDst)]> {
93 let Inst{59} = BPFSrc;
94 let Inst{55-52} = src;
95 let Inst{51-48} = dst;
96 let Inst{47-32} = BrDst;
100 let BPFClass = 5; // BPF_JMP
103 class JMP_RI<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
105 !strconcat(OpcodeStr, "i\t$dst, $imm goto $BrDst"),
106 [(BPFbrcc i64:$dst, i64immSExt32:$imm, Cond, bb:$BrDst)]> {
113 let Inst{63-60} = op;
114 let Inst{59} = BPFSrc;
115 let Inst{51-48} = dst;
116 let Inst{47-32} = BrDst;
117 let Inst{31-0} = imm;
121 let BPFClass = 5; // BPF_JMP
124 multiclass J<bits<4> Opc, string OpcodeStr, PatLeaf Cond> {
125 def _rr : JMP_RR<Opc, OpcodeStr, Cond>;
126 def _ri : JMP_RI<Opc, OpcodeStr, Cond>;
129 let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
130 // cmp+goto instructions
131 defm JEQ : J<0x1, "jeq", BPF_CC_EQ>;
132 defm JUGT : J<0x2, "jgt", BPF_CC_GTU>;
133 defm JUGE : J<0x3, "jge", BPF_CC_GEU>;
134 defm JNE : J<0x5, "jne", BPF_CC_NE>;
135 defm JSGT : J<0x6, "jsgt", BPF_CC_GT>;
136 defm JSGE : J<0x7, "jsge", BPF_CC_GE>;
140 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
141 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, i64imm:$imm),
142 !strconcat(OpcodeStr, "i\t$dst, $imm"),
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
149 let Inst{63-60} = op;
150 let Inst{59} = BPFSrc;
151 let Inst{51-48} = dst;
152 let Inst{31-0} = imm;
156 let BPFClass = 7; // BPF_ALU64
159 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
160 : InstBPF<(outs GPR:$dst), (ins GPR:$src2, GPR:$src),
161 !strconcat(OpcodeStr, "\t$dst, $src"),
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
168 let Inst{63-60} = op;
169 let Inst{59} = BPFSrc;
170 let Inst{55-52} = src;
171 let Inst{51-48} = dst;
175 let BPFClass = 7; // BPF_ALU64
178 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
183 let Constraints = "$dst = $src2" in {
184 let isAsCheapAsAMove = 1 in {
185 defm ADD : ALU<0x0, "add", add>;
186 defm SUB : ALU<0x1, "sub", sub>;
187 defm OR : ALU<0x4, "or", or>;
188 defm AND : ALU<0x5, "and", and>;
189 defm SLL : ALU<0x6, "sll", shl>;
190 defm SRL : ALU<0x7, "srl", srl>;
191 defm XOR : ALU<0xa, "xor", xor>;
192 defm SRA : ALU<0xc, "sra", sra>;
194 defm MUL : ALU<0x2, "mul", mul>;
195 defm DIV : ALU<0x3, "div", udiv>;
198 class MOV_RR<string OpcodeStr>
199 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
200 !strconcat(OpcodeStr, "\t$dst, $src"),
207 let Inst{63-60} = op;
208 let Inst{59} = BPFSrc;
209 let Inst{55-52} = src;
210 let Inst{51-48} = dst;
212 let op = 0xb; // BPF_MOV
213 let BPFSrc = 1; // BPF_X
214 let BPFClass = 7; // BPF_ALU64
217 class MOV_RI<string OpcodeStr>
218 : InstBPF<(outs GPR:$dst), (ins i64imm:$imm),
219 !strconcat(OpcodeStr, "\t$dst, $imm"),
220 [(set GPR:$dst, (i64 i64immSExt32:$imm))]> {
226 let Inst{63-60} = op;
227 let Inst{59} = BPFSrc;
228 let Inst{51-48} = dst;
229 let Inst{31-0} = imm;
231 let op = 0xb; // BPF_MOV
232 let BPFSrc = 0; // BPF_K
233 let BPFClass = 7; // BPF_ALU64
236 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
237 : InstBPF<(outs GPR:$dst), (ins u64imm:$imm),
238 !strconcat(OpcodeStr, "\t$dst, $imm"),
239 [(set GPR:$dst, (i64 imm:$imm))]> {
246 let Inst{63-61} = mode;
247 let Inst{60-59} = size;
248 let Inst{51-48} = dst;
249 let Inst{55-52} = Pseudo;
251 let Inst{31-0} = imm{31-0};
253 let mode = 0; // BPF_IMM
254 let size = 3; // BPF_DW
255 let BPFClass = 0; // BPF_LD
258 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
259 def LD_imm64 : LD_IMM64<0, "ld_64">;
260 def MOV_rr : MOV_RR<"mov">;
261 def MOV_ri : MOV_RI<"mov">;
265 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
267 [(set i64:$dst, FIri:$addr)]> {
268 // This is a tentative instruction, and will be replaced
269 // with MOV_rr and ADD_ri in PEI phase
274 : InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
275 "ld_pseudo\t$dst, $pseudo, $imm",
276 [(set GPR:$dst, (int_bpf_pseudo imm:$pseudo, imm:$imm))]> {
284 let Inst{63-61} = mode;
285 let Inst{60-59} = size;
286 let Inst{51-48} = dst;
287 let Inst{55-52} = pseudo;
289 let Inst{31-0} = imm{31-0};
291 let mode = 0; // BPF_IMM
292 let size = 3; // BPF_DW
293 let BPFClass = 0; // BPF_LD
296 // STORE instructions
297 class STORE<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
298 : InstBPF<(outs), (ins GPR:$src, MEMri:$addr),
299 !strconcat(OpcodeStr, "\t$addr, $src"), Pattern> {
305 let Inst{63-61} = mode;
306 let Inst{60-59} = size;
307 let Inst{51-48} = addr{19-16}; // base reg
308 let Inst{55-52} = src;
309 let Inst{47-32} = addr{15-0}; // offset
311 let mode = 3; // BPF_MEM
313 let BPFClass = 3; // BPF_STX
316 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
319 def STW : STOREi64<0x0, "stw", truncstorei32>;
320 def STH : STOREi64<0x1, "sth", truncstorei16>;
321 def STB : STOREi64<0x2, "stb", truncstorei8>;
322 def STD : STOREi64<0x3, "std", store>;
325 class LOAD<bits<2> SizeOp, string OpcodeStr, list<dag> Pattern>
326 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
327 !strconcat(OpcodeStr, "\t$dst, $addr"), Pattern> {
333 let Inst{63-61} = mode;
334 let Inst{60-59} = size;
335 let Inst{51-48} = dst;
336 let Inst{55-52} = addr{19-16};
337 let Inst{47-32} = addr{15-0};
339 let mode = 3; // BPF_MEM
341 let BPFClass = 1; // BPF_LDX
344 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
345 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
347 def LDW : LOADi64<0x0, "ldw", zextloadi32>;
348 def LDH : LOADi64<0x1, "ldh", zextloadi16>;
349 def LDB : LOADi64<0x2, "ldb", zextloadi8>;
350 def LDD : LOADi64<0x3, "ldd", load>;
352 class BRANCH<bits<4> Opc, string OpcodeStr, list<dag> Pattern>
353 : InstBPF<(outs), (ins brtarget:$BrDst),
354 !strconcat(OpcodeStr, "\t$BrDst"), Pattern> {
359 let Inst{63-60} = op;
360 let Inst{59} = BPFSrc;
361 let Inst{47-32} = BrDst;
365 let BPFClass = 5; // BPF_JMP
368 class CALL<string OpcodeStr>
369 : InstBPF<(outs), (ins calltarget:$BrDst),
370 !strconcat(OpcodeStr, "\t$BrDst"), []> {
375 let Inst{63-60} = op;
376 let Inst{59} = BPFSrc;
377 let Inst{31-0} = BrDst;
379 let op = 8; // BPF_CALL
381 let BPFClass = 5; // BPF_JMP
385 let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
386 def JMP : BRANCH<0x0, "jmp", [(br bb:$BrDst)]>;
390 let isCall=1, hasDelaySlot=0, Uses = [R11],
391 // Potentially clobbered registers
392 Defs = [R0, R1, R2, R3, R4, R5] in {
393 def JAL : CALL<"call">;
396 class NOP_I<string OpcodeStr>
397 : InstBPF<(outs), (ins i32imm:$imm),
398 !strconcat(OpcodeStr, "\t$imm"), []> {
405 let Inst{63-60} = op;
406 let Inst{59} = BPFSrc;
407 let Inst{55-52} = src;
408 let Inst{51-48} = dst;
410 let op = 0xb; // BPF_MOV
411 let BPFSrc = 1; // BPF_X
412 let BPFClass = 7; // BPF_ALU64
417 let hasSideEffects = 0 in
418 def NOP : NOP_I<"nop">;
420 class RET<string OpcodeStr>
421 : InstBPF<(outs), (ins),
422 !strconcat(OpcodeStr, ""), [(BPFretflag)]> {
425 let Inst{63-60} = op;
429 let op = 9; // BPF_EXIT
430 let BPFClass = 5; // BPF_JMP
433 let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
434 isNotDuplicable = 1 in {
435 def RET : RET<"ret">;
438 // ADJCALLSTACKDOWN/UP pseudo insns
439 let Defs = [R11], Uses = [R11] in {
440 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
441 "#ADJCALLSTACKDOWN $amt",
442 [(BPFcallseq_start timm:$amt)]>;
443 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
444 "#ADJCALLSTACKUP $amt1 $amt2",
445 [(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
448 let usesCustomInserter = 1 in {
449 def Select : Pseudo<(outs GPR:$dst),
450 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR:$src, GPR:$src2),
451 "# Select PSEUDO $dst = $lhs $imm $rhs ? $src : $src2",
453 (BPFselectcc i64:$lhs, i64:$rhs, (i64 imm:$imm), i64:$src, i64:$src2))]>;
456 // load 64-bit global addr into register
457 def : Pat<(BPFWrapper tglobaladdr:$in), (LD_imm64 tglobaladdr:$in)>;
459 // 0xffffFFFF doesn't fit into simm32, optimize common case
460 def : Pat<(i64 (and (i64 GPR:$src), 0xffffFFFF)),
461 (SRL_ri (SLL_ri (i64 GPR:$src), 32), 32)>;
464 def : Pat<(BPFcall tglobaladdr:$dst), (JAL tglobaladdr:$dst)>;
465 def : Pat<(BPFcall imm:$dst), (JAL imm:$dst)>;
468 def : Pat<(extloadi8 ADDRri:$src), (i64 (LDB ADDRri:$src))>;
469 def : Pat<(extloadi16 ADDRri:$src), (i64 (LDH ADDRri:$src))>;
470 def : Pat<(extloadi32 ADDRri:$src), (i64 (LDW ADDRri:$src))>;
473 class XADD<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
474 : InstBPF<(outs GPR:$dst), (ins MEMri:$addr, GPR:$val),
475 !strconcat(OpcodeStr, "\t$dst, $addr, $val"),
476 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
482 let Inst{63-61} = mode;
483 let Inst{60-59} = size;
484 let Inst{51-48} = addr{19-16}; // base reg
485 let Inst{55-52} = src;
486 let Inst{47-32} = addr{15-0}; // offset
488 let mode = 6; // BPF_XADD
490 let BPFClass = 3; // BPF_STX
493 let Constraints = "$dst = $val" in {
494 def XADD32 : XADD<0, "xadd32", atomic_load_add_32>;
495 def XADD64 : XADD<3, "xadd64", atomic_load_add_64>;
496 // undefined def XADD16 : XADD<1, "xadd16", atomic_load_add_16>;
497 // undefined def XADD8 : XADD<2, "xadd8", atomic_load_add_8>;
500 // bswap16, bswap32, bswap64
501 class BSWAP<bits<32> SizeOp, string OpcodeStr, list<dag> Pattern>
502 : InstBPF<(outs GPR:$dst), (ins GPR:$src),
503 !strconcat(OpcodeStr, "\t$dst"),
510 let Inst{63-60} = op;
511 let Inst{59} = BPFSrc;
512 let Inst{51-48} = dst;
513 let Inst{31-0} = imm;
515 let op = 0xd; // BPF_END
516 let BPFSrc = 1; // BPF_TO_BE (TODO: use BPF_TO_LE for big-endian target)
517 let BPFClass = 4; // BPF_ALU
521 let Constraints = "$dst = $src" in {
522 def BSWAP16 : BSWAP<16, "bswap16", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 48)))]>;
523 def BSWAP32 : BSWAP<32, "bswap32", [(set GPR:$dst, (srl (bswap GPR:$src), (i64 32)))]>;
524 def BSWAP64 : BSWAP<64, "bswap64", [(set GPR:$dst, (bswap GPR:$src))]>;
527 let Defs = [R0, R1, R2, R3, R4, R5], Uses = [R6], hasSideEffects = 1,
528 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
529 class LOAD_ABS<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
530 : InstBPF<(outs), (ins GPR:$skb, i64imm:$imm),
531 !strconcat(OpcodeStr, "\tr0, $skb.data + $imm"),
532 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
537 let Inst{63-61} = mode;
538 let Inst{60-59} = size;
539 let Inst{31-0} = imm;
541 let mode = 1; // BPF_ABS
543 let BPFClass = 0; // BPF_LD
546 class LOAD_IND<bits<2> SizeOp, string OpcodeStr, Intrinsic OpNode>
547 : InstBPF<(outs), (ins GPR:$skb, GPR:$val),
548 !strconcat(OpcodeStr, "\tr0, $skb.data + $val"),
549 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
554 let Inst{63-61} = mode;
555 let Inst{60-59} = size;
556 let Inst{55-52} = val;
558 let mode = 2; // BPF_IND
560 let BPFClass = 0; // BPF_LD
564 def LD_ABS_B : LOAD_ABS<2, "ldabs_b", int_bpf_load_byte>;
565 def LD_ABS_H : LOAD_ABS<1, "ldabs_h", int_bpf_load_half>;
566 def LD_ABS_W : LOAD_ABS<0, "ldabs_w", int_bpf_load_word>;
568 def LD_IND_B : LOAD_IND<2, "ldind_b", int_bpf_load_byte>;
569 def LD_IND_H : LOAD_IND<1, "ldind_h", int_bpf_load_half>;
570 def LD_IND_W : LOAD_IND<0, "ldind_w", int_bpf_load_word>;