1 //===- BlackfinISelDAGToDAG.cpp - A dag to dag inst selector for Blackfin -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the Blackfin target.
12 //===----------------------------------------------------------------------===//
15 #include "BlackfinTargetMachine.h"
16 #include "BlackfinRegisterInfo.h"
17 #include "llvm/Intrinsics.h"
18 #include "llvm/CodeGen/SelectionDAGISel.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Instruction Selector Implementation
29 //===----------------------------------------------------------------------===//
31 //===----------------------------------------------------------------------===//
32 /// BlackfinDAGToDAGISel - Blackfin specific code to select blackfin machine
33 /// instructions for SelectionDAG operations.
35 class BlackfinDAGToDAGISel : public SelectionDAGISel {
36 /// Subtarget - Keep a pointer to the Blackfin Subtarget around so that we
37 /// can make the right decision when generating code for different targets.
38 //const BlackfinSubtarget &Subtarget;
40 BlackfinDAGToDAGISel(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel)
41 : SelectionDAGISel(TM, OptLevel) {}
43 virtual void PostprocessISelDAG();
45 virtual const char *getPassName() const {
46 return "Blackfin DAG->DAG Pattern Instruction Selection";
49 // Include the pieces autogenerated from the target description.
50 #include "BlackfinGenDAGISel.inc"
53 SDNode *Select(SDNode *N);
54 bool SelectADDRspii(SDNode *Op, SDValue Addr,
55 SDValue &Base, SDValue &Offset);
57 // Walk the DAG after instruction selection, fixing register class issues.
58 void FixRegisterClasses(SelectionDAG &DAG);
60 const BlackfinInstrInfo &getInstrInfo() {
61 return *static_cast<const BlackfinTargetMachine&>(TM).getInstrInfo();
63 const BlackfinRegisterInfo *getRegisterInfo() {
64 return static_cast<const BlackfinTargetMachine&>(TM).getRegisterInfo();
67 } // end anonymous namespace
69 FunctionPass *llvm::createBlackfinISelDag(BlackfinTargetMachine &TM,
70 CodeGenOpt::Level OptLevel) {
71 return new BlackfinDAGToDAGISel(TM, OptLevel);
74 void BlackfinDAGToDAGISel::PostprocessISelDAG() {
75 FixRegisterClasses(*CurDAG);
78 SDNode *BlackfinDAGToDAGISel::Select(SDNode *N) {
79 if (N->isMachineOpcode())
80 return NULL; // Already selected.
82 switch (N->getOpcode()) {
84 case ISD::FrameIndex: {
85 // Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
87 int FI = cast<FrameIndexSDNode>(N)->getIndex();
88 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
89 return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
90 CurDAG->getTargetConstant(0, MVT::i32));
97 bool BlackfinDAGToDAGISel::SelectADDRspii(SDNode *Op,
101 FrameIndexSDNode *FIN = 0;
102 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
103 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
104 Offset = CurDAG->getTargetConstant(0, MVT::i32);
107 if (Addr.getOpcode() == ISD::ADD) {
108 ConstantSDNode *CN = 0;
109 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) &&
110 (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
111 (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
112 // Constant positive word offset from frame index
113 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
114 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
121 static inline bool isCC(const TargetRegisterClass *RC) {
122 return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC);
125 static inline bool isDCC(const TargetRegisterClass *RC) {
126 return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC);
129 static void UpdateNodeOperand(SelectionDAG &DAG,
133 SmallVector<SDValue, 8> ops(N->op_begin(), N->op_end());
135 SDNode *New = DAG.UpdateNodeOperands(N, ops.data(), ops.size());
136 DAG.ReplaceAllUsesWith(N, New);
139 // After instruction selection, insert COPY_TO_REGCLASS nodes to help in
140 // choosing the proper register classes.
141 void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) {
142 const BlackfinInstrInfo &TII = getInstrInfo();
143 const BlackfinRegisterInfo *TRI = getRegisterInfo();
144 DAG.AssignTopologicalOrder();
145 HandleSDNode Dummy(DAG.getRoot());
147 for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin();
148 NI != DAG.allnodes_end(); ++NI) {
149 if (NI->use_empty() || !NI->isMachineOpcode())
151 const TargetInstrDesc &DefTID = TII.get(NI->getMachineOpcode());
152 for (SDNode::use_iterator UI = NI->use_begin(); !UI.atEnd(); ++UI) {
153 if (!UI->isMachineOpcode())
156 if (UI.getUse().getResNo() >= DefTID.getNumDefs())
158 const TargetRegisterClass *DefRC =
159 DefTID.OpInfo[UI.getUse().getResNo()].getRegClass(TRI);
161 const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode());
162 if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands())
164 const TargetRegisterClass *UseRC =
165 UseTID.OpInfo[UseTID.getNumDefs()+UI.getOperandNo()].getRegClass(TRI);
166 if (!DefRC || !UseRC)
168 // We cannot copy CC <-> !(CC/D)
169 if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
171 DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
175 DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
176 UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
180 DAG.setRoot(Dummy.getValue());