1 //===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Blackfin uses to lower LLVM code
11 // into a selection DAG.
13 //===----------------------------------------------------------------------===//
15 #include "BlackfinISelLowering.h"
16 #include "BlackfinTargetMachine.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
31 //===----------------------------------------------------------------------===//
32 // Calling Convention Implementation
33 //===----------------------------------------------------------------------===//
35 #include "BlackfinGenCallingConv.inc"
37 //===----------------------------------------------------------------------===//
38 // TargetLowering Implementation
39 //===----------------------------------------------------------------------===//
41 BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
42 : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
43 setShiftAmountType(MVT::i16);
44 setBooleanContents(ZeroOrOneBooleanContent);
45 setStackPointerRegisterToSaveRestore(BF::SP);
46 setIntDivIsCheap(false);
48 // Set up the legal register classes.
49 addRegisterClass(MVT::i32, BF::DRegisterClass);
50 addRegisterClass(MVT::i16, BF::D16RegisterClass);
52 computeRegisterProperties();
54 // Blackfin doesn't have i1 loads or stores
55 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
56 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
59 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
60 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
62 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
63 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
64 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
66 // i16 registers don't do much
67 setOperationAction(ISD::AND, MVT::i16, Promote);
68 setOperationAction(ISD::OR, MVT::i16, Promote);
69 setOperationAction(ISD::XOR, MVT::i16, Promote);
70 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
71 // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
73 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
74 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
75 setOperationAction(ISD::SETCC, MVT::i16, Promote);
77 // Blackfin has no division
78 setOperationAction(ISD::SDIV, MVT::i16, Expand);
79 setOperationAction(ISD::SDIV, MVT::i32, Expand);
80 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
81 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
82 setOperationAction(ISD::SREM, MVT::i16, Expand);
83 setOperationAction(ISD::SREM, MVT::i32, Expand);
84 setOperationAction(ISD::UDIV, MVT::i16, Expand);
85 setOperationAction(ISD::UDIV, MVT::i32, Expand);
86 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
87 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i16, Expand);
89 setOperationAction(ISD::UREM, MVT::i32, Expand);
91 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
92 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
93 setOperationAction(ISD::MULHU, MVT::i32, Expand);
94 setOperationAction(ISD::MULHS, MVT::i32, Expand);
96 // No carry-in operations.
97 setOperationAction(ISD::ADDE, MVT::i32, Custom);
98 setOperationAction(ISD::SUBE, MVT::i32, Custom);
100 // Blackfin has no intrinsics for these particular operations.
101 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
102 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
104 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
105 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
106 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
110 // i32 has native CTPOP, but not CTLZ/CTTZ
111 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
112 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
114 // READCYCLECOUNTER needs special type legalization.
115 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
117 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
119 // Use the default implementation.
120 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
121 setOperationAction(ISD::VAEND, MVT::Other, Expand);
122 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
123 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
126 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
129 case BFISD::CALL: return "BFISD::CALL";
130 case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
131 case BFISD::Wrapper: return "BFISD::Wrapper";
135 MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
136 // SETCC always sets the CC register. Technically that is an i1 register, but
137 // that type is not legal, so we treat it as an i32 register.
141 SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
142 SelectionDAG &DAG) const {
143 DebugLoc DL = Op.getDebugLoc();
144 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
146 Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
147 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
150 SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
151 SelectionDAG &DAG) const {
152 DebugLoc DL = Op.getDebugLoc();
153 int JTI = cast<JumpTableSDNode>(Op)->getIndex();
155 Op = DAG.getTargetJumpTable(JTI, MVT::i32);
156 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
160 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
161 CallingConv::ID CallConv, bool isVarArg,
162 const SmallVectorImpl<ISD::InputArg>
164 DebugLoc dl, SelectionDAG &DAG,
165 SmallVectorImpl<SDValue> &InVals)
168 MachineFunction &MF = DAG.getMachineFunction();
169 MachineFrameInfo *MFI = MF.getFrameInfo();
171 SmallVector<CCValAssign, 16> ArgLocs;
172 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
173 ArgLocs, *DAG.getContext());
174 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
175 CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
177 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
178 CCValAssign &VA = ArgLocs[i];
181 EVT RegVT = VA.getLocVT();
182 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
183 BF::PRegisterClass : BF::DRegisterClass;
184 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
185 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
187 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
188 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
189 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
191 // If this is an 8 or 16-bit value, it is really passed promoted to 32
192 // bits. Insert an assert[sz]ext to capture this, then truncate to the
194 if (VA.getLocInfo() == CCValAssign::SExt)
195 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
196 DAG.getValueType(VA.getValVT()));
197 else if (VA.getLocInfo() == CCValAssign::ZExt)
198 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
199 DAG.getValueType(VA.getValVT()));
201 if (VA.getLocInfo() != CCValAssign::Full)
202 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
204 InVals.push_back(ArgValue);
206 assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
207 unsigned ObjSize = VA.getLocVT().getStoreSize();
208 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
209 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
210 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
211 MachinePointerInfo(),
220 BlackfinTargetLowering::LowerReturn(SDValue Chain,
221 CallingConv::ID CallConv, bool isVarArg,
222 const SmallVectorImpl<ISD::OutputArg> &Outs,
223 const SmallVectorImpl<SDValue> &OutVals,
224 DebugLoc dl, SelectionDAG &DAG) const {
226 // CCValAssign - represent the assignment of the return value to locations.
227 SmallVector<CCValAssign, 16> RVLocs;
229 // CCState - Info about the registers and stack slot.
230 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
231 RVLocs, *DAG.getContext());
233 // Analize return values.
234 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
236 // If this is the first return lowered for this function, add the regs to the
237 // liveout set for the function.
238 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
239 for (unsigned i = 0; i != RVLocs.size(); ++i)
240 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
245 // Copy the result values into the output registers.
246 for (unsigned i = 0; i != RVLocs.size(); ++i) {
247 CCValAssign &VA = RVLocs[i];
248 assert(VA.isRegLoc() && "Can only return in registers!");
249 SDValue Opi = OutVals[i];
251 // Expand to i32 if necessary
252 switch (VA.getLocInfo()) {
253 default: llvm_unreachable("Unknown loc info!");
254 case CCValAssign::Full: break;
255 case CCValAssign::SExt:
256 Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
258 case CCValAssign::ZExt:
259 Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
261 case CCValAssign::AExt:
262 Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
265 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
266 // Guarantee that all emitted copies are stuck together with flags.
267 Flag = Chain.getValue(1);
270 if (Flag.getNode()) {
271 return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
273 return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
278 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
279 CallingConv::ID CallConv, bool isVarArg,
281 const SmallVectorImpl<ISD::OutputArg> &Outs,
282 const SmallVectorImpl<SDValue> &OutVals,
283 const SmallVectorImpl<ISD::InputArg> &Ins,
284 DebugLoc dl, SelectionDAG &DAG,
285 SmallVectorImpl<SDValue> &InVals) const {
286 // Blackfin target does not yet support tail call optimization.
289 // Analyze operands of the call, assigning locations to each operand.
290 SmallVector<CCValAssign, 16> ArgLocs;
291 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
293 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
294 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
296 // Get the size of the outgoing arguments stack space requirement.
297 unsigned ArgsSize = CCInfo.getNextStackOffset();
299 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
300 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
301 SmallVector<SDValue, 8> MemOpChains;
303 // Walk the register/memloc assignments, inserting copies/loads.
304 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
305 CCValAssign &VA = ArgLocs[i];
306 SDValue Arg = OutVals[i];
308 // Promote the value if needed.
309 switch (VA.getLocInfo()) {
310 default: llvm_unreachable("Unknown loc info!");
311 case CCValAssign::Full: break;
312 case CCValAssign::SExt:
313 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
315 case CCValAssign::ZExt:
316 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
318 case CCValAssign::AExt:
319 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
323 // Arguments that can be passed on register must be kept at
326 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
328 assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
329 int Offset = VA.getLocMemOffset();
330 assert(Offset%4 == 0 && "Unaligned LocMemOffset");
331 assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
332 SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
333 SDValue OffsetN = DAG.getIntPtrConstant(Offset);
334 OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
335 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
336 PseudoSourceValue::getStack(),
337 Offset, false, false, 0));
341 // Transform all store nodes into one single node because
342 // all store nodes are independent of each other.
343 if (!MemOpChains.empty())
344 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
345 &MemOpChains[0], MemOpChains.size());
347 // Build a sequence of copy-to-reg nodes chained together with token
348 // chain and flag operands which copy the outgoing args into registers.
349 // The InFlag in necessary since all emited instructions must be
352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
353 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
354 RegsToPass[i].second, InFlag);
355 InFlag = Chain.getValue(1);
358 // If the callee is a GlobalAddress node (quite common, every direct call is)
359 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
360 // Likewise ExternalSymbol -> TargetExternalSymbol.
361 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
362 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
363 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
364 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
366 std::vector<EVT> NodeTys;
367 NodeTys.push_back(MVT::Other); // Returns a chain
368 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
369 SDValue Ops[] = { Chain, Callee, InFlag };
370 Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
371 InFlag.getNode() ? 3 : 2);
372 InFlag = Chain.getValue(1);
374 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
375 DAG.getIntPtrConstant(0, true), InFlag);
376 InFlag = Chain.getValue(1);
378 // Assign locations to each value returned by this call.
379 SmallVector<CCValAssign, 16> RVLocs;
380 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
383 RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
385 // Copy all of the result registers out of their specified physreg.
386 for (unsigned i = 0; i != RVLocs.size(); ++i) {
387 CCValAssign &RV = RVLocs[i];
388 unsigned Reg = RV.getLocReg();
390 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
391 RVLocs[i].getLocVT(), InFlag);
392 SDValue Val = Chain.getValue(0);
393 InFlag = Chain.getValue(2);
394 Chain = Chain.getValue(1);
396 // Callee is responsible for extending any i16 return values.
397 switch (RV.getLocInfo()) {
398 case CCValAssign::SExt:
399 Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
400 DAG.getValueType(RV.getValVT()));
402 case CCValAssign::ZExt:
403 Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
404 DAG.getValueType(RV.getValVT()));
410 // Truncate to valtype
411 if (RV.getLocInfo() != CCValAssign::Full)
412 Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
413 InVals.push_back(Val);
419 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
420 // add-with-carry instructions.
421 SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
422 // Operands: lhs, rhs, carry-in (AC0 flag)
423 // Results: sum, carry-out (AC0 flag)
424 DebugLoc dl = Op.getDebugLoc();
426 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
428 // zext incoming carry flag in AC0 to 32 bits
429 SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
430 /* flag= */ Op.getOperand(2));
431 CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
432 SDValue(CarryIn, 0));
434 // Add operands, produce sum and carry flag
435 SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
436 Op.getOperand(0), Op.getOperand(1));
438 // Store intermediate carry from Sum
439 SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
440 /* flag= */ SDValue(Sum, 1));
442 // Add incoming carry, again producing an output flag
443 Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag,
444 SDValue(Sum, 0), SDValue(CarryIn, 0));
446 // Update AC0 with the intermediate carry, producing a flag.
447 SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Flag,
450 // Compose (i32, flag) pair
451 SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
452 return DAG.getMergeValues(ops, 2, dl);
455 SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
456 SelectionDAG &DAG) const {
457 switch (Op.getOpcode()) {
459 Op.getNode()->dump();
460 llvm_unreachable("Should not custom lower this!");
461 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
462 case ISD::GlobalTLSAddress:
463 llvm_unreachable("TLS not implemented for Blackfin.");
464 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
465 // Frame & Return address. Currently unimplemented
466 case ISD::FRAMEADDR: return SDValue();
467 case ISD::RETURNADDR: return SDValue();
469 case ISD::SUBE: return LowerADDE(Op, DAG);
474 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
475 SmallVectorImpl<SDValue> &Results,
476 SelectionDAG &DAG) const {
477 DebugLoc dl = N->getDebugLoc();
478 switch (N->getOpcode()) {
480 llvm_unreachable("Do not know how to custom type legalize this operation!");
482 case ISD::READCYCLECOUNTER: {
483 // The low part of the cycle counter is in CYCLES, the high part in
484 // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
486 SDValue TheChain = N->getOperand(0);
487 SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
488 SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
489 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
490 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
491 // Outgoing chain. If we were to use the chain from lo instead, it would be
492 // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
493 // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
494 // read beyond the next CYCLES read, leading to invalid results.
495 Results.push_back(hi.getValue(1));
501 /// getFunctionAlignment - Return the Log2 alignment of this function.
502 unsigned BlackfinTargetLowering::getFunctionAlignment(const Function *F) const {
506 //===----------------------------------------------------------------------===//
507 // Blackfin Inline Assembly Support
508 //===----------------------------------------------------------------------===//
510 /// getConstraintType - Given a constraint letter, return the type of
511 /// constraint it is for this target.
512 BlackfinTargetLowering::ConstraintType
513 BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
514 if (Constraint.size() != 1)
515 return TargetLowering::getConstraintType(Constraint);
517 switch (Constraint[0]) {
518 // Standard constraints
520 return C_RegisterClass;
522 // Blackfin-specific constraints
539 return C_RegisterClass;
548 // Not implemented: q0-q7, qA. Use {R2} etc instead
550 return TargetLowering::getConstraintType(Constraint);
553 /// getRegForInlineAsmConstraint - Return register no and class for a C_Register
555 std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
556 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
557 typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
560 if (Constraint.size() != 1)
561 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
563 switch (Constraint[0]) {
564 // Standard constraints
566 return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
568 // Blackfin-specific constraints
569 case 'a': return Pair(0U, PRegisterClass);
570 case 'd': return Pair(0U, DRegisterClass);
571 case 'e': return Pair(0U, AccuRegisterClass);
572 case 'A': return Pair(A0, AccuRegisterClass);
573 case 'B': return Pair(A1, AccuRegisterClass);
574 case 'b': return Pair(0U, IRegisterClass);
575 case 'v': return Pair(0U, BRegisterClass);
576 case 'f': return Pair(0U, MRegisterClass);
577 case 'C': return Pair(CC, JustCCRegisterClass);
578 case 'x': return Pair(0U, GRRegisterClass);
579 case 'w': return Pair(0U, ALLRegisterClass);
580 case 'Z': return Pair(P3, PRegisterClass);
581 case 'Y': return Pair(P1, PRegisterClass);
584 // Not implemented: q0-q7, qA. Use {R2} etc instead.
585 // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
586 // getRegClassForInlineAsmConstraint()
588 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
591 std::vector<unsigned> BlackfinTargetLowering::
592 getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
595 if (Constraint.size() != 1)
596 return std::vector<unsigned>();
598 switch (Constraint[0]) {
599 case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
600 case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
601 case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
602 case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
605 case 't': return make_vector<unsigned>(LT0, LT1, 0);
606 case 'u': return make_vector<unsigned>(LB0, LB1, 0);
607 case 'k': return make_vector<unsigned>(LC0, LC1, 0);
608 case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
609 ASTAT, SEQSTAT, USP, 0);
612 return std::vector<unsigned>();
615 bool BlackfinTargetLowering::
616 isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
617 // The Blackfin target isn't yet aware of offsets.