1 //===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Blackfin uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef BLACKFIN_ISELLOWERING_H
16 #define BLACKFIN_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
26 CALL, // A call instruction.
27 RET_FLAG, // Return with a flag operand.
28 Wrapper // Address wrapper
32 class BlackfinTargetLowering : public TargetLowering {
34 BlackfinTargetLowering(TargetMachine &TM);
35 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
36 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
37 virtual void ReplaceNodeResults(SDNode *N,
38 SmallVectorImpl<SDValue> &Results,
39 SelectionDAG &DAG) const;
41 ConstraintType getConstraintType(const std::string &Constraint) const;
42 std::pair<unsigned, const TargetRegisterClass*>
43 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
45 getRegClassForInlineAsmConstraint(const std::string &Constraint,
47 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
48 const char *getTargetNodeName(unsigned Opcode) const;
49 unsigned getFunctionAlignment(const Function *F) const;
52 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
57 LowerFormalArguments(SDValue Chain,
58 CallingConv::ID CallConv, bool isVarArg,
59 const SmallVectorImpl<ISD::InputArg> &Ins,
60 DebugLoc dl, SelectionDAG &DAG,
61 SmallVectorImpl<SDValue> &InVals) const;
63 LowerCall(SDValue Chain, SDValue Callee,
64 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
65 const SmallVectorImpl<ISD::OutputArg> &Outs,
66 const SmallVectorImpl<ISD::InputArg> &Ins,
67 DebugLoc dl, SelectionDAG &DAG,
68 SmallVectorImpl<SDValue> &InVals) const;
71 LowerReturn(SDValue Chain,
72 CallingConv::ID CallConv, bool isVarArg,
73 const SmallVectorImpl<ISD::OutputArg> &Outs,
74 DebugLoc dl, SelectionDAG &DAG) const;
76 } // end namespace llvm
78 #endif // BLACKFIN_ISELLOWERING_H