1 //===- BlackfinInstrInfo.h - Blackfin Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef BLACKFININSTRUCTIONINFO_H
15 #define BLACKFININSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "BlackfinRegisterInfo.h"
20 #define GET_INSTRINFO_HEADER
21 #include "BlackfinGenInstrInfo.inc"
25 class BlackfinInstrInfo : public BlackfinGenInstrInfo {
26 const BlackfinRegisterInfo RI;
27 const BlackfinSubtarget& Subtarget;
29 explicit BlackfinInstrInfo(BlackfinSubtarget &ST);
31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32 /// such, whenever a client has an instance of instruction info, it should
33 /// always be able to get register info as well (through this method).
34 virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
36 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
37 int &FrameIndex) const;
39 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
43 InsertBranch(MachineBasicBlock &MBB,
44 MachineBasicBlock *TBB,
45 MachineBasicBlock *FBB,
46 const SmallVectorImpl<MachineOperand> &Cond,
49 virtual void copyPhysReg(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI, DebugLoc DL,
51 unsigned DestReg, unsigned SrcReg,
54 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MBBI,
56 unsigned SrcReg, bool isKill,
58 const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI) const;
61 virtual void storeRegToAddr(MachineFunction &MF,
62 unsigned SrcReg, bool isKill,
63 SmallVectorImpl<MachineOperand> &Addr,
64 const TargetRegisterClass *RC,
65 SmallVectorImpl<MachineInstr*> &NewMIs) const;
67 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator MBBI,
69 unsigned DestReg, int FrameIndex,
70 const TargetRegisterClass *RC,
71 const TargetRegisterInfo *TRI) const;
73 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
74 SmallVectorImpl<MachineOperand> &Addr,
75 const TargetRegisterClass *RC,
76 SmallVectorImpl<MachineInstr*> &NewMIs) const;
79 } // end namespace llvm