1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "BlackfinRegisterInfo.h"
17 #include "BlackfinSubtarget.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineLocation.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Type.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
35 const TargetInstrInfo &tii)
36 : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
43 static const unsigned CalleeSavedRegs[] = {
48 return CalleeSavedRegs;
51 const TargetRegisterClass* const *BlackfinRegisterInfo::
52 getCalleeSavedRegClasses(const MachineFunction *MF) const {
54 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
56 &DRegClass, &DRegClass, &DRegClass, &DRegClass,
57 &PRegClass, &PRegClass, &PRegClass,
59 return CalleeSavedRegClasses;
63 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
65 BitVector Reserved(getNumRegs());
77 Reserved.set(CYCLES).set(CYCLES2);
89 const TargetRegisterClass*
90 BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
91 assert(isPhysicalRegister(reg) && "reg must be a physical register");
93 // Pick the smallest register class of the right type that contains
95 const TargetRegisterClass* BestRC = 0;
96 for (regclass_iterator I = regclass_begin(), E = regclass_end();
98 const TargetRegisterClass* RC = *I;
99 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
100 (!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
104 assert(BestRC && "Couldn't find the register class");
108 // hasFP - Return true if the specified function should have a dedicated frame
109 // pointer register. This is true if the function has variable sized allocas or
110 // if frame pointer elimination is disabled.
111 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
112 const MachineFrameInfo *MFI = MF.getFrameInfo();
113 return DisableFramePointerElim(MF) ||
114 MFI->adjustsStack() || MFI->hasVarSizedObjects();
117 bool BlackfinRegisterInfo::
118 requiresRegisterScavenging(const MachineFunction &MF) const {
122 // Emit instructions to add delta to D/P register. ScratchReg must be of the
123 // same class as Reg (P).
124 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I,
132 if (isInt<7>(delta)) {
133 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
134 .addReg(Reg) // No kill on two-addr operand
139 // We must load delta into ScratchReg and add that.
140 loadConstant(MBB, I, DL, ScratchReg, delta);
141 if (BF::PRegClass.contains(Reg)) {
142 assert(BF::PRegClass.contains(ScratchReg) &&
143 "ScratchReg must be a P register");
144 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
145 .addReg(Reg, RegState::Kill)
146 .addReg(ScratchReg, RegState::Kill);
148 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
149 assert(BF::DRegClass.contains(ScratchReg) &&
150 "ScratchReg must be a D register");
151 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
152 .addReg(Reg, RegState::Kill)
153 .addReg(ScratchReg, RegState::Kill);
157 // Emit instructions to load a constant into D/P register
158 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator I,
163 if (isInt<7>(value)) {
164 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
168 if (isUInt<16>(value)) {
169 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
173 if (isInt<16>(value)) {
174 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
178 // We must split into halves
180 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_hi16))
181 .addImm((value >> 16) & 0xffff)
182 .addReg(Reg, RegState::ImplicitDefine);
184 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_lo16))
185 .addImm(value & 0xffff)
186 .addReg(Reg, RegState::ImplicitKill)
187 .addReg(Reg, RegState::ImplicitDefine);
190 void BlackfinRegisterInfo::
191 eliminateCallFramePseudoInstr(MachineFunction &MF,
192 MachineBasicBlock &MBB,
193 MachineBasicBlock::iterator I) const {
194 if (!hasReservedCallFrame(MF)) {
195 int64_t Amount = I->getOperand(0).getImm();
197 assert(Amount%4 == 0 && "Unaligned call frame size");
198 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
199 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
201 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
202 "Unknown call frame pseudo instruction");
203 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
210 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
211 /// register first and then a spilled callee-saved register if that fails.
212 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
214 const TargetRegisterClass *RC,
216 assert(RS && "Register scavenging must be on");
217 unsigned Reg = RS->FindUnusedReg(RC);
219 Reg = RS->scavengeRegister(RC, II, SPAdj);
224 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
225 int SPAdj, FrameIndexValue *Value,
226 RegScavenger *RS) const {
227 MachineInstr &MI = *II;
228 MachineBasicBlock &MBB = *MI.getParent();
229 MachineFunction &MF = *MBB.getParent();
230 DebugLoc DL = MI.getDebugLoc();
233 for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
234 assert(FIPos < MI.getNumOperands() &&
235 "Instr doesn't have FrameIndex operand!");
237 int FrameIndex = MI.getOperand(FIPos).getIndex();
238 assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
239 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
240 + MI.getOperand(FIPos+1).getImm();
241 unsigned BaseReg = BF::FP;
243 assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
246 Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
249 bool isStore = false;
251 switch (MI.getOpcode()) {
255 assert(Offset%4 == 0 && "Unaligned i32 stack access");
256 assert(FIPos==1 && "Bad frame index operand");
257 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
258 MI.getOperand(FIPos+1).setImm(Offset);
259 if (isUInt<6>(Offset)) {
260 MI.setDesc(TII.get(isStore
261 ? BF::STORE32p_uimm6m4
262 : BF::LOAD32p_uimm6m4));
265 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
266 MI.setDesc(TII.get(isStore
267 ? BF::STORE32fp_nimm7m4
268 : BF::LOAD32fp_nimm7m4));
269 MI.getOperand(FIPos+1).setImm(-Offset);
272 if (isInt<18>(Offset)) {
273 MI.setDesc(TII.get(isStore
274 ? BF::STORE32p_imm18m4
275 : BF::LOAD32p_imm18m4));
278 // Use RegScavenger to calculate proper offset...
280 llvm_unreachable("Stack frame offset too big");
284 assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
285 unsigned DestReg = MI.getOperand(0).getReg();
286 // We need to produce a stack offset in a P register. We emit:
289 assert(FIPos==1 && "Bad frame index operand");
290 loadConstant(MBB, II, DL, DestReg, Offset);
291 MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
292 MI.getOperand(2).ChangeToRegister(BaseReg, false);
298 assert(Offset%2 == 0 && "Unaligned i16 stack access");
299 assert(FIPos==1 && "Bad frame index operand");
300 // We need a P register to use as an address
301 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
302 assert(ScratchReg && "Could not scavenge register");
303 loadConstant(MBB, II, DL, ScratchReg, Offset);
304 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
305 .addReg(ScratchReg, RegState::Kill)
307 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
308 MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
313 // This is an AnyCC spill, we need a scratch register.
314 assert(FIPos==1 && "Bad frame index operand");
315 MachineOperand SpillReg = MI.getOperand(0);
316 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
317 assert(ScratchReg && "Could not scavenge register");
318 if (SpillReg.getReg()==BF::NCC) {
319 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
320 .addOperand(SpillReg);
321 BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
322 .addReg(ScratchReg).addImm(0);
324 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
325 .addOperand(SpillReg);
328 MI.setDesc(TII.get(BF::STORE8p_imm16));
329 MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
330 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
331 MI.getOperand(FIPos+1).setImm(Offset);
335 // This is an restore, we need a scratch register.
336 assert(FIPos==1 && "Bad frame index operand");
337 MachineOperand SpillReg = MI.getOperand(0);
338 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
339 assert(ScratchReg && "Could not scavenge register");
340 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
341 MI.getOperand(0).ChangeToRegister(ScratchReg, true);
342 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
343 MI.getOperand(FIPos+1).setImm(Offset);
345 if (SpillReg.getReg()==BF::CC) {
347 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
348 .addReg(ScratchReg, RegState::Kill);
350 // Restore NCC (CC = D==0)
351 BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
352 .addReg(ScratchReg, RegState::Kill)
358 llvm_unreachable("Cannot eliminate frame index");
364 void BlackfinRegisterInfo::
365 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
366 RegScavenger *RS) const {
367 MachineFrameInfo *MFI = MF.getFrameInfo();
368 const TargetRegisterClass *RC = BF::DPRegisterClass;
369 if (requiresRegisterScavenging(MF)) {
370 // Reserve a slot close to SP or frame pointer.
371 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
377 void BlackfinRegisterInfo::
378 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
381 // Emit a prologue that sets up a stack frame.
382 // On function entry, R0-R2 and P0 may hold arguments.
383 // R3, P1, and P2 may be used as scratch registers
384 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
385 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
386 MachineBasicBlock::iterator MBBI = MBB.begin();
387 MachineFrameInfo *MFI = MF.getFrameInfo();
388 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
390 int FrameSize = MFI->getStackSize();
392 FrameSize = (FrameSize+3) & ~3;
393 MFI->setStackSize(FrameSize);
397 assert(!MFI->adjustsStack() &&
398 "FP elimination on a non-leaf function is not supported");
399 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
403 // emit a LINK instruction
404 if (FrameSize <= 0x3ffff) {
405 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
409 // Frame is too big, do a manual LINK:
415 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
416 .addReg(BF::RETS, RegState::Kill);
417 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
418 .addReg(BF::FP, RegState::Kill);
419 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
421 loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
422 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
423 .addReg(BF::SP, RegState::Kill)
424 .addReg(BF::P1, RegState::Kill);
428 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
429 MachineBasicBlock &MBB) const {
430 MachineFrameInfo *MFI = MF.getFrameInfo();
431 MachineBasicBlock::iterator MBBI = prior(MBB.end());
432 DebugLoc dl = MBBI->getDebugLoc();
434 int FrameSize = MFI->getStackSize();
435 assert(FrameSize%4 == 0 && "Misaligned frame size");
438 assert(!MFI->adjustsStack() &&
439 "FP elimination on a non-leaf function is not supported");
440 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
444 // emit an UNLINK instruction
445 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
448 unsigned BlackfinRegisterInfo::getRARegister() const {
453 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
454 return hasFP(MF) ? BF::FP : BF::SP;
457 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
458 llvm_unreachable("What is the exception register");
462 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
463 llvm_unreachable("What is the exception handler register");
467 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
468 llvm_unreachable("What is the dwarf register number");
472 #include "BlackfinGenRegisterInfo.inc"