1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "BlackfinRegisterInfo.h"
17 #include "BlackfinSubtarget.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineLocation.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Type.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
35 const TargetInstrInfo &tii)
36 : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
43 static const unsigned CalleeSavedRegs[] = {
48 return CalleeSavedRegs;
51 const TargetRegisterClass* const *BlackfinRegisterInfo::
52 getCalleeSavedRegClasses(const MachineFunction *MF) const {
54 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
56 &DRegClass, &DRegClass, &DRegClass, &DRegClass,
57 &PRegClass, &PRegClass, &PRegClass,
59 return CalleeSavedRegClasses;
63 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
65 BitVector Reserved(getNumRegs());
77 Reserved.set(CYCLES).set(CYCLES2);
89 const TargetRegisterClass*
90 BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
91 assert(isPhysicalRegister(reg) && "reg must be a physical register");
93 // Pick the smallest register class of the right type that contains
95 const TargetRegisterClass* BestRC = 0;
96 for (regclass_iterator I = regclass_begin(), E = regclass_end();
98 const TargetRegisterClass* RC = *I;
99 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
100 (!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
104 assert(BestRC && "Couldn't find the register class");
108 // hasFP - Return true if the specified function should have a dedicated frame
109 // pointer register. This is true if the function has variable sized allocas or
110 // if frame pointer elimination is disabled.
111 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
112 const MachineFrameInfo *MFI = MF.getFrameInfo();
113 return NoFramePointerElim || MFI->hasCalls() || MFI->hasVarSizedObjects();
116 bool BlackfinRegisterInfo::
117 requiresRegisterScavenging(const MachineFunction &MF) const {
121 // Emit instructions to add delta to D/P register. ScratchReg must be of the
122 // same class as Reg (P).
123 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
124 MachineBasicBlock::iterator I,
131 if (isInt<7>(delta)) {
132 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
133 .addReg(Reg) // No kill on two-addr operand
138 // We must load delta into ScratchReg and add that.
139 loadConstant(MBB, I, DL, ScratchReg, delta);
140 if (BF::PRegClass.contains(Reg)) {
141 assert(BF::PRegClass.contains(ScratchReg) &&
142 "ScratchReg must be a P register");
143 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
144 .addReg(Reg, RegState::Kill)
145 .addReg(ScratchReg, RegState::Kill);
147 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
148 assert(BF::DRegClass.contains(ScratchReg) &&
149 "ScratchReg must be a D register");
150 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
151 .addReg(Reg, RegState::Kill)
152 .addReg(ScratchReg, RegState::Kill);
156 // Emit instructions to load a constant into D/P register
157 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
158 MachineBasicBlock::iterator I,
162 if (isInt<7>(value)) {
163 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
167 if (isUInt<16>(value)) {
168 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
172 if (isInt<16>(value)) {
173 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
177 // We must split into halves
179 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_hi16))
180 .addImm((value >> 16) & 0xffff)
181 .addReg(Reg, RegState::ImplicitDefine);
183 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_lo16))
184 .addImm(value & 0xffff)
185 .addReg(Reg, RegState::ImplicitKill)
186 .addReg(Reg, RegState::ImplicitDefine);
189 void BlackfinRegisterInfo::
190 eliminateCallFramePseudoInstr(MachineFunction &MF,
191 MachineBasicBlock &MBB,
192 MachineBasicBlock::iterator I) const {
193 if (!hasReservedCallFrame(MF)) {
194 int64_t Amount = I->getOperand(0).getImm();
196 assert(Amount%4 == 0 && "Unaligned call frame size");
197 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
198 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
200 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
201 "Unknown call frame pseudo instruction");
202 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
209 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
210 /// register first and then a spilled callee-saved register if that fails.
211 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
213 const TargetRegisterClass *RC,
215 assert(RS && "Register scavenging must be on");
216 unsigned Reg = RS->FindUnusedReg(RC);
218 Reg = RS->scavengeRegister(RC, II, SPAdj);
223 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
224 int SPAdj, FrameIndexValue *Value,
225 RegScavenger *RS) const {
226 MachineInstr &MI = *II;
227 MachineBasicBlock &MBB = *MI.getParent();
228 MachineFunction &MF = *MBB.getParent();
229 DebugLoc DL = MI.getDebugLoc();
232 for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
233 assert(FIPos < MI.getNumOperands() &&
234 "Instr doesn't have FrameIndex operand!");
236 int FrameIndex = MI.getOperand(FIPos).getIndex();
237 assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
238 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
239 + MI.getOperand(FIPos+1).getImm();
240 unsigned BaseReg = BF::FP;
242 assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
245 Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
248 bool isStore = false;
250 switch (MI.getOpcode()) {
254 assert(Offset%4 == 0 && "Unaligned i32 stack access");
255 assert(FIPos==1 && "Bad frame index operand");
256 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
257 MI.getOperand(FIPos+1).setImm(Offset);
258 if (isUInt<6>(Offset)) {
259 MI.setDesc(TII.get(isStore
260 ? BF::STORE32p_uimm6m4
261 : BF::LOAD32p_uimm6m4));
264 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
265 MI.setDesc(TII.get(isStore
266 ? BF::STORE32fp_nimm7m4
267 : BF::LOAD32fp_nimm7m4));
268 MI.getOperand(FIPos+1).setImm(-Offset);
271 if (isInt<18>(Offset)) {
272 MI.setDesc(TII.get(isStore
273 ? BF::STORE32p_imm18m4
274 : BF::LOAD32p_imm18m4));
277 // Use RegScavenger to calculate proper offset...
279 llvm_unreachable("Stack frame offset too big");
283 assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
284 unsigned DestReg = MI.getOperand(0).getReg();
285 // We need to produce a stack offset in a P register. We emit:
288 assert(FIPos==1 && "Bad frame index operand");
289 loadConstant(MBB, II, DL, DestReg, Offset);
290 MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
291 MI.getOperand(2).ChangeToRegister(BaseReg, false);
297 assert(Offset%2 == 0 && "Unaligned i16 stack access");
298 assert(FIPos==1 && "Bad frame index operand");
299 // We need a P register to use as an address
300 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
301 assert(ScratchReg && "Could not scavenge register");
302 loadConstant(MBB, II, DL, ScratchReg, Offset);
303 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
304 .addReg(ScratchReg, RegState::Kill)
306 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
307 MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
312 // This is an AnyCC spill, we need a scratch register.
313 assert(FIPos==1 && "Bad frame index operand");
314 MachineOperand SpillReg = MI.getOperand(0);
315 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
316 assert(ScratchReg && "Could not scavenge register");
317 if (SpillReg.getReg()==BF::NCC) {
318 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
319 .addOperand(SpillReg);
320 BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
321 .addReg(ScratchReg).addImm(0);
323 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
324 .addOperand(SpillReg);
327 MI.setDesc(TII.get(BF::STORE8p_imm16));
328 MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
329 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
330 MI.getOperand(FIPos+1).setImm(Offset);
334 // This is an restore, we need a scratch register.
335 assert(FIPos==1 && "Bad frame index operand");
336 MachineOperand SpillReg = MI.getOperand(0);
337 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
338 assert(ScratchReg && "Could not scavenge register");
339 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
340 MI.getOperand(0).ChangeToRegister(ScratchReg, true);
341 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
342 MI.getOperand(FIPos+1).setImm(Offset);
344 if (SpillReg.getReg()==BF::CC) {
346 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
347 .addReg(ScratchReg, RegState::Kill);
349 // Restore NCC (CC = D==0)
350 BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
351 .addReg(ScratchReg, RegState::Kill)
357 llvm_unreachable("Cannot eliminate frame index");
363 void BlackfinRegisterInfo::
364 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
365 RegScavenger *RS) const {
366 MachineFrameInfo *MFI = MF.getFrameInfo();
367 const TargetRegisterClass *RC = BF::DPRegisterClass;
368 if (requiresRegisterScavenging(MF)) {
369 // Reserve a slot close to SP or frame pointer.
370 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
376 void BlackfinRegisterInfo::
377 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
380 // Emit a prologue that sets up a stack frame.
381 // On function entry, R0-R2 and P0 may hold arguments.
382 // R3, P1, and P2 may be used as scratch registers
383 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
384 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
385 MachineBasicBlock::iterator MBBI = MBB.begin();
386 MachineFrameInfo *MFI = MF.getFrameInfo();
387 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
389 int FrameSize = MFI->getStackSize();
391 FrameSize = (FrameSize+3) & ~3;
392 MFI->setStackSize(FrameSize);
396 assert(!MFI->hasCalls() &&
397 "FP elimination on a non-leaf function is not supported");
398 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
402 // emit a LINK instruction
403 if (FrameSize <= 0x3ffff) {
404 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
408 // Frame is too big, do a manual LINK:
414 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
415 .addReg(BF::RETS, RegState::Kill);
416 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
417 .addReg(BF::FP, RegState::Kill);
418 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
420 loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
421 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
422 .addReg(BF::SP, RegState::Kill)
423 .addReg(BF::P1, RegState::Kill);
427 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
428 MachineBasicBlock &MBB) const {
429 MachineFrameInfo *MFI = MF.getFrameInfo();
430 MachineBasicBlock::iterator MBBI = prior(MBB.end());
431 DebugLoc dl = MBBI->getDebugLoc();
433 int FrameSize = MFI->getStackSize();
434 assert(FrameSize%4 == 0 && "Misaligned frame size");
437 assert(!MFI->hasCalls() &&
438 "FP elimination on a non-leaf function is not supported");
439 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
443 // emit an UNLINK instruction
444 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
447 unsigned BlackfinRegisterInfo::getRARegister() const {
452 BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
453 return hasFP(MF) ? BF::FP : BF::SP;
456 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
457 llvm_unreachable("What is the exception register");
461 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
462 llvm_unreachable("What is the exception handler register");
466 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
467 llvm_unreachable("What is the dwarf register number");
471 #include "BlackfinGenRegisterInfo.inc"