1 //===- BlackfinRegisterInfo.cpp - Blackfin Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Blackfin implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "BlackfinRegisterInfo.h"
17 #include "BlackfinSubtarget.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineLocation.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Type.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
34 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
35 const TargetInstrInfo &tii)
36 : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
41 BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
43 static const unsigned CalleeSavedRegs[] = {
48 return CalleeSavedRegs;
51 const TargetRegisterClass* const *BlackfinRegisterInfo::
52 getCalleeSavedRegClasses(const MachineFunction *MF) const {
54 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
56 &DRegClass, &DRegClass, &DRegClass, &DRegClass,
57 &PRegClass, &PRegClass, &PRegClass,
59 return CalleeSavedRegClasses;
63 BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
65 BitVector Reserved(getNumRegs());
77 const TargetRegisterClass*
78 BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
79 assert(isPhysicalRegister(reg) && "reg must be a physical register");
81 // Pick the smallest register class of the right type that contains
83 const TargetRegisterClass* BestRC = 0;
84 for (regclass_iterator I = regclass_begin(), E = regclass_end();
86 const TargetRegisterClass* RC = *I;
87 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
88 (!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
92 assert(BestRC && "Couldn't find the register class");
96 // hasFP - Return true if the specified function should have a dedicated frame
97 // pointer register. This is true if the function has variable sized allocas or
98 // if frame pointer elimination is disabled.
99 bool BlackfinRegisterInfo::hasFP(const MachineFunction &MF) const {
100 const MachineFrameInfo *MFI = MF.getFrameInfo();
101 return NoFramePointerElim || MFI->hasCalls() || MFI->hasVarSizedObjects();
104 bool BlackfinRegisterInfo::
105 requiresRegisterScavenging(const MachineFunction &MF) const {
109 // Emit instructions to add delta to D/P register. ScratchReg must be of the
110 // same class as Reg (P).
111 void BlackfinRegisterInfo::adjustRegister(MachineBasicBlock &MBB,
112 MachineBasicBlock::iterator I,
119 if (isImm<7>(delta)) {
120 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
121 .addReg(Reg) // No kill on two-addr operand
126 // We must load delta into ScratchReg and add that.
127 loadConstant(MBB, I, DL, ScratchReg, delta);
128 if (BF::PRegClass.contains(Reg)) {
129 assert(BF::PRegClass.contains(ScratchReg) &&
130 "ScratchReg must be a P register");
131 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
132 .addReg(Reg, RegState::Kill)
133 .addReg(ScratchReg, RegState::Kill);
135 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
136 assert(BF::DRegClass.contains(ScratchReg) &&
137 "ScratchReg must be a D register");
138 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
139 .addReg(Reg, RegState::Kill)
140 .addReg(ScratchReg, RegState::Kill);
144 // Emit instructions to load a constant into D/P register
145 void BlackfinRegisterInfo::loadConstant(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator I,
150 if (isImm<7>(value)) {
151 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
155 if (isUimm<16>(value)) {
156 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
160 if (isImm<16>(value)) {
161 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
165 // We must split into halves
167 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_hi16))
168 .addImm((value >> 16) & 0xffff)
169 .addReg(Reg, RegState::ImplicitDefine);
171 TII.get(BF::LOAD16i), getSubReg(Reg, bfin_subreg_lo16))
172 .addImm(value & 0xffff)
173 .addReg(Reg, RegState::ImplicitKill)
174 .addReg(Reg, RegState::ImplicitDefine);
177 void BlackfinRegisterInfo::
178 eliminateCallFramePseudoInstr(MachineFunction &MF,
179 MachineBasicBlock &MBB,
180 MachineBasicBlock::iterator I) const {
181 if (!hasReservedCallFrame(MF)) {
182 int64_t Amount = I->getOperand(0).getImm();
184 assert(Amount%4 == 0 && "Unaligned call frame size");
185 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
186 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
188 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
189 "Unknown call frame pseudo instruction");
190 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
197 /// findScratchRegister - Find a 'free' register. Try for a call-clobbered
198 /// register first and then a spilled callee-saved register if that fails.
199 static unsigned findScratchRegister(MachineBasicBlock::iterator II,
201 const TargetRegisterClass *RC,
203 assert(RS && "Register scavenging must be on");
204 unsigned Reg = RS->FindUnusedReg(RC, true);
206 Reg = RS->scavengeRegister(RC, II, SPAdj);
210 void BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
212 RegScavenger *RS) const {
213 MachineInstr &MI = *II;
214 MachineBasicBlock &MBB = *MI.getParent();
215 MachineFunction &MF = *MBB.getParent();
216 DebugLoc DL = MI.getDebugLoc();
219 for (FIPos=0; !MI.getOperand(FIPos).isFI(); ++FIPos) {
220 assert(FIPos < MI.getNumOperands() &&
221 "Instr doesn't have FrameIndex operand!");
223 int FrameIndex = MI.getOperand(FIPos).getIndex();
224 assert(FIPos+1 < MI.getNumOperands() && MI.getOperand(FIPos+1).isImm());
225 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex)
226 + MI.getOperand(FIPos+1).getImm();
227 unsigned BaseReg = BF::FP;
229 assert(SPAdj==0 && "Unexpected SP adjust in function with frame pointer");
232 Offset += MF.getFrameInfo()->getStackSize() + SPAdj;
235 bool isStore = false;
237 switch (MI.getOpcode()) {
241 assert(Offset%4 == 0 && "Unaligned i32 stack access");
242 assert(FIPos==1 && "Bad frame index operand");
243 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
244 MI.getOperand(FIPos+1).setImm(Offset);
245 if (isUimm<6>(Offset)) {
246 MI.setDesc(TII.get(isStore
247 ? BF::STORE32p_uimm6m4
248 : BF::LOAD32p_uimm6m4));
251 if (BaseReg == BF::FP && isUimm<7>(-Offset)) {
252 MI.setDesc(TII.get(isStore
253 ? BF::STORE32fp_nimm7m4
254 : BF::LOAD32fp_nimm7m4));
255 MI.getOperand(FIPos+1).setImm(-Offset);
258 if (isImm<18>(Offset)) {
259 MI.setDesc(TII.get(isStore
260 ? BF::STORE32p_imm18m4
261 : BF::LOAD32p_imm18m4));
264 // Use RegScavenger to calculate proper offset...
266 llvm_unreachable("Stack frame offset too big");
270 assert(MI.getOperand(0).isReg() && "ADD instruction needs a register");
271 unsigned DestReg = MI.getOperand(0).getReg();
272 // We need to produce a stack offset in a P register. We emit:
275 assert(FIPos==1 && "Bad frame index operand");
276 loadConstant(MBB, II, DL, DestReg, Offset);
277 MI.getOperand(1).ChangeToRegister(DestReg, false, false, true);
278 MI.getOperand(2).ChangeToRegister(BaseReg, false);
284 assert(Offset%2 == 0 && "Unaligned i16 stack access");
285 assert(FIPos==1 && "Bad frame index operand");
286 // We need a P register to use as an address
287 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
288 assert(ScratchReg && "Could not scavenge register");
289 loadConstant(MBB, II, DL, ScratchReg, Offset);
290 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
291 .addReg(ScratchReg, RegState::Kill)
293 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
294 MI.getOperand(1).ChangeToRegister(ScratchReg, false, false, true);
299 // This is an AnyCC spill, we need a scratch register.
300 assert(FIPos==1 && "Bad frame index operand");
301 MachineOperand SpillReg = MI.getOperand(0);
302 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
303 assert(ScratchReg && "Could not scavenge register");
304 if (SpillReg.getReg()==BF::NCC) {
305 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
306 .addOperand(SpillReg);
307 BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
308 .addReg(ScratchReg).addImm(0);
310 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
311 .addOperand(SpillReg);
314 MI.setDesc(TII.get(BF::STORE8p_imm16));
315 MI.getOperand(0).ChangeToRegister(ScratchReg, false, false, true);
316 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
317 MI.getOperand(FIPos+1).setImm(Offset);
321 // This is an restore, we need a scratch register.
322 assert(FIPos==1 && "Bad frame index operand");
323 MachineOperand SpillReg = MI.getOperand(0);
324 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
325 assert(ScratchReg && "Could not scavenge register");
326 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
327 MI.getOperand(0).ChangeToRegister(ScratchReg, true);
328 MI.getOperand(FIPos).ChangeToRegister(BaseReg, false);
329 MI.getOperand(FIPos+1).setImm(Offset);
331 if (SpillReg.getReg()==BF::CC) {
333 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
334 .addReg(ScratchReg, RegState::Kill);
336 // Restore NCC (CC = D==0)
337 BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
338 .addReg(ScratchReg, RegState::Kill)
344 llvm_unreachable("Cannot eliminate frame index");
349 void BlackfinRegisterInfo::
350 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
351 RegScavenger *RS) const {
352 MachineFrameInfo *MFI = MF.getFrameInfo();
353 const TargetRegisterClass *RC = BF::DPRegisterClass;
354 if (requiresRegisterScavenging(MF)) {
355 // Reserve a slot close to SP or frame pointer.
356 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
357 RC->getAlignment()));
361 void BlackfinRegisterInfo::
362 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
365 // Emit a prologue that sets up a stack frame.
366 // On function entry, R0-R2 and P0 may hold arguments.
367 // R3, P1, and P2 may be used as scratch registers
368 void BlackfinRegisterInfo::emitPrologue(MachineFunction &MF) const {
369 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
370 MachineBasicBlock::iterator MBBI = MBB.begin();
371 MachineFrameInfo *MFI = MF.getFrameInfo();
372 DebugLoc dl = (MBBI != MBB.end()
373 ? MBBI->getDebugLoc()
374 : DebugLoc::getUnknownLoc());
376 int FrameSize = MFI->getStackSize();
378 FrameSize = (FrameSize+3) & ~3;
379 MFI->setStackSize(FrameSize);
383 assert(!MFI->hasCalls() &&
384 "FP elimination on a non-leaf function is not supported");
385 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
389 // emit a LINK instruction
390 if (FrameSize <= 0x3ffff) {
391 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
395 // Frame is too big, do a manual LINK:
401 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
402 .addReg(BF::RETS, RegState::Kill);
403 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
404 .addReg(BF::FP, RegState::Kill);
405 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
407 loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
408 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
409 .addReg(BF::SP, RegState::Kill)
410 .addReg(BF::P1, RegState::Kill);
414 void BlackfinRegisterInfo::emitEpilogue(MachineFunction &MF,
415 MachineBasicBlock &MBB) const {
416 MachineFrameInfo *MFI = MF.getFrameInfo();
417 MachineBasicBlock::iterator MBBI = prior(MBB.end());
418 DebugLoc dl = MBBI->getDebugLoc();
420 int FrameSize = MFI->getStackSize();
421 assert(FrameSize%4 == 0 && "Misaligned frame size");
424 assert(!MFI->hasCalls() &&
425 "FP elimination on a non-leaf function is not supported");
426 adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
430 // emit an UNLINK instruction
431 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
434 unsigned BlackfinRegisterInfo::getRARegister() const {
438 unsigned BlackfinRegisterInfo::getFrameRegister(MachineFunction &MF) const {
439 return hasFP(MF) ? BF::FP : BF::SP;
443 BlackfinRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
444 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
445 MachineFrameInfo *MFI = MF.getFrameInfo();
446 return MFI->getObjectOffset(FI) + MFI->getStackSize() -
447 TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
450 unsigned BlackfinRegisterInfo::getEHExceptionRegister() const {
451 llvm_unreachable("What is the exception register");
455 unsigned BlackfinRegisterInfo::getEHHandlerRegister() const {
456 llvm_unreachable("What is the exception handler register");
460 int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
461 llvm_unreachable("What is the dwarf register number");
465 #include "BlackfinGenRegisterInfo.inc"