lib/Target/Blackfin/README.txt

   1 //===-- README.txt - Notes for Blackfin Target ------------------*- org -*-===//
   2
   3 * Condition codes
   4 ** DONE Problem with asymmetric SETCC operations
   5 The instruction
   6
   7   CC = R0 < 2
   8
   9 is not symmetric - there is no R0 > 2 instruction. On the other hand, IF CC
  10 JUMP can take both CC and !CC as a condition. We cannot pattern-match (brcond
  11 (not cc), target), the DAG optimizer removes that kind of thing.
  12
  13 This is handled by creating a pseudo-register NCC that aliases CC. Register
  14 classes JustCC and NotCC are used to control the inversion of CC.
  15
  16 ** DONE CC as an i32 register
  17 The AnyCC register class pretends to hold i32 values. It can only represent the
  18 values 0 and 1, but we can copy to and from the D class. This hack makes it
  19 possible to represent the setcc instruction without having i1 as a legal type.
  20
  21 In most cases, the CC register is set by a "CC = .." or BITTST instruction, and
  22 then used in a conditional branch or move. The code generator thinks it is
  23 moving 32 bits, but the value stays in CC. In other cases, the result of a
  24 comparison is actually used as am i32 number, and CC will be copied to a D
  25 register.
  26
  27 * Stack frames
  28 ** TODO Use Push/Pop instructions
  29 We should use the push/pop instructions when saving callee-saved
  30 registers. The are smaller, and we may even use push multiple instructions.
  31
  32 ** TODO requiresRegisterScavenging
  33 We need more intelligence in determining when the scavenger is needed. We
  34 should keep track of:
  35 - Spilling D16 registers
  36 - Spilling AnyCC registers
  37
  38 * Assembler
  39 ** TODO Implement PrintGlobalVariable
  40 ** TODO Remove LOAD32sym
  41 It's a hack combining two instructions by concatenation.
  42
  43 * Inline Assembly
  44
  45 These are the GCC constraints from bfin/constraints.md:
  46
  47 | Code  | Register class                            | LLVM |
  48 |-------+-------------------------------------------+------|
  49 | a     | P                                         | C    |
  50 | d     | D                                         | C    |
  51 | z     | Call clobbered P (P0, P1, P2)             | X    |
  52 | D     | EvenD                                     | X    |
  53 | W     | OddD                                      | X    |
  54 | e     | Accu                                      | C    |
  55 | A     | A0                                        | S    |
  56 | B     | A1                                        | S    |
  57 | b     | I                                         | C    |
  58 | v     | B                                         | C    |
  59 | f     | M                                         | C    |
  60 | c     | Circular I, B, L                          | X    |
  61 | C     | JustCC                                    | S    |
  62 | t     | LoopTop                                   | X    |
  63 | u     | LoopBottom                                | X    |
  64 | k     | LoopCount                                 | X    |
  65 | x     | GR                                        | C    |
  66 | y     | RET*, ASTAT, SEQSTAT, USP                 | X    |
  67 | w     | ALL                                       | C    |
  68 | Z     | The FD-PIC GOT pointer (P3)               | S    |
  69 | Y     | The FD-PIC function pointer register (P1) | S    |
  70 | q0-q7 | R0-R7 individually                        |      |
  71 | qA    | P0                                        |      |
  72 |-------+-------------------------------------------+------|
  73 | Code  | Constant                                  |      |
  74 |-------+-------------------------------------------+------|
  75 | J     | 1<<N, N<32                                |      |
  76 | Ks3   | imm3                                      |      |
  77 | Ku3   | uimm3                                     |      |
  78 | Ks4   | imm4                                      |      |
  79 | Ku4   | uimm4                                     |      |
  80 | Ks5   | imm5                                      |      |
  81 | Ku5   | uimm5                                     |      |
  82 | Ks7   | imm7                                      |      |
  83 | KN7   | -imm7                                     |      |
  84 | Ksh   | imm16                                     |      |
  85 | Kuh   | uimm16                                    |      |
  86 | L     | ~(1<<N)                                   |      |
  87 | M1    | 0xff                                      |      |
  88 | M2    | 0xffff                                    |      |
  89 | P0-P4 | 0-4                                       |      |
  90 | PA    | Macflag, not M                            |      |
  91 | PB    | Macflag, only M                           |      |
  92 | Q     | Symbol                                    |      |
  93
  94 ** TODO Support all register classes
  95 * DAG combiner
  96 ** Create test case for each Illegal SETCC case
  97 The DAG combiner may someimes produce illegal i16 SETCC instructions.
  98
  99 *** TODO SETCC (ctlz x), 5) == const
 100 *** TODO SETCC (and load, const) == const
 101 *** DONE SETCC (zext x) == const
 102 *** TODO SETCC (sext x) == const
 103
 104 * Instruction selection
 105 ** TODO Better imediate constants
 106 Like ARM, build constants as small imm + shift.
 107
 108 ** TODO Implement cycle counter
 109 We have CYCLES and CYCLES2 registers, but the readcyclecounter intrinsic wants
 110 to return i64, and the code generator doesn't know how to legalize that.
 111
 112 ** TODO Instruction alternatives
 113 Some instructions come in different variants for example:
 114
 115   D = D + D
 116   P = P + P
 117
 118 Cross combinations are not allowed:
 119
 120   P = D + D (bad)
 121
 122 Similarly for the subreg pseudo-instructions:
 123
 124  D16L = EXTRACT_SUBREG D16, bfin_subreg_lo16
 125  P16L = EXTRACT_SUBREG P16, bfin_subreg_lo16
 126
 127 We want to take advantage of the alternative instructions. This could be done by
 128 changing the DAG after instruction selection.
 129
 130
 131 ** Multipatterns for load/store
 132 We should try to identify multipatterns for load and store instructions. The
 133 available instruction matrix is a bit irregular.
 134
 135 Loads:
 136
 137 | Addr       | D | P | D 16z | D 16s | D16 | D 8z | D 8s |
 138 |------------+---+---+-------+-------+-----+------+------|
 139 | P          | * | * | *     | *     | *   | *    | *    |
 140 | P++        | * | * | *     | *     |     | *    | *    |
 141 | P--        | * | * | *     | *     |     | *    | *    |
 142 | P+uimm5m2  |   |   | *     | *     |     |      |      |
 143 | P+uimm6m4  | * | * |       |       |     |      |      |
 144 | P+imm16    |   |   |       |       |     | *    | *    |
 145 | P+imm17m2  |   |   | *     | *     |     |      |      |
 146 | P+imm18m4  | * | * |       |       |     |      |      |
 147 | P++P       | * |   | *     | *     | *   |      |      |
 148 | FP-uimm7m4 | * | * |       |       |     |      |      |
 149 | I          | * |   |       |       | *   |      |      |
 150 | I++        | * |   |       |       | *   |      |      |
 151 | I--        | * |   |       |       | *   |      |      |
 152 | I++M       | * |   |       |       |     |      |      |
 153
 154 Stores:
 155
 156 | Addr       | D | P | D16H | D16L | D 8 |
 157 |------------+---+---+------+------+-----|
 158 | P          | * | * | *    | *    | *   |
 159 | P++        | * | * |      | *    | *   |
 160 | P--        | * | * |      | *    | *   |
 161 | P+uimm5m2  |   |   |      | *    |     |
 162 | P+uimm6m4  | * | * |      |      |     |
 163 | P+imm16    |   |   |      |      | *   |
 164 | P+imm17m2  |   |   |      | *    |     |
 165 | P+imm18m4  | * | * |      |      |     |
 166 | P++P       | * |   | *    | *    |     |
 167 | FP-uimm7m4 | * | * |      |      |     |
 168 | I          | * |   | *    | *    |     |
 169 | I++        | * |   | *    | *    |     |
 170 | I--        | * |   | *    | *    |     |
 171 | I++M       | * |   |      |      |     |
 172