1 //===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This is the top level entry point for the STI Cell SPU target machine.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing.
17 include "../Target.td"
19 //===----------------------------------------------------------------------===//
20 // Register File Description
21 //===----------------------------------------------------------------------===//
23 include "SPURegisterInfo.td"
25 //===----------------------------------------------------------------------===//
26 // Instruction formats, instructions
27 //===----------------------------------------------------------------------===//
30 include "SPUOperands.td"
31 include "SPUSchedule.td"
32 include "SPUInstrFormats.td"
33 include "SPUInstrInfo.td"
35 //===----------------------------------------------------------------------===//
36 // Subtarget features:
37 //===----------------------------------------------------------------------===//
39 def DefaultProc: SubtargetFeature<"", "ProcDirective", "SPU::DEFAULT_PROC", "">;
41 SubtargetFeature<"large_mem","UseLargeMem", "true",
42 "Use large (>256) LSA memory addressing [default = false]">;
44 def SPURev0 : Processor<"v0", SPUItineraries, [DefaultProc]>;
46 //===----------------------------------------------------------------------===//
47 // Calling convention:
48 //===----------------------------------------------------------------------===//
50 include "SPUCallingConv.td"
54 def SPUInstrInfo : InstrInfo {
55 let isLittleEndianEncoding = 1;
59 let InstructionSet = SPUInstrInfo;