1 //===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
6 // This file was developed by a team from the Computer Systems Research
7 // Department at The Aerospace Corporation.
9 // See README.txt for details.
10 //===----------------------------------------------------------------------===//
12 // This is the top level entry point for the STI Cell SPU target machine.
14 //===----------------------------------------------------------------------===//
16 // Get the target-independent interfaces which we are implementing.
18 include "../Target.td"
20 //===----------------------------------------------------------------------===//
21 // Register File Description
22 //===----------------------------------------------------------------------===//
24 include "SPURegisterInfo.td"
26 //===----------------------------------------------------------------------===//
27 // Instruction formats, instructions
28 //===----------------------------------------------------------------------===//
31 include "SPUOperands.td"
32 include "SPUSchedule.td"
33 include "SPUInstrFormats.td"
34 include "SPUInstrInfo.td"
36 //===----------------------------------------------------------------------===//
37 // Subtarget features:
38 //===----------------------------------------------------------------------===//
40 def DefaultProc: SubtargetFeature<"", "ProcDirective", "SPU::DEFAULT_PROC", "">;
42 SubtargetFeature<"large_mem","UseLargeMem", "true",
43 "Use large (>256) LSA memory addressing [default = false]">;
45 def SPURev0 : Processor<"v0", SPUItineraries, [DefaultProc]>;
47 //===----------------------------------------------------------------------===//
48 // Calling convention:
49 //===----------------------------------------------------------------------===//
51 include "SPUCallingConv.td"
55 def SPUInstrInfo : InstrInfo {
56 let isLittleEndianEncoding = 1;
60 let InstructionSet = SPUInstrInfo;