1 //====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
3 // Cell SPU 64-bit operations
5 // Primary author: Scott Michel (scottm@aero.org)
6 //===----------------------------------------------------------------------===//
8 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
11 // 1. The instruction sequences for vector vice scalar differ by a
12 // constant. In the scalar case, we're only interested in the
13 // top two 32-bit slots, whereas we're interested in an exact
14 // all-four-slot match in the vector case.
16 // 2. There are no "immediate" forms, since loading 64-bit constants
17 // could be a constant pool load.
19 // 3. i64 setcc results are i32, which are subsequently converted to a FSM
20 // mask when used in a select pattern.
22 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
23 // [Note: this may be moot, since gb produces v4i32 or r32.]
25 // M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!)
26 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
28 // selb instruction definition for i64. Note that the selection mask is
29 // a vector, produced by various forms of FSM:
31 SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
34 // select the negative condition:
35 class I64SELECTNegCond<PatFrag cond, CodeFrag compare>:
36 Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
37 (SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 compare.Fragment))>;
39 // setcc the negative condition:
40 class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
41 Pat<(cond R64C:$rA, R64C:$rB),
42 (XORIr32 compare.Fragment, -1)>;
44 // The i64 seteq fragment that does the scalar->vector conversion and
47 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA),
48 (ORv2i64_i64 R64C:$rB))),
52 // The i64 seteq fragment that does the vector comparison
54 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)),
57 // i64 seteq (equality): the setcc result is i32, which is converted to a
58 // vector FSM mask when used in a select pattern.
60 // v2i64 seteq (equality): the setcc result is v4i32
61 multiclass CompareEqual64 {
62 // Plain old comparison, converts back to i32 scalar
63 def r64: CodeFrag<(ORi32_v4i32 CEQr64compare.Fragment)>;
64 def v2i64: CodeFrag<(ORi32_v4i32 CEQv2i64compare.Fragment)>;
66 // SELB mask from FSM:
67 def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQr64compare.Fragment))>;
68 def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQv2i64compare.Fragment))>;
71 defm I64EQ: CompareEqual64;
73 def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
74 def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
76 def : Pat<(select R32C:$rC, R64C:$rB, R64C:$rA),
77 (SELBr64_cond R64C:$rA, R64C:$rB, (FSMr32 R32C:$rC))>;
80 def : I64SETCCNegCond<setne, I64EQr64>;
81 def : I64SELECTNegCond<setne, I64EQr64>;