1 //====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====//
3 // Cell SPU 64-bit operations
5 // Primary author: Scott Michel (scottm@aero.org)
6 //===----------------------------------------------------------------------===//
8 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
11 // 1. The instruction sequences for vector vice scalar differ by a
12 // constant. In the scalar case, we're only interested in the
13 // top two 32-bit slots, whereas we're interested in an exact
14 // all-four-slot match in the vector case.
16 // 2. There are no "immediate" forms, since loading 64-bit constants
17 // could be a constant pool load.
19 // 3. i64 setcc results are i32, which are subsequently converted to a FSM
20 // mask when used in a select pattern.
22 // 4. v2i64 setcc results are v4i32, which can be converted to a FSM mask (TODO)
23 // [Note: this may be moot, since gb produces v4i32 or r32.]
25 // 5. The code sequences for r64 and v2i64 are probably overly conservative,
26 // compared to the code that gcc produces.
28 // M00$E B!tes Kan be Pretty N@sTi!!!!! (appologies to Monty!)
29 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
31 // selb instruction definition for i64. Note that the selection mask is
32 // a vector, produced by various forms of FSM:
34 SELBInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB, VECREG:$rC),
37 // select the negative condition:
38 class I64SELECTNegCond<PatFrag cond, CodeFrag compare>:
39 Pat<(select (i32 (cond R64C:$rA, R64C:$rB)), R64C:$rTrue, R64C:$rFalse),
40 (SELBr64_cond R64C:$rTrue, R64C:$rFalse, (FSMr32 compare.Fragment))>;
42 // setcc the negative condition:
43 class I64SETCCNegCond<PatFrag cond, CodeFrag compare>:
44 Pat<(cond R64C:$rA, R64C:$rB),
45 (XORIr32 compare.Fragment, -1)>;
47 // The generic i64 select pattern, which assumes that the comparison result
48 // is in a 32-bit register that contains a select mask pattern (i.e., gather
51 def : Pat<(select R32C:$rC, R64C:$rB, R64C:$rA),
52 (SELBr64_cond R64C:$rA, R64C:$rB, (FSMr32 R32C:$rC))>;
54 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
55 // The i64 seteq fragment that does the scalar->vector conversion and
58 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (ORv2i64_i64 R64C:$rA),
59 (ORv2i64_i64 R64C:$rB))), 0xb)>;
61 // The i64 seteq fragment that does the vector comparison
63 CodeFrag<(CEQIv4i32 (GBv4i32 (CEQv4i32 VECREG:$rA, VECREG:$rB)), 0xf)>;
65 // i64 seteq (equality): the setcc result is i32, which is converted to a
66 // vector FSM mask when used in a select pattern.
68 // v2i64 seteq (equality): the setcc result is v4i32
69 multiclass CompareEqual64 {
70 // Plain old comparison, converts back to i32 scalar
71 def r64: CodeFrag<(ORi32_v4i32 CEQr64compare.Fragment)>;
72 def v2i64: CodeFrag<(ORi32_v4i32 CEQv2i64compare.Fragment)>;
74 // SELB mask from FSM:
75 def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQr64compare.Fragment))>;
76 def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CEQv2i64compare.Fragment))>;
79 defm I64EQ: CompareEqual64;
81 def : Pat<(seteq R64C:$rA, R64C:$rB), I64EQr64.Fragment>;
82 def : Pat<(seteq (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)), I64EQv2i64.Fragment>;
85 def : I64SETCCNegCond<setne, I64EQr64>;
86 def : I64SELECTNegCond<setne, I64EQr64>;
88 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
90 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
93 CodeFrag<(CLGTv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
96 CodeFrag<(CEQv4i32 (ORv2i64_i64 R64C:$rA), (ORv2i64_i64 R64C:$rB))>;
99 CodeFrag<(SELBv2i64 CLGTr64ugt.Fragment,
100 (XSWDv2i64 CLGTr64ugt.Fragment),
101 CLGTr64eq.Fragment)>;
104 CodeFrag<(CLGTv4i32 VECREG:$rA, VECREG:$rB)>;
107 CodeFrag<(CEQv4i32 VECREG:$rA, VECREG:$rB)>;
109 def CLGTv2i64compare:
110 CodeFrag<(SELBv2i64 CLGTv2i64ugt.Fragment,
111 (XSWDv2i64 CLGTr64ugt.Fragment),
112 CLGTv2i64eq.Fragment)>;
114 multiclass CompareLogicalGreaterThan64 {
115 // Plain old comparison, converts back to i32 scalar
116 def r64: CodeFrag<(ORi32_v4i32 CLGTr64compare.Fragment)>;
117 def v2i64: CodeFrag<CLGTv2i64compare.Fragment>;
119 // SELB mask from FSM:
120 def r64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTr64compare.Fragment))>;
121 def v2i64mask: CodeFrag<(ORi32_v4i32 (FSMv4i32 CLGTv2i64compare.Fragment))>;
124 defm I64LGT: CompareLogicalGreaterThan64;
126 def : Pat<(setugt R64C:$rA, R64C:$rB), I64LGTr64.Fragment>;
127 def : Pat<(setugt (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
128 I64LGTv2i64.Fragment>;
131 def : I64SETCCNegCond<setule, I64LGTr64>;
132 def : I64SELECTNegCond<setule, I64LGTr64>;