1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSExtValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSExtValue());
54 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
56 isI32IntU10Immediate(ConstantSDNode *CN)
58 return isU10Constant(CN->getSExtValue());
61 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
63 isI16IntS10Immediate(ConstantSDNode *CN)
65 return isS10Constant(CN->getSExtValue());
68 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
70 isI16IntS10Immediate(SDNode *N)
72 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
73 return (CN != 0 && isI16IntS10Immediate(CN));
76 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
78 isI16IntU10Immediate(ConstantSDNode *CN)
80 return isU10Constant((short) CN->getZExtValue());
83 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
85 isI16IntU10Immediate(SDNode *N)
87 return (N->getOpcode() == ISD::Constant
88 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
91 //! ConstantSDNode predicate for signed 16-bit values
93 \arg CN The constant SelectionDAG node holding the value
94 \arg Imm The returned 16-bit value, if returning true
96 This predicate tests the value in \a CN to see whether it can be
97 represented as a 16-bit, sign-extended quantity. Returns true if
101 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
103 MVT vt = CN->getValueType(0);
104 Imm = (short) CN->getZExtValue();
105 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
107 } else if (vt == MVT::i32) {
108 int32_t i_val = (int32_t) CN->getZExtValue();
109 short s_val = (short) i_val;
110 return i_val == s_val;
112 int64_t i_val = (int64_t) CN->getZExtValue();
113 short s_val = (short) i_val;
114 return i_val == s_val;
120 //! SDNode predicate for signed 16-bit values.
122 isIntS16Immediate(SDNode *N, short &Imm)
124 return (N->getOpcode() == ISD::Constant
125 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
128 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
130 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
132 MVT vt = FPN->getValueType(0);
133 if (vt == MVT::f32) {
134 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
135 int sval = (int) ((val << 16) >> 16);
144 isHighLow(const SDValue &Op)
146 return (Op.getOpcode() == SPUISD::IndirectAddr
147 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
148 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
149 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
150 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
153 //===------------------------------------------------------------------===//
154 //! MVT to "useful stuff" mapping structure:
156 struct valtype_map_s {
158 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
159 bool ldresult_imm; /// LDRESULT instruction requires immediate?
160 unsigned lrinst; /// LR instruction
163 const valtype_map_s valtype_map[] = {
164 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
165 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
166 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
167 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
168 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
169 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
170 // vector types... (sigh!)
171 { MVT::v16i8, 0, false, SPU::LRv16i8 },
172 { MVT::v8i16, 0, false, SPU::LRv8i16 },
173 { MVT::v4i32, 0, false, SPU::LRv4i32 },
174 { MVT::v2i64, 0, false, SPU::LRv2i64 },
175 { MVT::v4f32, 0, false, SPU::LRv4f32 },
176 { MVT::v2f64, 0, false, SPU::LRv2f64 }
179 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
181 const valtype_map_s *getValueTypeMapEntry(MVT VT)
183 const valtype_map_s *retval = 0;
184 for (size_t i = 0; i < n_valtype_map; ++i) {
185 if (valtype_map[i].VT == VT) {
186 retval = valtype_map + i;
194 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
207 //===--------------------------------------------------------------------===//
208 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
209 /// instructions for SelectionDAG operations.
211 class SPUDAGToDAGISel :
212 public SelectionDAGISel
214 SPUTargetMachine &TM;
215 SPUTargetLowering &SPUtli;
216 unsigned GlobalBaseReg;
219 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
220 SelectionDAGISel(tm),
222 SPUtli(*tm.getTargetLowering())
225 virtual bool runOnFunction(Function &Fn) {
226 // Make sure we re-emit a set of the global base reg if necessary
228 SelectionDAGISel::runOnFunction(Fn);
232 /// getI32Imm - Return a target constant with the specified value, of type
234 inline SDValue getI32Imm(uint32_t Imm) {
235 return CurDAG->getTargetConstant(Imm, MVT::i32);
238 /// getI64Imm - Return a target constant with the specified value, of type
240 inline SDValue getI64Imm(uint64_t Imm) {
241 return CurDAG->getTargetConstant(Imm, MVT::i64);
244 /// getSmallIPtrImm - Return a target constant of pointer type.
245 inline SDValue getSmallIPtrImm(unsigned Imm) {
246 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
249 SDNode *emitBuildVector(SDValue build_vec) {
250 MVT vecVT = build_vec.getValueType();
251 SDNode *bvNode = build_vec.getNode();
252 DebugLoc dl = bvNode->getDebugLoc();
254 // Check to see if this vector can be represented as a CellSPU immediate
255 // constant by invoking all of the instruction selection predicates:
256 if (((vecVT == MVT::v8i16) &&
257 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
258 ((vecVT == MVT::v4i32) &&
259 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
260 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
261 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
262 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
263 ((vecVT == MVT::v2i64) &&
264 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
265 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
266 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
267 return Select(build_vec);
269 // No, need to emit a constant pool spill:
270 std::vector<Constant*> CV;
272 for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
273 ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
274 CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
277 Constant *CP = ConstantVector::get(CV);
278 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
279 unsigned Alignment = 1 << cast<ConstantPoolSDNode > (CPIdx)->getAlignment();
280 SDValue CGPoolOffset =
281 SPU::LowerConstantPool(CPIdx, *CurDAG,
282 SPUtli.getSPUTargetMachine());
283 return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl,
284 CurDAG->getEntryNode(), CGPoolOffset,
285 PseudoSourceValue::getConstantPool(), 0,
289 /// Select - Convert the specified operand from a target-independent to a
290 /// target-specific node if it hasn't already been changed.
291 SDNode *Select(SDValue Op);
293 //! Emit the instruction sequence for i64 shl
294 SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
296 //! Emit the instruction sequence for i64 srl
297 SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
299 //! Emit the instruction sequence for i64 sra
300 SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
302 //! Emit the necessary sequence for loading i64 constants:
303 SDNode *SelectI64Constant(SDValue &Op, MVT OpVT);
305 //! Returns true if the address N is an A-form (local store) address
306 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
309 //! D-form address predicate
310 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
313 /// Alternate D-form address using i7 offset predicate
314 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
317 /// D-form address selection workhorse
318 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
319 SDValue &Base, int minOffset, int maxOffset);
321 //! Address predicate if N can be expressed as an indexed [r+r] operation.
322 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
325 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
326 /// inline asm expressions.
327 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
329 std::vector<SDValue> &OutOps) {
331 switch (ConstraintCode) {
332 default: return true;
334 if (!SelectDFormAddr(Op, Op, Op0, Op1)
335 && !SelectAFormAddr(Op, Op, Op0, Op1))
336 SelectXFormAddr(Op, Op, Op0, Op1);
338 case 'o': // offsetable
339 if (!SelectDFormAddr(Op, Op, Op0, Op1)
340 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
342 Op1 = getSmallIPtrImm(0);
345 case 'v': // not offsetable
347 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
349 SelectAddrIdxOnly(Op, Op, Op0, Op1);
354 OutOps.push_back(Op0);
355 OutOps.push_back(Op1);
359 /// InstructionSelect - This callback is invoked by
360 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
361 virtual void InstructionSelect();
363 virtual const char *getPassName() const {
364 return "Cell SPU DAG->DAG Pattern Instruction Selection";
367 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
368 /// this target when scheduling the DAG.
369 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
370 const TargetInstrInfo *II = TM.getInstrInfo();
371 assert(II && "No InstrInfo?");
372 return new SPUHazardRecognizer(*II);
375 // Include the pieces autogenerated from the target description.
376 #include "SPUGenDAGISel.inc"
381 /// InstructionSelect - This callback is invoked by
382 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
384 SPUDAGToDAGISel::InstructionSelect()
388 // Select target instructions for the DAG.
390 CurDAG->RemoveDeadNodes();
394 \arg Op The ISD instruction operand
395 \arg N The address to be tested
396 \arg Base The base address
397 \arg Index The base address index
400 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
402 // These match the addr256k operand type:
403 MVT OffsVT = MVT::i16;
404 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
406 switch (N.getOpcode()) {
408 case ISD::ConstantPool:
409 case ISD::GlobalAddress:
410 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
414 case ISD::TargetConstant:
415 case ISD::TargetGlobalAddress:
416 case ISD::TargetJumpTable:
417 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
418 << "A-form address.\n";
422 case SPUISD::AFormAddr:
423 // Just load from memory if there's only a single use of the location,
424 // otherwise, this will get handled below with D-form offset addresses
426 SDValue Op0 = N.getOperand(0);
427 switch (Op0.getOpcode()) {
428 case ISD::TargetConstantPool:
429 case ISD::TargetJumpTable:
434 case ISD::TargetGlobalAddress: {
435 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
436 GlobalValue *GV = GSDN->getGlobal();
437 if (GV->getAlignment() == 16) {
452 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
454 const int minDForm2Offset = -(1 << 7);
455 const int maxDForm2Offset = (1 << 7) - 1;
456 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
461 \arg Op The ISD instruction (ignored)
462 \arg N The address to be tested
463 \arg Base Base address register/pointer
464 \arg Index Base address index
466 Examine the input address by a base register plus a signed 10-bit
467 displacement, [r+I10] (D-form address).
469 \return true if \a N is a D-form address with \a Base and \a Index set
470 to non-empty SDValue instances.
473 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
475 return DFormAddressPredicate(Op, N, Base, Index,
476 SPUFrameInfo::minFrameOffset(),
477 SPUFrameInfo::maxFrameOffset());
481 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
482 SDValue &Index, int minOffset,
484 unsigned Opc = N.getOpcode();
485 MVT PtrTy = SPUtli.getPointerTy();
487 if (Opc == ISD::FrameIndex) {
488 // Stack frame index must be less than 512 (divided by 16):
489 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
490 int FI = int(FIN->getIndex());
491 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
493 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
494 Base = CurDAG->getTargetConstant(0, PtrTy);
495 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
498 } else if (Opc == ISD::ADD) {
499 // Generated by getelementptr
500 const SDValue Op0 = N.getOperand(0);
501 const SDValue Op1 = N.getOperand(1);
503 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
504 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
505 Base = CurDAG->getTargetConstant(0, PtrTy);
508 } else if (Op1.getOpcode() == ISD::Constant
509 || Op1.getOpcode() == ISD::TargetConstant) {
510 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
511 int32_t offset = int32_t(CN->getSExtValue());
513 if (Op0.getOpcode() == ISD::FrameIndex) {
514 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
515 int FI = int(FIN->getIndex());
516 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
517 << " frame index = " << FI << "\n");
519 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
520 Base = CurDAG->getTargetConstant(offset, PtrTy);
521 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
524 } else if (offset > minOffset && offset < maxOffset) {
525 Base = CurDAG->getTargetConstant(offset, PtrTy);
529 } else if (Op0.getOpcode() == ISD::Constant
530 || Op0.getOpcode() == ISD::TargetConstant) {
531 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
532 int32_t offset = int32_t(CN->getSExtValue());
534 if (Op1.getOpcode() == ISD::FrameIndex) {
535 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
536 int FI = int(FIN->getIndex());
537 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
538 << " frame index = " << FI << "\n");
540 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
541 Base = CurDAG->getTargetConstant(offset, PtrTy);
542 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
545 } else if (offset > minOffset && offset < maxOffset) {
546 Base = CurDAG->getTargetConstant(offset, PtrTy);
551 } else if (Opc == SPUISD::IndirectAddr) {
552 // Indirect with constant offset -> D-Form address
553 const SDValue Op0 = N.getOperand(0);
554 const SDValue Op1 = N.getOperand(1);
556 if (Op0.getOpcode() == SPUISD::Hi
557 && Op1.getOpcode() == SPUISD::Lo) {
558 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
559 Base = CurDAG->getTargetConstant(0, PtrTy);
562 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
566 if (isa<ConstantSDNode>(Op1)) {
567 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
568 offset = int32_t(CN->getSExtValue());
570 } else if (isa<ConstantSDNode>(Op0)) {
571 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
572 offset = int32_t(CN->getSExtValue());
576 if (offset >= minOffset && offset <= maxOffset) {
577 Base = CurDAG->getTargetConstant(offset, PtrTy);
582 } else if (Opc == SPUISD::AFormAddr) {
583 Base = CurDAG->getTargetConstant(0, N.getValueType());
586 } else if (Opc == SPUISD::LDRESULT) {
587 Base = CurDAG->getTargetConstant(0, N.getValueType());
590 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
591 unsigned OpOpc = Op.getOpcode();
593 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
594 // Direct load/store without getelementptr
597 // Get the register from CopyFromReg
598 if (Opc == ISD::CopyFromReg)
599 Addr = N.getOperand(1);
601 Addr = N; // Register
603 Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
605 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
606 if (Offs.getOpcode() == ISD::UNDEF)
607 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
614 /* If otherwise unadorned, default to D-form address with 0 offset: */
615 if (Opc == ISD::CopyFromReg) {
616 Index = N.getOperand(1);
621 Base = CurDAG->getTargetConstant(0, Index.getValueType());
630 \arg Op The ISD instruction operand
631 \arg N The address operand
632 \arg Base The base pointer operand
633 \arg Index The offset/index operand
635 If the address \a N can be expressed as an A-form or D-form address, returns
636 false. Otherwise, creates two operands, Base and Index that will become the
637 (r)(r) X-form address.
640 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
642 if (!SelectAFormAddr(Op, N, Base, Index)
643 && !SelectDFormAddr(Op, N, Base, Index)) {
644 // If the address is neither A-form or D-form, punt and use an X-form
646 Base = N.getOperand(1);
647 Index = N.getOperand(0);
654 //! Convert the operand from a target-independent to a target-specific node
658 SPUDAGToDAGISel::Select(SDValue Op) {
659 SDNode *N = Op.getNode();
660 unsigned Opc = N->getOpcode();
663 MVT OpVT = Op.getValueType();
665 DebugLoc dl = N->getDebugLoc();
667 if (N->isMachineOpcode()) {
668 return NULL; // Already selected.
671 if (Opc == ISD::FrameIndex) {
672 int FI = cast<FrameIndexSDNode>(N)->getIndex();
673 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
674 SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
683 Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
684 Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(),
688 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
689 // Catch the i64 constants that end up here. Note: The backend doesn't
690 // attempt to legalize the constant (it's useless because DAGCombiner
691 // will insert 64-bit constants and we can't stop it).
692 return SelectI64Constant(Op, OpVT);
693 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
694 && OpVT == MVT::i64) {
695 SDValue Op0 = Op.getOperand(0);
696 MVT Op0VT = Op0.getValueType();
697 MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
698 MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
701 switch (Op0VT.getSimpleVT()) {
703 cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
708 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
709 CurDAG->getConstant(0x80808080, MVT::i32),
710 CurDAG->getConstant(0x00010203, MVT::i32),
711 CurDAG->getConstant(0x80808080, MVT::i32),
712 CurDAG->getConstant(0x08090a0b, MVT::i32));
716 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
717 CurDAG->getConstant(0x80808080, MVT::i32),
718 CurDAG->getConstant(0x80800203, MVT::i32),
719 CurDAG->getConstant(0x80808080, MVT::i32),
720 CurDAG->getConstant(0x80800a0b, MVT::i32));
724 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
725 CurDAG->getConstant(0x80808080, MVT::i32),
726 CurDAG->getConstant(0x80808003, MVT::i32),
727 CurDAG->getConstant(0x80808080, MVT::i32),
728 CurDAG->getConstant(0x8080800b, MVT::i32));
732 SDNode *shufMaskLoad = emitBuildVector(shufMask);
733 SDNode *PromoteScalar =
734 SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0));
736 SDValue zextShuffle =
737 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
738 SDValue(PromoteScalar, 0),
739 SDValue(PromoteScalar, 0),
740 SDValue(shufMaskLoad, 0));
742 // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
743 // re-use it in the VEC2PREFSLOT selection without needing to explicitly
744 // call SelectCode (it's already done for us.)
745 SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
746 return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
748 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
750 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl));
752 return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
753 Op.getOperand(0), Op.getOperand(1),
754 SDValue(CGLoad, 0)));
755 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
757 emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG, dl));
759 return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
760 Op.getOperand(0), Op.getOperand(1),
761 SDValue(CGLoad, 0)));
762 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
764 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG, dl));
766 return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
767 Op.getOperand(0), Op.getOperand(1),
768 SDValue(CGLoad, 0)));
769 } else if (Opc == ISD::TRUNCATE) {
770 SDValue Op0 = Op.getOperand(0);
771 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
773 && Op0.getValueType() == MVT::i64) {
774 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
776 // Take advantage of the fact that the upper 32 bits are in the
777 // i32 preferred slot and avoid shuffle gymnastics:
778 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
780 unsigned shift_amt = unsigned(CN->getZExtValue());
782 if (shift_amt >= 32) {
784 CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT,
789 // Take care of the additional shift, if present:
790 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
791 unsigned Opc = SPU::ROTMAIr32_i32;
793 if (Op0.getOpcode() == ISD::SRL)
796 hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0),
804 } else if (Opc == ISD::SHL) {
805 if (OpVT == MVT::i64) {
806 return SelectSHLi64(Op, OpVT);
808 } else if (Opc == ISD::SRL) {
809 if (OpVT == MVT::i64) {
810 return SelectSRLi64(Op, OpVT);
812 } else if (Opc == ISD::SRA) {
813 if (OpVT == MVT::i64) {
814 return SelectSRAi64(Op, OpVT);
816 } else if (Opc == SPUISD::LDRESULT) {
817 // Custom select instructions for LDRESULT
818 MVT VT = N->getValueType(0);
819 SDValue Arg = N->getOperand(0);
820 SDValue Chain = N->getOperand(1);
822 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
824 if (vtm->ldresult_ins == 0) {
825 cerr << "LDRESULT for unsupported type: "
831 Opc = vtm->ldresult_ins;
832 if (vtm->ldresult_imm) {
833 SDValue Zero = CurDAG->getTargetConstant(0, VT);
835 Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
837 Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
841 } else if (Opc == SPUISD::IndirectAddr) {
842 // Look at the operands: SelectCode() will catch the cases that aren't
843 // specifically handled here.
845 // SPUInstrInfo catches the following patterns:
846 // (SPUindirect (SPUhi ...), (SPUlo ...))
847 // (SPUindirect $sp, imm)
848 MVT VT = Op.getValueType();
849 SDValue Op0 = N->getOperand(0);
850 SDValue Op1 = N->getOperand(1);
853 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
854 || (Op0.getOpcode() == ISD::Register
855 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
856 && RN->getReg() != SPU::R1))) {
858 if (Op1.getOpcode() == ISD::Constant) {
859 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
860 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
861 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
871 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
873 return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops);
875 return SelectCode(Op);
879 * Emit the instruction sequence for i64 left shifts. The basic algorithm
880 * is to fill the bottom two word slots with zeros so that zeros are shifted
881 * in as the entire quadword is shifted left.
883 * \note This code could also be used to implement v2i64 shl.
885 * @param Op The shl operand
886 * @param OpVT Op's machine value value type (doesn't need to be passed, but
887 * makes life easier.)
888 * @return The SDNode with the entire instruction sequence
891 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
892 SDValue Op0 = Op.getOperand(0);
893 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
894 SDValue ShiftAmt = Op.getOperand(1);
895 MVT ShiftAmtVT = ShiftAmt.getValueType();
896 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
898 DebugLoc dl = Op.getDebugLoc();
900 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
901 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
902 SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
903 ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
904 CurDAG->getTargetConstant(0, OpVT));
905 VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
906 SDValue(ZeroFill, 0),
908 SDValue(SelMask, 0));
910 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
911 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
912 unsigned bits = unsigned(CN->getZExtValue()) & 7;
916 CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT,
918 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
923 CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT,
924 SDValue((Shift != 0 ? Shift : VecOp0), 0),
925 CurDAG->getTargetConstant(bits, ShiftAmtVT));
929 CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
931 CurDAG->getTargetConstant(3, ShiftAmtVT));
933 CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
935 CurDAG->getTargetConstant(7, ShiftAmtVT));
937 CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT,
938 SDValue(VecOp0, 0), SDValue(Bytes, 0));
940 CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT,
941 SDValue(Shift, 0), SDValue(Bits, 0));
944 return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
948 * Emit the instruction sequence for i64 logical right shifts.
950 * @param Op The shl operand
951 * @param OpVT Op's machine value value type (doesn't need to be passed, but
952 * makes life easier.)
953 * @return The SDNode with the entire instruction sequence
956 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
957 SDValue Op0 = Op.getOperand(0);
958 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
959 SDValue ShiftAmt = Op.getOperand(1);
960 MVT ShiftAmtVT = ShiftAmt.getValueType();
961 SDNode *VecOp0, *Shift = 0;
962 DebugLoc dl = Op.getDebugLoc();
964 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
966 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
967 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
968 unsigned bits = unsigned(CN->getZExtValue()) & 7;
972 CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT,
974 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
979 CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT,
980 SDValue((Shift != 0 ? Shift : VecOp0), 0),
981 CurDAG->getTargetConstant(bits, ShiftAmtVT));
985 CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
987 CurDAG->getTargetConstant(3, ShiftAmtVT));
989 CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
991 CurDAG->getTargetConstant(7, ShiftAmtVT));
993 // Ensure that the shift amounts are negated!
994 Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
996 CurDAG->getTargetConstant(0, ShiftAmtVT));
998 Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1000 CurDAG->getTargetConstant(0, ShiftAmtVT));
1003 CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT,
1004 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1006 CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT,
1007 SDValue(Shift, 0), SDValue(Bits, 0));
1010 return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1014 * Emit the instruction sequence for i64 arithmetic right shifts.
1016 * @param Op The shl operand
1017 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1018 * makes life easier.)
1019 * @return The SDNode with the entire instruction sequence
1022 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
1023 // Promote Op0 to vector
1024 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1025 SDValue ShiftAmt = Op.getOperand(1);
1026 MVT ShiftAmtVT = ShiftAmt.getValueType();
1027 DebugLoc dl = Op.getDebugLoc();
1030 CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0));
1032 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1034 CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1035 SDValue(VecOp0, 0), SignRotAmt);
1036 SDNode *UpperHalfSign =
1037 CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1039 SDNode *UpperHalfSignMask =
1040 CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1041 SDNode *UpperLowerMask =
1042 CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
1043 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1044 SDNode *UpperLowerSelect =
1045 CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
1046 SDValue(UpperHalfSignMask, 0),
1048 SDValue(UpperLowerMask, 0));
1052 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1053 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1054 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1059 CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT,
1060 SDValue(UpperLowerSelect, 0),
1061 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1067 CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT,
1068 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1069 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1073 CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1074 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1077 CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1078 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1080 CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT,
1081 SDValue(Shift, 0), SDValue(NegShift, 0));
1084 return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1088 Do the necessary magic necessary to load a i64 constant
1090 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) {
1091 ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
1092 // Currently there's no DL on the input, but won't hurt to pretend.
1093 DebugLoc dl = Op.getDebugLoc();
1094 MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
1096 SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue(), dl);
1098 // Here's where it gets interesting, because we have to parse out the
1099 // subtree handed back in i64vec:
1101 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1102 // The degenerate case where the upper and lower bits in the splat are
1104 SDValue Op0 = i64vec.getOperand(0);
1106 ReplaceUses(i64vec, Op0);
1107 return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1108 SDValue(emitBuildVector(Op0), 0));
1109 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1110 SDValue lhs = i64vec.getOperand(0);
1111 SDValue rhs = i64vec.getOperand(1);
1112 SDValue shufmask = i64vec.getOperand(2);
1114 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1115 ReplaceUses(lhs, lhs.getOperand(0));
1116 lhs = lhs.getOperand(0);
1119 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1121 : emitBuildVector(lhs));
1123 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1124 ReplaceUses(rhs, rhs.getOperand(0));
1125 rhs = rhs.getOperand(0);
1128 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1130 : emitBuildVector(rhs));
1132 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1133 ReplaceUses(shufmask, shufmask.getOperand(0));
1134 shufmask = shufmask.getOperand(0);
1137 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1138 ? shufmask.getNode()
1139 : emitBuildVector(shufmask));
1142 Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1143 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1144 SDValue(shufMaskNode, 0)));
1146 return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1147 SDValue(shufNode, 0));
1149 cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
1154 /// createSPUISelDag - This pass converts a legalized DAG into a
1155 /// SPU-specific DAG, ready for instruction scheduling.
1157 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1158 return new SPUDAGToDAGISel(TM);