1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant((int) CN->getValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant((int) CN->getValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant((short) CN->getValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT::ValueType vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt >= MVT::i1 && vt <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT::ValueType vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDOperand &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT::ValueType to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 int prefslot_byte; /// Byte offset of the "preferred" slot
170 unsigned insmask_ins; /// Insert mask instruction for a-form
173 const valtype_map_s valtype_map[] = {
174 { MVT::i1, 0, 3, 0 },
175 { MVT::i8, SPU::ORBIr8, 3, 0 },
176 { MVT::i16, SPU::ORHIr16, 2, 0 },
177 { MVT::i32, SPU::ORIr32, 0, 0 },
178 { MVT::i64, SPU::ORIr64, 0, 0 },
179 { MVT::f32, 0, 0, 0 },
180 { MVT::f64, 0, 0, 0 },
181 // vector types... (sigh!)
182 { MVT::v16i8, 0, 0, SPU::CBD },
183 { MVT::v8i16, 0, 0, SPU::CHD },
184 { MVT::v4i32, 0, 0, SPU::CWD },
185 { MVT::v2i64, 0, 0, 0 },
186 { MVT::v4f32, 0, 0, SPU::CWD },
187 { MVT::v2f64, 0, 0, 0 }
190 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
192 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
194 const valtype_map_s *retval = 0;
195 for (size_t i = 0; i < n_valtype_map; ++i) {
196 if (valtype_map[i].VT == VT) {
197 retval = valtype_map + i;
205 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
206 << MVT::getValueTypeString(VT)
216 //===--------------------------------------------------------------------===//
217 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
218 /// instructions for SelectionDAG operations.
220 class SPUDAGToDAGISel :
221 public SelectionDAGISel
223 SPUTargetMachine &TM;
224 SPUTargetLowering &SPUtli;
225 unsigned GlobalBaseReg;
228 SPUDAGToDAGISel(SPUTargetMachine &tm) :
229 SelectionDAGISel(*tm.getTargetLowering()),
231 SPUtli(*tm.getTargetLowering())
234 virtual bool runOnFunction(Function &Fn) {
235 // Make sure we re-emit a set of the global base reg if necessary
237 SelectionDAGISel::runOnFunction(Fn);
241 /// getI32Imm - Return a target constant with the specified value, of type
243 inline SDOperand getI32Imm(uint32_t Imm) {
244 return CurDAG->getTargetConstant(Imm, MVT::i32);
247 /// getI64Imm - Return a target constant with the specified value, of type
249 inline SDOperand getI64Imm(uint64_t Imm) {
250 return CurDAG->getTargetConstant(Imm, MVT::i64);
253 /// getSmallIPtrImm - Return a target constant of pointer type.
254 inline SDOperand getSmallIPtrImm(unsigned Imm) {
255 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
258 /// Select - Convert the specified operand from a target-independent to a
259 /// target-specific node if it hasn't already been changed.
260 SDNode *Select(SDOperand Op);
262 /// Return true if the address N is a RI7 format address [r+imm]
263 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
266 //! Returns true if the address N is an A-form (local store) address
267 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
270 //! D-form address predicate
271 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
274 //! Address predicate if N can be expressed as an indexed [r+r] operation.
275 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
278 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
279 /// inline asm expressions.
280 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
282 std::vector<SDOperand> &OutOps,
285 switch (ConstraintCode) {
286 default: return true;
288 if (!SelectDFormAddr(Op, Op, Op0, Op1)
289 && !SelectAFormAddr(Op, Op, Op0, Op1))
290 SelectXFormAddr(Op, Op, Op0, Op1);
292 case 'o': // offsetable
293 if (!SelectDFormAddr(Op, Op, Op0, Op1)
294 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
296 AddToISelQueue(Op0); // r+0.
297 Op1 = getSmallIPtrImm(0);
300 case 'v': // not offsetable
302 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
304 SelectAddrIdxOnly(Op, Op, Op0, Op1);
309 OutOps.push_back(Op0);
310 OutOps.push_back(Op1);
314 /// InstructionSelectBasicBlock - This callback is invoked by
315 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
316 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
318 virtual const char *getPassName() const {
319 return "Cell SPU DAG->DAG Pattern Instruction Selection";
322 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
323 /// this target when scheduling the DAG.
324 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
325 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
326 assert(II && "No InstrInfo?");
327 return new SPUHazardRecognizer(*II);
330 // Include the pieces autogenerated from the target description.
331 #include "SPUGenDAGISel.inc"
334 /// InstructionSelectBasicBlock - This callback is invoked by
335 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
337 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
341 // Select target instructions for the DAG.
342 DAG.setRoot(SelectRoot(DAG.getRoot()));
343 DAG.RemoveDeadNodes();
345 // Emit machine code to BB.
346 ScheduleAndEmitDAG(DAG);
350 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
352 unsigned Opc = N.getOpcode();
353 unsigned VT = N.getValueType();
354 MVT::ValueType PtrVT = SPUtli.getPointerTy();
355 ConstantSDNode *CN = 0;
358 if (Opc == ISD::ADD) {
359 SDOperand Op0 = N.getOperand(0);
360 SDOperand Op1 = N.getOperand(1);
361 if (Op1.getOpcode() == ISD::Constant ||
362 Op1.getOpcode() == ISD::TargetConstant) {
363 CN = cast<ConstantSDNode>(Op1);
364 Imm = int(CN->getValue());
366 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
371 } else if (Opc == ISD::GlobalAddress
372 || Opc == ISD::TargetGlobalAddress
373 || Opc == ISD::Register) {
374 // Plain old local store address:
375 Disp = CurDAG->getTargetConstant(0, VT);
378 } else if (Opc == SPUISD::IndirectAddr) {
379 SDOperand Op1 = N.getOperand(1);
380 if (Op1.getOpcode() == ISD::TargetConstant
381 || Op1.getOpcode() == ISD::Constant) {
382 CN = cast<ConstantSDNode>(N.getOperand(1));
383 assert(CN != 0 && "SelectIndirectAddr/SPUISD::DForm2Addr expecting constant");
384 Imm = unsigned(CN->getValue());
386 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
387 Base = N.getOperand(0);
396 \arg Op The ISD instructio operand
397 \arg N The address to be tested
398 \arg Base The base address
399 \arg Index The base address index
402 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
404 // These match the addr256k operand type:
405 MVT::ValueType OffsVT = MVT::i16;
406 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
408 switch (N.getOpcode()) {
410 case ISD::ConstantPool:
411 case ISD::GlobalAddress:
412 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
416 case ISD::TargetConstant:
417 case ISD::TargetGlobalAddress:
418 case ISD::TargetJumpTable:
419 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
420 << "A-form address.\n";
424 case SPUISD::AFormAddr:
425 // Just load from memory if there's only a single use of the location,
426 // otherwise, this will get handled below with D-form offset addresses
428 SDOperand Op0 = N.getOperand(0);
429 switch (Op0.getOpcode()) {
430 case ISD::TargetConstantPool:
431 case ISD::TargetJumpTable:
436 case ISD::TargetGlobalAddress: {
437 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
438 GlobalValue *GV = GSDN->getGlobal();
439 if (GV->getAlignment() == 16) {
454 \arg Op The ISD instruction (ignored)
455 \arg N The address to be tested
456 \arg Base Base address register/pointer
457 \arg Index Base address index
459 Examine the input address by a base register plus a signed 10-bit
460 displacement, [r+I10] (D-form address).
462 \return true if \a N is a D-form address with \a Base and \a Index set
463 to non-empty SDOperand instances.
466 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
468 unsigned Opc = N.getOpcode();
469 unsigned PtrTy = SPUtli.getPointerTy();
471 if (Opc == ISD::FrameIndex) {
472 // Stack frame index must be less than 512 (divided by 16):
473 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
474 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
475 << FI->getIndex() << "\n");
476 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
477 Base = CurDAG->getTargetConstant(0, PtrTy);
478 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
481 } else if (Opc == ISD::ADD) {
482 // Generated by getelementptr
483 const SDOperand Op0 = N.getOperand(0);
484 const SDOperand Op1 = N.getOperand(1);
486 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
487 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
488 Base = CurDAG->getTargetConstant(0, PtrTy);
491 } else if (Op1.getOpcode() == ISD::Constant
492 || Op1.getOpcode() == ISD::TargetConstant) {
493 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
494 int32_t offset = int32_t(CN->getSignExtended());
496 if (Op0.getOpcode() == ISD::FrameIndex) {
497 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
498 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
499 << " frame index = " << FI->getIndex() << "\n");
501 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
502 Base = CurDAG->getTargetConstant(offset, PtrTy);
503 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
506 } else if (offset > SPUFrameInfo::minFrameOffset()
507 && offset < SPUFrameInfo::maxFrameOffset()) {
508 Base = CurDAG->getTargetConstant(offset, PtrTy);
512 } else if (Op0.getOpcode() == ISD::Constant
513 || Op0.getOpcode() == ISD::TargetConstant) {
514 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
515 int32_t offset = int32_t(CN->getSignExtended());
517 if (Op1.getOpcode() == ISD::FrameIndex) {
518 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op1);
519 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
520 << " frame index = " << FI->getIndex() << "\n");
522 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
523 Base = CurDAG->getTargetConstant(offset, PtrTy);
524 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
527 } else if (offset > SPUFrameInfo::minFrameOffset()
528 && offset < SPUFrameInfo::maxFrameOffset()) {
529 Base = CurDAG->getTargetConstant(offset, PtrTy);
534 } else if (Opc == SPUISD::IndirectAddr) {
535 // Indirect with constant offset -> D-Form address
536 const SDOperand Op0 = N.getOperand(0);
537 const SDOperand Op1 = N.getOperand(1);
538 SDOperand Zero = CurDAG->getTargetConstant(0, N.getValueType());
540 if (Op1.getOpcode() == ISD::Constant
541 || Op1.getOpcode() == ISD::TargetConstant) {
542 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
543 int32_t offset = int32_t(CN->getSignExtended());
544 if (offset > SPUFrameInfo::minFrameOffset()
545 && offset < SPUFrameInfo::maxFrameOffset()) {
546 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
550 } else if (Op0.getOpcode() == ISD::Constant
551 || Op0.getOpcode() == ISD::TargetConstant) {
552 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
553 int32_t offset = int32_t(CN->getSignExtended());
554 if (offset > SPUFrameInfo::minFrameOffset()
555 && offset < SPUFrameInfo::maxFrameOffset()) {
556 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
560 } else if (Op0.getOpcode() == SPUISD::Hi
561 && Op1.getOpcode() == SPUISD::Lo) {
562 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
563 Base = CurDAG->getTargetConstant(0, PtrTy);
567 } else if (Opc == SPUISD::AFormAddr) {
568 Base = CurDAG->getTargetConstant(0, N.getValueType());
576 \arg Op The ISD instruction operand
577 \arg N The address operand
578 \arg Base The base pointer operand
579 \arg Index The offset/index operand
581 If the address \a N can be expressed as a [r + s10imm] address, returns false.
582 Otherwise, creates two operands, Base and Index that will become the [r+r]
586 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
588 if (SelectAFormAddr(Op, N, Base, Index)
589 || SelectDFormAddr(Op, N, Base, Index))
592 // All else fails, punt and use an X-form address:
593 Base = N.getOperand(0);
594 Index = N.getOperand(1);
598 //! Convert the operand from a target-independent to a target-specific node
602 SPUDAGToDAGISel::Select(SDOperand Op) {
604 unsigned Opc = N->getOpcode();
607 MVT::ValueType OpVT = Op.getValueType();
610 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
611 return NULL; // Already selected.
612 } else if (Opc == ISD::FrameIndex) {
613 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
614 int FI = cast<FrameIndexSDNode>(N)->getIndex();
615 MVT::ValueType PtrVT = SPUtli.getPointerTy();
616 SDOperand Zero = CurDAG->getTargetConstant(0, PtrVT);
617 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, PtrVT);
619 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
624 } else if (Opc == ISD::ZERO_EXTEND) {
625 // (zero_extend:i16 (and:i8 <arg>, <const>))
626 const SDOperand &Op1 = N->getOperand(0);
628 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
629 if (Op1.getOpcode() == ISD::AND) {
630 // Fold this into a single ANDHI. This is often seen in expansions of i1
631 // to i8, then i8 to i16 in logical/branching operations.
632 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
633 "<arg>, <const>))\n");
634 NewOpc = SPU::ANDHI1To2;
635 Ops[0] = Op1.getOperand(0);
636 Ops[1] = Op1.getOperand(1);
640 } else if (Opc == SPUISD::INSERT_MASK) {
641 SDOperand Op0 = Op.getOperand(0);
642 if (Op0.getOpcode() == SPUISD::AFormAddr) {
643 // (SPUvecinsmask (SPUaform <arg>, 0)) ->
644 // (CBD|CHD|CWD 0, arg)
645 const valtype_map_s *vtm = getValueTypeMapEntry(OpVT);
646 ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getOperand(1));
647 assert(vtm->insmask_ins != 0 && "missing insert mask instruction");
648 NewOpc = vtm->insmask_ins;
649 Ops[0] = CurDAG->getTargetConstant(CN->getValue(), Op0.getValueType());
654 } else if (Op0.getOpcode() == ISD::FrameIndex) {
655 // (SPUvecinsmask <fi>) ->
656 // (CBD|CHD|CWD 0, <fi>)
657 const valtype_map_s *vtm = getValueTypeMapEntry(OpVT);
658 NewOpc = vtm->insmask_ins;
659 Ops[0] = CurDAG->getTargetConstant(0, Op0.getValueType());
662 } else if (isHighLow(Op0)) {
663 // (SPUvecinsmask (SPUindirect (SPUhi <arg>, 0), (SPUlow <arg>, 0))) ->
664 // (CBD|CHD|CWD 0, arg)
665 const valtype_map_s *vtm = getValueTypeMapEntry(OpVT);
666 NewOpc = vtm->insmask_ins;
667 Ops[0] = CurDAG->getTargetConstant(0, Op0.getValueType());
672 } else if (Opc == SPUISD::LDRESULT) {
673 // Custom select instructions for LDRESULT
674 unsigned VT = N->getValueType(0);
675 SDOperand Arg = N->getOperand(0);
676 SDOperand Chain = N->getOperand(1);
680 if (!MVT::isFloatingPoint(VT)) {
681 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
682 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
684 if (vtm->ldresult_ins == 0) {
685 cerr << "LDRESULT for unsupported type: "
686 << MVT::getValueTypeString(VT)
690 Opc = vtm->ldresult_ins;
692 AddToISelQueue(Zero);
693 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
695 Opc = (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64);
696 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
699 Chain = SDOperand(Result, 1);
700 AddToISelQueue(Chain);
703 } else if (Opc == SPUISD::IndirectAddr) {
704 SDOperand Op0 = Op.getOperand(0);
705 if (Op0.getOpcode() == SPUISD::LDRESULT
706 || Op0.getOpcode() == SPUISD::AFormAddr) {
707 // (IndirectAddr (LDRESULT|AFormAddr, imm))
708 SDOperand Op1 = Op.getOperand(1);
709 MVT::ValueType VT = Op.getValueType();
711 DEBUG(cerr << "CellSPU: IndirectAddr("
712 << (Op0.getOpcode() == SPUISD::LDRESULT
715 << ", imm):\nOp0 = ");
716 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
717 DEBUG(cerr << "\nOp1 = ");
718 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
721 if (Op1.getOpcode() == ISD::Constant) {
722 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
723 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
736 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
738 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
740 return SelectCode(Op);
743 /// createPPCISelDag - This pass converts a legalized DAG into a
744 /// SPU-specific DAG, ready for instruction scheduling.
746 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
747 return new SPUDAGToDAGISel(TM);