1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant((int) CN->getValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant((int) CN->getValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant((short) CN->getValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT::ValueType vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt >= MVT::i1 && vt <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT::ValueType vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
153 //===------------------------------------------------------------------===//
154 //! MVT::ValueType to "useful stuff" mapping structure:
156 struct valtype_map_s {
158 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
159 int prefslot_byte; /// Byte offset of the "preferred" slot
160 unsigned brcc_eq_ins; /// br_cc equal instruction
161 unsigned brcc_neq_ins; /// br_cc not equal instruction
162 unsigned load_aform; /// A-form load instruction for this VT
163 unsigned store_aform; /// A-form store instruction for this VT
166 const valtype_map_s valtype_map[] = {
167 { MVT::i1, 0, 3, 0, 0, 0,
169 { MVT::i8, SPU::ORBIr8, 3, 0, 0, SPU::LQAr8,
171 { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ, SPU::LQAr16,
173 { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ, SPU::LQAr32,
175 { MVT::i64, SPU::ORIr64, 0, 0, 0, SPU::LQAr64,
177 { MVT::f32, 0, 0, 0, 0, SPU::LQAf32,
179 { MVT::f64, 0, 0, 0, 0, SPU::LQAf64,
181 // vector types... (sigh!)
182 { MVT::v16i8, 0, 0, 0, 0, SPU::LQAv16i8,
184 { MVT::v8i16, 0, 0, 0, 0, SPU::LQAv8i16,
186 { MVT::v4i32, 0, 0, 0, 0, SPU::LQAv4i32,
188 { MVT::v2i64, 0, 0, 0, 0, SPU::LQAv2i64,
190 { MVT::v4f32, 0, 0, 0, 0, SPU::LQAv4f32,
192 { MVT::v2f64, 0, 0, 0, 0, SPU::LQAv2f64,
196 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
198 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
200 const valtype_map_s *retval = 0;
201 for (size_t i = 0; i < n_valtype_map; ++i) {
202 if (valtype_map[i].VT == VT) {
203 retval = valtype_map + i;
211 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
212 << MVT::getValueTypeString(VT)
222 //===--------------------------------------------------------------------===//
223 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
224 /// instructions for SelectionDAG operations.
226 class SPUDAGToDAGISel :
227 public SelectionDAGISel
229 SPUTargetMachine &TM;
230 SPUTargetLowering &SPUtli;
231 unsigned GlobalBaseReg;
234 SPUDAGToDAGISel(SPUTargetMachine &tm) :
235 SelectionDAGISel(*tm.getTargetLowering()),
237 SPUtli(*tm.getTargetLowering())
240 virtual bool runOnFunction(Function &Fn) {
241 // Make sure we re-emit a set of the global base reg if necessary
243 SelectionDAGISel::runOnFunction(Fn);
247 /// getI32Imm - Return a target constant with the specified value, of type
249 inline SDOperand getI32Imm(uint32_t Imm) {
250 return CurDAG->getTargetConstant(Imm, MVT::i32);
253 /// getI64Imm - Return a target constant with the specified value, of type
255 inline SDOperand getI64Imm(uint64_t Imm) {
256 return CurDAG->getTargetConstant(Imm, MVT::i64);
259 /// getSmallIPtrImm - Return a target constant of pointer type.
260 inline SDOperand getSmallIPtrImm(unsigned Imm) {
261 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
264 /// Select - Convert the specified operand from a target-independent to a
265 /// target-specific node if it hasn't already been changed.
266 SDNode *Select(SDOperand Op);
268 /// Return true if the address N is a RI7 format address [r+imm]
269 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
272 //! Returns true if the address N is an A-form (local store) address
273 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
276 //! D-form address predicate
277 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
280 //! Address predicate if N can be expressed as an indexed [r+r] operation.
281 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
284 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
285 /// inline asm expressions.
286 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
288 std::vector<SDOperand> &OutOps,
291 switch (ConstraintCode) {
292 default: return true;
294 if (!SelectDFormAddr(Op, Op, Op0, Op1)
295 && !SelectAFormAddr(Op, Op, Op0, Op1))
296 SelectXFormAddr(Op, Op, Op0, Op1);
298 case 'o': // offsetable
299 if (!SelectDFormAddr(Op, Op, Op0, Op1)
300 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
302 AddToISelQueue(Op0); // r+0.
303 Op1 = getSmallIPtrImm(0);
306 case 'v': // not offsetable
308 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
310 SelectAddrIdxOnly(Op, Op, Op0, Op1);
315 OutOps.push_back(Op0);
316 OutOps.push_back(Op1);
320 /// InstructionSelectBasicBlock - This callback is invoked by
321 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
322 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
324 virtual const char *getPassName() const {
325 return "Cell SPU DAG->DAG Pattern Instruction Selection";
328 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
329 /// this target when scheduling the DAG.
330 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
331 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
332 assert(II && "No InstrInfo?");
333 return new SPUHazardRecognizer(*II);
336 // Include the pieces autogenerated from the target description.
337 #include "SPUGenDAGISel.inc"
340 /// InstructionSelectBasicBlock - This callback is invoked by
341 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
343 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
347 // Select target instructions for the DAG.
348 DAG.setRoot(SelectRoot(DAG.getRoot()));
349 DAG.RemoveDeadNodes();
351 // Emit machine code to BB.
352 ScheduleAndEmitDAG(DAG);
356 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
358 unsigned Opc = N.getOpcode();
359 unsigned VT = N.getValueType();
360 MVT::ValueType PtrVT = SPUtli.getPointerTy();
361 ConstantSDNode *CN = 0;
364 if (Opc == ISD::ADD) {
365 SDOperand Op0 = N.getOperand(0);
366 SDOperand Op1 = N.getOperand(1);
367 if (Op1.getOpcode() == ISD::Constant ||
368 Op1.getOpcode() == ISD::TargetConstant) {
369 CN = cast<ConstantSDNode>(Op1);
370 Imm = int(CN->getValue());
372 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
377 } else if (Opc == ISD::GlobalAddress
378 || Opc == ISD::TargetGlobalAddress
379 || Opc == ISD::Register) {
380 // Plain old local store address:
381 Disp = CurDAG->getTargetConstant(0, VT);
384 } else if (Opc == SPUISD::DFormAddr) {
385 // D-Form address: This is pretty straightforward, naturally...
386 CN = cast<ConstantSDNode>(N.getOperand(1));
387 assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
388 Imm = unsigned(CN->getValue());
390 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
391 Base = N.getOperand(0);
400 \arg Op The ISD instructio operand
401 \arg N The address to be tested
402 \arg Base The base address
403 \arg Index The base address index
406 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
408 // These match the addr256k operand type:
409 MVT::ValueType OffsVT = MVT::i16;
410 MVT::ValueType PtrVT = SPUtli.getPointerTy();
412 switch (N.getOpcode()) {
414 case ISD::ConstantPool:
415 case ISD::GlobalAddress:
416 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
420 case ISD::TargetConstant: {
421 // Loading from a constant address.
422 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
423 int Imm = (int)CN->getValue();
424 if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
425 Base = CurDAG->getTargetConstant(Imm, PtrVT);
426 // Note that this operand will be ignored by the assembly printer...
427 Index = CurDAG->getTargetConstant(0, OffsVT);
431 case ISD::TargetGlobalAddress:
432 case ISD::TargetConstantPool:
433 case SPUISD::AFormAddr: {
434 // The address is in Base. N is a dummy that will be ignored by
435 // the assembly printer.
437 Index = CurDAG->getTargetConstant(0, OffsVT);
446 \arg Op The ISD instruction (ignored)
447 \arg N The address to be tested
448 \arg Base Base address register/pointer
449 \arg Index Base address index
451 Examine the input address by a base register plus a signed 10-bit
452 displacement, [r+I10] (D-form address).
454 \return true if \a N is a D-form address with \a Base and \a Index set
455 to non-empty SDOperand instances.
458 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
460 unsigned Opc = N.getOpcode();
461 unsigned PtrTy = SPUtli.getPointerTy();
463 if (Opc == ISD::Register) {
465 Index = CurDAG->getTargetConstant(0, PtrTy);
467 } else if (Opc == ISD::FrameIndex) {
468 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
469 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
470 << FI->getIndex() << "\n");
471 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
472 Base = CurDAG->getTargetConstant(0, PtrTy);
473 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
476 } else if (Opc == ISD::ADD) {
477 // Generated by getelementptr
478 const SDOperand Op0 = N.getOperand(0); // Frame index/base
479 const SDOperand Op1 = N.getOperand(1); // Offset within base
481 if ((Op1.getOpcode() == ISD::Constant
482 || Op1.getOpcode() == ISD::TargetConstant)
483 && Op0.getOpcode() != SPUISD::XFormAddr) {
484 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
485 assert(CN != 0 && "SelectDFormAddr: Expected a constant");
487 int32_t offset = (int32_t) CN->getSignExtended();
488 unsigned Opc0 = Op0.getOpcode();
490 if (Opc0 == ISD::FrameIndex) {
491 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
492 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
493 << " frame index = " << FI->getIndex() << "\n");
495 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
496 Base = CurDAG->getTargetConstant(offset, PtrTy);
497 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
500 } else if (offset > SPUFrameInfo::minFrameOffset()
501 && offset < SPUFrameInfo::maxFrameOffset()) {
502 Base = CurDAG->getTargetConstant(offset, PtrTy);
503 if (Opc0 == ISD::GlobalAddress) {
504 // Convert global address to target global address
505 GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
506 Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
509 // Otherwise, just take operand 0
516 } else if (Opc == SPUISD::DFormAddr) {
517 // D-Form address: This is pretty straightforward,
518 // naturally... but make sure that this isn't a D-form address
519 // with a X-form address embedded within:
520 const SDOperand Op0 = N.getOperand(0); // Frame index/base
521 const SDOperand Op1 = N.getOperand(1); // Offset within base
523 if (Op0.getOpcode() == ISD::Constant
524 || Op0.getOpcode() == ISD::TargetConstant) {
525 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
526 assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
527 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
531 } else if (Opc == ISD::FrameIndex) {
532 // Stack frame index must be less than 512 (divided by 16):
533 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
534 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
535 << FI->getIndex() << "\n");
536 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
537 Base = CurDAG->getTargetConstant(0, PtrTy);
538 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
541 } else if (Opc == SPUISD::LDRESULT) {
542 // It's a load result dereference
543 Base = CurDAG->getTargetConstant(0, PtrTy);
544 Index = N.getOperand(0);
552 \arg Op The ISD instruction operand
553 \arg N The address operand
554 \arg Base The base pointer operand
555 \arg Index The offset/index operand
557 If the address \a N can be expressed as a [r + s10imm] address, returns false.
558 Otherwise, creates two operands, Base and Index that will become the [r+r]
562 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
564 if (SelectAFormAddr(Op, N, Base, Index)
565 || SelectDFormAddr(Op, N, Base, Index))
568 unsigned Opc = N.getOpcode();
570 if (Opc == ISD::ADD) {
571 SDOperand N1 = N.getOperand(0);
572 SDOperand N2 = N.getOperand(1);
573 Base = N.getOperand(0);
574 Index = N.getOperand(1);
576 } else if (Opc == SPUISD::XFormAddr) {
578 Index = N.getOperand(1);
580 } else if (Opc == SPUISD::DFormAddr) {
581 // Must be a D-form address with an X-form address embedded
583 Base = N.getOperand(0);
584 Index = N.getOperand(1);
586 } else if (N.getNumOperands() == 2) {
587 SDOperand N1 = N.getOperand(0);
588 SDOperand N2 = N.getOperand(1);
589 unsigned N1Opc = N1.getOpcode();
590 unsigned N2Opc = N2.getOpcode();
592 if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
593 && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
594 Base = N.getOperand(0);
595 Index = N.getOperand(1);
599 cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
606 cerr << "SelectXFormAddr: Unhandled operand type:\n";
616 //! Emit load for A-form addresses
620 Emit_LOAD_AFormAddr(SDOperand Op, SelectionDAG &CurDAG, SPUDAGToDAGISel &ISel)
623 MVT::ValueType OpVT = Op.getValueType();
624 SDOperand Chain = Op.getOperand(0);
625 SDOperand Ptr = Op.getOperand(1);
626 SDOperand PtrArg = Ptr.getOperand(0);
627 SDOperand PtrOffs = Ptr.getOperand(1);
628 const valtype_map_s *vtm = getValueTypeMapEntry(OpVT);
630 if (PtrOffs.getOpcode() == ISD::Constant) {
631 ConstantSDNode *CN = cast<ConstantSDNode>(PtrOffs);
632 MVT::ValueType PVT = PtrOffs.getValueType();
633 PtrOffs = CurDAG.getTargetConstant(CN->getValue(), PVT);
635 ISel.AddToISelQueue(PtrArg);
636 ISel.AddToISelQueue(PtrOffs);
637 ISel.AddToISelQueue(Chain);
638 Result = CurDAG.getTargetNode(vtm->load_aform, OpVT, MVT::Other, PtrArg, PtrOffs, Chain);
639 Chain = SDOperand(Result, 1);
643 //! Emit store for A-form addresses
647 Emit_STORE_AFormAddr(SDOperand Op, SelectionDAG &CurDAG, SPUDAGToDAGISel &ISel)
650 SDOperand Chain = Op.getOperand(0);
651 SDOperand Val = Op.getOperand(1);
652 SDOperand Ptr = Op.getOperand(2);
653 SDOperand PtrArg = Ptr.getOperand(0);
654 SDOperand PtrOffs = Ptr.getOperand(1);
655 const valtype_map_s *vtm = getValueTypeMapEntry(Val.getValueType());
657 if (PtrOffs.getOpcode() == ISD::Constant) {
658 ConstantSDNode *CN = cast<ConstantSDNode>(PtrOffs);
659 MVT::ValueType PVT = PtrOffs.getValueType();
660 PtrOffs = CurDAG.getTargetConstant(CN->getValue(), PVT);
662 ISel.AddToISelQueue(Val);
663 ISel.AddToISelQueue(PtrArg);
664 ISel.AddToISelQueue(PtrOffs);
665 ISel.AddToISelQueue(Chain);
666 SDOperand Ops[4] = { Val, PtrArg, PtrOffs, Chain };
667 Result = CurDAG.getTargetNode(vtm->store_aform, MVT::Other, Ops, 4);
668 Chain = SDOperand(Result, 1);
672 //! Convert the operand from a target-independent to a target-specific node
676 SPUDAGToDAGISel::Select(SDOperand Op) {
678 unsigned Opc = N->getOpcode();
681 MVT::ValueType OpVT = Op.getValueType();
684 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
685 return NULL; // Already selected.
686 } else if (Opc == ISD::FrameIndex) {
687 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
688 int FI = cast<FrameIndexSDNode>(N)->getIndex();
689 MVT::ValueType PtrVT = SPUtli.getPointerTy();
690 SDOperand Zero = CurDAG->getTargetConstant(0, PtrVT);
691 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, PtrVT);
693 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
698 } else if (Opc == ISD::LOAD
699 && Op.getOperand(1).getOpcode() == SPUISD::AFormAddr) {
700 return Emit_LOAD_AFormAddr(Op, *CurDAG, *this);
701 } else if (Opc == ISD::STORE
702 && Op.getOperand(2).getOpcode() == SPUISD::AFormAddr) {
703 return Emit_STORE_AFormAddr(Op, *CurDAG, *this);
704 } else if (Opc == ISD::ZERO_EXTEND) {
705 // (zero_extend:i16 (and:i8 <arg>, <const>))
706 const SDOperand &Op1 = N->getOperand(0);
708 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
709 if (Op1.getOpcode() == ISD::AND) {
710 // Fold this into a single ANDHI. This is often seen in expansions of i1
711 // to i8, then i8 to i16 in logical/branching operations.
712 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
713 "<arg>, <const>))\n");
714 NewOpc = SPU::ANDHI1To2;
715 Ops[0] = Op1.getOperand(0);
716 Ops[1] = Op1.getOperand(1);
720 } else if (Opc == SPUISD::LDRESULT) {
721 // Custom select instructions for LDRESULT
722 unsigned VT = N->getValueType(0);
723 SDOperand Arg = N->getOperand(0);
724 SDOperand Chain = N->getOperand(1);
728 if (!MVT::isFloatingPoint(VT)) {
729 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
730 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
732 if (vtm->ldresult_ins == 0) {
733 cerr << "LDRESULT for unsupported type: "
734 << MVT::getValueTypeString(VT)
738 Opc = vtm->ldresult_ins;
740 AddToISelQueue(Zero);
741 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
743 Opc = (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64);
744 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
747 Chain = SDOperand(Result, 1);
748 AddToISelQueue(Chain);
751 } else if (Opc == SPUISD::XFormAddr) {
752 SDOperand Op0 = Op.getOperand(0);
753 if (Op0.getOpcode() == SPUISD::LDRESULT
754 || Op0.getOpcode() == SPUISD::AFormAddr) {
755 // (XFormAddr (LDRESULT|AFormAddr, imm))
756 SDOperand Op1 = Op.getOperand(1);
757 MVT::ValueType VT = Op.getValueType();
759 DEBUG(cerr << "CellSPU: XFormAddr("
760 << (Op0.getOpcode() == SPUISD::LDRESULT
763 << ", imm):\nOp0 = ");
764 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
765 DEBUG(cerr << "\nOp1 = ");
766 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
769 if (Op1.getOpcode() == ISD::Constant) {
770 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
771 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
784 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
786 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
788 return SelectCode(Op);
791 /// createPPCISelDag - This pass converts a legalized DAG into a
792 /// SPU-specific DAG, ready for instruction scheduling.
794 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
795 return new SPUDAGToDAGISel(TM);