1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant((int) CN->getValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant((int) CN->getValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant((short) CN->getValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT::ValueType vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt >= MVT::i1 && vt <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT::ValueType vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
153 //===------------------------------------------------------------------===//
154 //! MVT::ValueType to "useful stuff" mapping structure:
156 struct valtype_map_s {
158 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
159 int prefslot_byte; /// Byte offset of the "preferred" slot
160 unsigned brcc_eq_ins; /// br_cc equal instruction
161 unsigned brcc_neq_ins; /// br_cc not equal instruction
164 const valtype_map_s valtype_map[] = {
165 { MVT::i1, 0, 3, 0, 0 },
166 { MVT::i8, 0, 3, 0, 0 },
167 { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
168 { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
169 { MVT::i64, SPU::ORIr64, 0, 0, 0 },
170 { MVT::f32, 0, 0, 0, 0 },
171 { MVT::f64, 0, 0, 0, 0 }
174 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
176 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
178 const valtype_map_s *retval = 0;
179 for (size_t i = 0; i < n_valtype_map; ++i) {
180 if (valtype_map[i].VT == VT) {
181 retval = valtype_map + i;
189 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
190 << MVT::getValueTypeString(VT)
200 //===--------------------------------------------------------------------===//
201 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
202 /// instructions for SelectionDAG operations.
204 class SPUDAGToDAGISel :
205 public SelectionDAGISel
207 SPUTargetMachine &TM;
208 SPUTargetLowering &SPUtli;
209 unsigned GlobalBaseReg;
212 SPUDAGToDAGISel(SPUTargetMachine &tm) :
213 SelectionDAGISel(*tm.getTargetLowering()),
215 SPUtli(*tm.getTargetLowering())
218 virtual bool runOnFunction(Function &Fn) {
219 // Make sure we re-emit a set of the global base reg if necessary
221 SelectionDAGISel::runOnFunction(Fn);
225 /// getI32Imm - Return a target constant with the specified value, of type
227 inline SDOperand getI32Imm(uint32_t Imm) {
228 return CurDAG->getTargetConstant(Imm, MVT::i32);
231 /// getI64Imm - Return a target constant with the specified value, of type
233 inline SDOperand getI64Imm(uint64_t Imm) {
234 return CurDAG->getTargetConstant(Imm, MVT::i64);
237 /// getSmallIPtrImm - Return a target constant of pointer type.
238 inline SDOperand getSmallIPtrImm(unsigned Imm) {
239 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
242 /// Select - Convert the specified operand from a target-independent to a
243 /// target-specific node if it hasn't already been changed.
244 SDNode *Select(SDOperand Op);
246 /// Return true if the address N is a RI7 format address [r+imm]
247 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
250 //! Returns true if the address N is an A-form (local store) address
251 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
254 //! D-form address predicate
255 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
258 //! Address predicate if N can be expressed as an indexed [r+r] operation.
259 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
262 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
263 /// inline asm expressions.
264 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
266 std::vector<SDOperand> &OutOps,
269 switch (ConstraintCode) {
270 default: return true;
272 if (!SelectDFormAddr(Op, Op, Op0, Op1)
273 && !SelectAFormAddr(Op, Op, Op0, Op1))
274 SelectXFormAddr(Op, Op, Op0, Op1);
276 case 'o': // offsetable
277 if (!SelectDFormAddr(Op, Op, Op0, Op1)
278 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
280 AddToISelQueue(Op0); // r+0.
281 Op1 = getSmallIPtrImm(0);
284 case 'v': // not offsetable
286 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
288 SelectAddrIdxOnly(Op, Op, Op0, Op1);
293 OutOps.push_back(Op0);
294 OutOps.push_back(Op1);
298 /// InstructionSelectBasicBlock - This callback is invoked by
299 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
300 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
302 virtual const char *getPassName() const {
303 return "Cell SPU DAG->DAG Pattern Instruction Selection";
306 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
307 /// this target when scheduling the DAG.
308 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
309 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
310 assert(II && "No InstrInfo?");
311 return new SPUHazardRecognizer(*II);
314 // Include the pieces autogenerated from the target description.
315 #include "SPUGenDAGISel.inc"
318 /// InstructionSelectBasicBlock - This callback is invoked by
319 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
321 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
325 // Select target instructions for the DAG.
326 DAG.setRoot(SelectRoot(DAG.getRoot()));
327 DAG.RemoveDeadNodes();
329 // Emit machine code to BB.
330 ScheduleAndEmitDAG(DAG);
334 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
336 unsigned Opc = N.getOpcode();
337 unsigned VT = N.getValueType();
338 MVT::ValueType PtrVT = SPUtli.getPointerTy();
339 ConstantSDNode *CN = 0;
342 if (Opc == ISD::ADD) {
343 SDOperand Op0 = N.getOperand(0);
344 SDOperand Op1 = N.getOperand(1);
345 if (Op1.getOpcode() == ISD::Constant ||
346 Op1.getOpcode() == ISD::TargetConstant) {
347 CN = cast<ConstantSDNode>(Op1);
348 Imm = int(CN->getValue());
350 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
355 } else if (Opc == ISD::GlobalAddress
356 || Opc == ISD::TargetGlobalAddress
357 || Opc == ISD::Register) {
358 // Plain old local store address:
359 Disp = CurDAG->getTargetConstant(0, VT);
362 } else if (Opc == SPUISD::DFormAddr) {
363 // D-Form address: This is pretty straightforward, naturally...
364 CN = cast<ConstantSDNode>(N.getOperand(1));
365 assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
366 Imm = unsigned(CN->getValue());
368 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
369 Base = N.getOperand(0);
378 \arg Op The ISD instructio operand
379 \arg N The address to be tested
380 \arg Base The base address
381 \arg Index The base address index
384 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
386 // These match the addr256k operand type:
387 MVT::ValueType PtrVT = SPUtli.getPointerTy();
388 MVT::ValueType OffsVT = MVT::i16;
390 switch (N.getOpcode()) {
392 case ISD::TargetConstant: {
393 // Loading from a constant address.
394 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
395 int Imm = (int)CN->getValue();
396 if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
397 Base = CurDAG->getTargetConstant(Imm, PtrVT);
398 // Note that this operand will be ignored by the assembly printer...
399 Index = CurDAG->getTargetConstant(0, OffsVT);
403 case ISD::ConstantPool:
404 case ISD::TargetConstantPool: {
405 // The constant pool address is N. Base is a dummy that will be ignored by
406 // the assembly printer.
408 Index = CurDAG->getTargetConstant(0, OffsVT);
412 case ISD::GlobalAddress:
413 case ISD::TargetGlobalAddress: {
414 // The global address is N. Base is a dummy that is ignored by the
417 Index = CurDAG->getTargetConstant(0, OffsVT);
426 \arg Op The ISD instruction (ignored)
427 \arg N The address to be tested
428 \arg Base Base address register/pointer
429 \arg Index Base address index
431 Examine the input address by a base register plus a signed 10-bit
432 displacement, [r+I10] (D-form address).
434 \return true if \a N is a D-form address with \a Base and \a Index set
435 to non-empty SDOperand instances.
438 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
440 unsigned Opc = N.getOpcode();
441 unsigned PtrTy = SPUtli.getPointerTy();
443 if (Opc == ISD::Register) {
445 Index = CurDAG->getTargetConstant(0, PtrTy);
447 } else if (Opc == ISD::FrameIndex) {
448 // Stack frame index must be less than 512 (divided by 16):
449 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
450 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
451 << FI->getIndex() << "\n");
452 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
453 Base = CurDAG->getTargetConstant(0, PtrTy);
454 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
457 } else if (Opc == ISD::ADD) {
458 // Generated by getelementptr
459 const SDOperand Op0 = N.getOperand(0); // Frame index/base
460 const SDOperand Op1 = N.getOperand(1); // Offset within base
461 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
467 int32_t offset = (int32_t) CN->getSignExtended();
468 unsigned Opc0 = Op0.getOpcode();
470 if ((offset & 0xf) != 0) {
471 cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n";
476 if (Opc0 == ISD::FrameIndex) {
477 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
478 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
479 << " frame index = " << FI->getIndex() << "\n");
481 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
482 Base = CurDAG->getTargetConstant(offset, PtrTy);
483 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
486 } else if (offset > SPUFrameInfo::minFrameOffset()
487 && offset < SPUFrameInfo::maxFrameOffset()) {
488 Base = CurDAG->getTargetConstant(offset, PtrTy);
489 if (Opc0 == ISD::GlobalAddress) {
490 // Convert global address to target global address
491 GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
492 Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
495 // Otherwise, just take operand 0
500 } else if (Opc == SPUISD::DFormAddr) {
501 // D-Form address: This is pretty straightforward, naturally...
502 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
503 assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
504 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
505 Index = N.getOperand(0);
513 \arg Op The ISD instruction operand
514 \arg N The address operand
515 \arg Base The base pointer operand
516 \arg Index The offset/index operand
518 If the address \a N can be expressed as a [r + s10imm] address, returns false.
519 Otherwise, creates two operands, Base and Index that will become the [r+r]
523 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
525 if (SelectAFormAddr(Op, N, Base, Index)
526 || SelectDFormAddr(Op, N, Base, Index))
529 unsigned Opc = N.getOpcode();
531 if (Opc == ISD::ADD) {
532 SDOperand N1 = N.getOperand(0);
533 SDOperand N2 = N.getOperand(1);
534 unsigned N1Opc = N1.getOpcode();
535 unsigned N2Opc = N2.getOpcode();
537 if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo)
538 || (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) {
539 Base = N.getOperand(0);
540 Index = N.getOperand(1);
543 cerr << "SelectXFormAddr: Unhandled ADD operands:\n";
551 } else if (N.getNumOperands() == 2) {
552 SDOperand N1 = N.getOperand(0);
553 SDOperand N2 = N.getOperand(1);
554 unsigned N1Opc = N1.getOpcode();
555 unsigned N2Opc = N2.getOpcode();
557 if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
558 && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
559 Base = N.getOperand(0);
560 Index = N.getOperand(1);
564 cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
571 cerr << "SelectXFormAddr: Unhandled operand type:\n";
581 //! Convert the operand from a target-independent to a target-specific node
585 SPUDAGToDAGISel::Select(SDOperand Op) {
587 unsigned Opc = N->getOpcode();
589 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
590 return NULL; // Already selected.
591 } else if (Opc == ISD::FrameIndex) {
592 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
593 int FI = cast<FrameIndexSDNode>(N)->getIndex();
594 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
596 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
597 return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
598 CurDAG->getTargetConstant(0, MVT::i32));
599 } else if (Opc == SPUISD::LDRESULT) {
600 // Custom select instructions for LDRESULT
601 unsigned VT = N->getValueType(0);
602 SDOperand Arg = N->getOperand(0);
603 SDOperand Chain = N->getOperand(1);
607 if (!MVT::isFloatingPoint(VT)) {
608 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
609 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
611 if (vtm->ldresult_ins == 0) {
612 cerr << "LDRESULT for unsupported type: "
613 << MVT::getValueTypeString(VT)
617 Opc = vtm->ldresult_ins;
619 AddToISelQueue(Zero);
620 Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
623 CurDAG->SelectNodeTo(N, (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64),
624 MVT::Other, Arg, Arg, Chain);
627 Chain = SDOperand(Result, 1);
628 AddToISelQueue(Chain);
633 return SelectCode(Op);
636 /// createPPCISelDag - This pass converts a legalized DAG into a
637 /// SPU-specific DAG, ready for instruction scheduling.
639 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
640 return new SPUDAGToDAGISel(TM);