1 //===-- SPUISelDAGToDAG.cpp - CellSPU -pattern matching inst selector -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation.
8 // See README.txt for details.
10 //===----------------------------------------------------------------------===//
12 // This file defines a pattern matching instruction selector for the Cell SPU,
13 // converting from a legalized dag to a SPU-target dag.
15 //===----------------------------------------------------------------------===//
18 #include "SPUTargetMachine.h"
19 #include "SPUISelLowering.h"
20 #include "SPUHazardRecognizers.h"
21 #include "SPUFrameInfo.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
43 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
45 isI64IntS10Immediate(ConstantSDNode *CN)
47 return isS10Constant(CN->getValue());
50 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
52 isI32IntS10Immediate(ConstantSDNode *CN)
54 return isS10Constant((int) CN->getValue());
58 //! SDNode predicate for sign-extended, 10-bit immediate values
60 isI32IntS10Immediate(SDNode *N)
62 return (N->getOpcode() == ISD::Constant
63 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
67 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
69 isI16IntS10Immediate(ConstantSDNode *CN)
71 return isS10Constant((short) CN->getValue());
74 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
76 isI16IntS10Immediate(SDNode *N)
78 return (N->getOpcode() == ISD::Constant
79 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
82 //! ConstantSDNode predicate for signed 16-bit values
84 \arg CN The constant SelectionDAG node holding the value
85 \arg Imm The returned 16-bit value, if returning true
87 This predicate tests the value in \a CN to see whether it can be
88 represented as a 16-bit, sign-extended quantity. Returns true if
92 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
94 MVT::ValueType vt = CN->getValueType(0);
95 Imm = (short) CN->getValue();
96 if (vt >= MVT::i1 && vt <= MVT::i16) {
98 } else if (vt == MVT::i32) {
99 int32_t i_val = (int32_t) CN->getValue();
100 short s_val = (short) i_val;
101 return i_val == s_val;
103 int64_t i_val = (int64_t) CN->getValue();
104 short s_val = (short) i_val;
105 return i_val == s_val;
111 //! SDNode predicate for signed 16-bit values.
113 isIntS16Immediate(SDNode *N, short &Imm)
115 return (N->getOpcode() == ISD::Constant
116 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
119 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
121 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
123 MVT::ValueType vt = FPN->getValueType(0);
124 if (vt == MVT::f32) {
125 const APFloat &apf = FPN->getValueAPF();
126 float fval = apf.convertToFloat();
127 int val = *((int *) &fval);
128 int sval = (int) ((val << 16) >> 16);
136 //===------------------------------------------------------------------===//
137 //! MVT::ValueType to useful stuff structure:
139 struct valtype_map_s {
141 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
142 int prefslot_byte; /// Byte offset of the "preferred" slot
143 unsigned brcc_eq_ins; /// br_cc equal instruction
144 unsigned brcc_neq_ins; /// br_cc not equal instruction
147 const valtype_map_s valtype_map[] = {
148 { MVT::i1, 0, 3, 0, 0 },
149 { MVT::i8, 0, 3, 0, 0 },
150 { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
151 { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
152 { MVT::i64, SPU::ORIr64, 0, 0, 0 },
153 { MVT::f32, SPU::ORIf32, 0, 0, 0 },
154 { MVT::f64, SPU::ORIf64, 0, 0, 0 }
157 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
159 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
161 const valtype_map_s *retval = 0;
162 for (size_t i = 0; i < n_valtype_map; ++i) {
163 if (valtype_map[i].VT == VT) {
164 retval = valtype_map + i;
172 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
173 << MVT::getValueTypeString(VT)
183 //===--------------------------------------------------------------------===//
184 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
185 /// instructions for SelectionDAG operations.
187 class SPUDAGToDAGISel :
188 public SelectionDAGISel
190 SPUTargetMachine &TM;
191 SPUTargetLowering &SPUtli;
192 unsigned GlobalBaseReg;
195 SPUDAGToDAGISel(SPUTargetMachine &tm) :
196 SelectionDAGISel(*tm.getTargetLowering()),
198 SPUtli(*tm.getTargetLowering())
201 virtual bool runOnFunction(Function &Fn) {
202 // Make sure we re-emit a set of the global base reg if necessary
204 SelectionDAGISel::runOnFunction(Fn);
208 /// getI32Imm - Return a target constant with the specified value, of type
210 inline SDOperand getI32Imm(uint32_t Imm) {
211 return CurDAG->getTargetConstant(Imm, MVT::i32);
214 /// getI64Imm - Return a target constant with the specified value, of type
216 inline SDOperand getI64Imm(uint64_t Imm) {
217 return CurDAG->getTargetConstant(Imm, MVT::i64);
220 /// getSmallIPtrImm - Return a target constant of pointer type.
221 inline SDOperand getSmallIPtrImm(unsigned Imm) {
222 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
225 /// Select - Convert the specified operand from a target-independent to a
226 /// target-specific node if it hasn't already been changed.
227 SDNode *Select(SDOperand Op);
229 /// Return true if the address N is a RI7 format address [r+imm]
230 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
233 //! Returns true if the address N is an A-form (local store) address
234 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
237 //! D-form address predicate
238 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
241 //! Address predicate if N can be expressed as an indexed [r+r] operation.
242 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
245 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
246 /// inline asm expressions.
247 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
249 std::vector<SDOperand> &OutOps,
252 switch (ConstraintCode) {
253 default: return true;
255 if (!SelectDFormAddr(Op, Op, Op0, Op1)
256 && !SelectAFormAddr(Op, Op, Op0, Op1))
257 SelectXFormAddr(Op, Op, Op0, Op1);
259 case 'o': // offsetable
260 if (!SelectDFormAddr(Op, Op, Op0, Op1)
261 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
263 AddToISelQueue(Op0); // r+0.
264 Op1 = getSmallIPtrImm(0);
267 case 'v': // not offsetable
269 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
271 SelectAddrIdxOnly(Op, Op, Op0, Op1);
276 OutOps.push_back(Op0);
277 OutOps.push_back(Op1);
281 /// InstructionSelectBasicBlock - This callback is invoked by
282 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
283 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
285 virtual const char *getPassName() const {
286 return "Cell SPU DAG->DAG Pattern Instruction Selection";
289 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
290 /// this target when scheduling the DAG.
291 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
292 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
293 assert(II && "No InstrInfo?");
294 return new SPUHazardRecognizer(*II);
297 // Include the pieces autogenerated from the target description.
298 #include "SPUGenDAGISel.inc"
301 /// InstructionSelectBasicBlock - This callback is invoked by
302 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
304 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
308 // Select target instructions for the DAG.
309 DAG.setRoot(SelectRoot(DAG.getRoot()));
310 DAG.RemoveDeadNodes();
312 // Emit machine code to BB.
313 ScheduleAndEmitDAG(DAG);
317 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
319 unsigned Opc = N.getOpcode();
320 unsigned VT = N.getValueType();
321 MVT::ValueType PtrVT = SPUtli.getPointerTy();
322 ConstantSDNode *CN = 0;
325 if (Opc == ISD::ADD) {
326 SDOperand Op0 = N.getOperand(0);
327 SDOperand Op1 = N.getOperand(1);
328 if (Op1.getOpcode() == ISD::Constant ||
329 Op1.getOpcode() == ISD::TargetConstant) {
330 CN = cast<ConstantSDNode>(Op1);
331 Imm = int(CN->getValue());
333 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
338 } else if (Opc == ISD::GlobalAddress
339 || Opc == ISD::TargetGlobalAddress
340 || Opc == ISD::Register) {
341 // Plain old local store address:
342 Disp = CurDAG->getTargetConstant(0, VT);
345 } else if (Opc == SPUISD::DFormAddr) {
346 // D-Form address: This is pretty straightforward, naturally...
347 CN = cast<ConstantSDNode>(N.getOperand(1));
348 assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
349 Imm = unsigned(CN->getValue());
351 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
352 Base = N.getOperand(0);
361 \arg Op The ISD instructio operand
362 \arg N The address to be tested
363 \arg Base The base address
364 \arg Index The base address index
367 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
369 // These match the addr256k operand type:
370 MVT::ValueType PtrVT = SPUtli.getPointerTy();
371 MVT::ValueType OffsVT = MVT::i16;
373 switch (N.getOpcode()) {
375 case ISD::TargetConstant: {
376 // Loading from a constant address.
377 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
378 int Imm = (int)CN->getValue();
379 if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
380 Base = CurDAG->getTargetConstant(Imm, PtrVT);
381 // Note that this operand will be ignored by the assembly printer...
382 Index = CurDAG->getTargetConstant(0, OffsVT);
386 case ISD::ConstantPool:
387 case ISD::TargetConstantPool: {
388 // The constant pool address is N. Base is a dummy that will be ignored by
389 // the assembly printer.
391 Index = CurDAG->getTargetConstant(0, OffsVT);
395 case ISD::GlobalAddress:
396 case ISD::TargetGlobalAddress: {
397 // The global address is N. Base is a dummy that is ignored by the
400 Index = CurDAG->getTargetConstant(0, OffsVT);
409 \arg Op The ISD instruction (ignored)
410 \arg N The address to be tested
411 \arg Base Base address register/pointer
412 \arg Index Base address index
414 Examine the input address by a base register plus a signed 10-bit
415 displacement, [r+I10] (D-form address).
417 \return true if \a N is a D-form address with \a Base and \a Index set
418 to non-empty SDOperand instances.
421 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
423 unsigned Opc = N.getOpcode();
424 unsigned PtrTy = SPUtli.getPointerTy();
426 if (Opc == ISD::Register) {
428 Index = CurDAG->getTargetConstant(0, PtrTy);
430 } else if (Opc == ISD::FrameIndex) {
431 // Stack frame index must be less than 512 (divided by 16):
432 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
433 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
434 << FI->getIndex() << "\n");
435 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
436 Base = CurDAG->getTargetConstant(0, PtrTy);
437 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
440 } else if (Opc == ISD::ADD) {
441 // Generated by getelementptr
442 const SDOperand Op0 = N.getOperand(0); // Frame index/base
443 const SDOperand Op1 = N.getOperand(1); // Offset within base
444 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
450 int32_t offset = (int32_t) CN->getSignExtended();
451 unsigned Opc0 = Op0.getOpcode();
453 if ((offset & 0xf) != 0) {
454 cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n";
459 if (Opc0 == ISD::FrameIndex) {
460 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
461 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
462 << " frame index = " << FI->getIndex() << "\n");
464 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
465 Base = CurDAG->getTargetConstant(offset, PtrTy);
466 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
469 } else if (offset > SPUFrameInfo::minFrameOffset()
470 && offset < SPUFrameInfo::maxFrameOffset()) {
471 Base = CurDAG->getTargetConstant(offset, PtrTy);
472 if (Opc0 == ISD::GlobalAddress) {
473 // Convert global address to target global address
474 GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
475 Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
478 // Otherwise, just take operand 0
483 } else if (Opc == SPUISD::DFormAddr) {
484 // D-Form address: This is pretty straightforward, naturally...
485 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
486 assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
487 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
488 Index = N.getOperand(0);
496 \arg Op The ISD instruction operand
497 \arg N The address operand
498 \arg Base The base pointer operand
499 \arg Index The offset/index operand
501 If the address \a N can be expressed as a [r + s10imm] address, returns false.
502 Otherwise, creates two operands, Base and Index that will become the [r+r]
506 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
508 if (SelectAFormAddr(Op, N, Base, Index)
509 || SelectDFormAddr(Op, N, Base, Index))
512 unsigned Opc = N.getOpcode();
514 if (Opc == ISD::ADD) {
515 SDOperand N1 = N.getOperand(0);
516 SDOperand N2 = N.getOperand(1);
517 unsigned N1Opc = N1.getOpcode();
518 unsigned N2Opc = N2.getOpcode();
520 if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo)
521 || (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) {
522 Base = N.getOperand(0);
523 Index = N.getOperand(1);
526 cerr << "SelectXFormAddr: Unhandled ADD operands:\n";
534 } else if (N.getNumOperands() == 2) {
535 SDOperand N1 = N.getOperand(0);
536 SDOperand N2 = N.getOperand(1);
537 unsigned N1Opc = N1.getOpcode();
538 unsigned N2Opc = N2.getOpcode();
540 if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
541 && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
542 Base = N.getOperand(0);
543 Index = N.getOperand(1);
547 cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
554 cerr << "SelectXFormAddr: Unhandled operand type:\n";
564 //! Convert the operand from a target-independent to a target-specific node
568 SPUDAGToDAGISel::Select(SDOperand Op) {
570 unsigned Opc = N->getOpcode();
572 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
573 return NULL; // Already selected.
574 } else if (Opc == ISD::FrameIndex) {
575 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
576 int FI = cast<FrameIndexSDNode>(N)->getIndex();
577 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
579 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
580 return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
581 CurDAG->getTargetConstant(0, MVT::i32));
582 } else if (Opc == SPUISD::LDRESULT) {
583 // Custom select instructions for LDRESULT
584 unsigned VT = N->getValueType(0);
585 SDOperand Arg = N->getOperand(0);
586 SDOperand Chain = N->getOperand(1);
587 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
589 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
591 if (vtm->ldresult_ins == 0) {
592 cerr << "LDRESULT for unsupported type: "
593 << MVT::getValueTypeString(VT)
597 Opc = vtm->ldresult_ins;
600 AddToISelQueue(Zero);
601 AddToISelQueue(Chain);
602 Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
603 Chain = SDOperand(Result, 1);
607 return SelectCode(Op);
610 /// createPPCISelDag - This pass converts a legalized DAG into a
611 /// SPU-specific DAG, ready for instruction scheduling.
613 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
614 return new SPUDAGToDAGISel(TM);