1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
38 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
40 isI64IntS10Immediate(ConstantSDNode *CN)
42 return isS10Constant(CN->getSExtValue());
45 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
47 isI32IntS10Immediate(ConstantSDNode *CN)
49 return isS10Constant(CN->getSExtValue());
53 //! SDNode predicate for sign-extended, 10-bit immediate values
55 isI32IntS10Immediate(SDNode *N)
57 return (N->getOpcode() == ISD::Constant
58 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
62 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
64 isI32IntU10Immediate(ConstantSDNode *CN)
66 return isU10Constant(CN->getSExtValue());
69 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
71 isI16IntS10Immediate(ConstantSDNode *CN)
73 return isS10Constant(CN->getSExtValue());
76 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
78 isI16IntS10Immediate(SDNode *N)
80 return (N->getOpcode() == ISD::Constant
81 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
84 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
86 isI16IntU10Immediate(ConstantSDNode *CN)
88 return isU10Constant((short) CN->getZExtValue());
91 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
93 isI16IntU10Immediate(SDNode *N)
95 return (N->getOpcode() == ISD::Constant
96 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
99 //! ConstantSDNode predicate for signed 16-bit values
101 \arg CN The constant SelectionDAG node holding the value
102 \arg Imm The returned 16-bit value, if returning true
104 This predicate tests the value in \a CN to see whether it can be
105 represented as a 16-bit, sign-extended quantity. Returns true if
109 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
111 MVT vt = CN->getValueType(0);
112 Imm = (short) CN->getZExtValue();
113 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
115 } else if (vt == MVT::i32) {
116 int32_t i_val = (int32_t) CN->getZExtValue();
117 short s_val = (short) i_val;
118 return i_val == s_val;
120 int64_t i_val = (int64_t) CN->getZExtValue();
121 short s_val = (short) i_val;
122 return i_val == s_val;
128 //! SDNode predicate for signed 16-bit values.
130 isIntS16Immediate(SDNode *N, short &Imm)
132 return (N->getOpcode() == ISD::Constant
133 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
136 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
138 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
140 MVT vt = FPN->getValueType(0);
141 if (vt == MVT::f32) {
142 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
143 int sval = (int) ((val << 16) >> 16);
152 isHighLow(const SDValue &Op)
154 return (Op.getOpcode() == SPUISD::IndirectAddr
155 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
156 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
157 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
158 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
161 //===------------------------------------------------------------------===//
162 //! MVT to "useful stuff" mapping structure:
164 struct valtype_map_s {
166 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
167 bool ldresult_imm; /// LDRESULT instruction requires immediate?
168 int prefslot_byte; /// Byte offset of the "preferred" slot
171 const valtype_map_s valtype_map[] = {
172 { MVT::i1, 0, false, 3 },
173 { MVT::i8, SPU::ORBIr8, true, 3 },
174 { MVT::i16, SPU::ORHIr16, true, 2 },
175 { MVT::i32, SPU::ORIr32, true, 0 },
176 { MVT::i64, SPU::ORr64, false, 0 },
177 { MVT::f32, SPU::ORf32, false, 0 },
178 { MVT::f64, SPU::ORf64, false, 0 },
179 // vector types... (sigh!)
180 { MVT::v16i8, 0, false, 0 },
181 { MVT::v8i16, 0, false, 0 },
182 { MVT::v4i32, 0, false, 0 },
183 { MVT::v2i64, 0, false, 0 },
184 { MVT::v4f32, 0, false, 0 },
185 { MVT::v2f64, 0, false, 0 }
188 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
190 const valtype_map_s *getValueTypeMapEntry(MVT VT)
192 const valtype_map_s *retval = 0;
193 for (size_t i = 0; i < n_valtype_map; ++i) {
194 if (valtype_map[i].VT == VT) {
195 retval = valtype_map + i;
203 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
216 //===--------------------------------------------------------------------===//
217 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
218 /// instructions for SelectionDAG operations.
220 class SPUDAGToDAGISel :
221 public SelectionDAGISel
223 SPUTargetMachine &TM;
224 SPUTargetLowering &SPUtli;
225 unsigned GlobalBaseReg;
228 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
229 SelectionDAGISel(*tm.getTargetLowering()),
231 SPUtli(*tm.getTargetLowering())
234 virtual bool runOnFunction(Function &Fn) {
235 // Make sure we re-emit a set of the global base reg if necessary
237 SelectionDAGISel::runOnFunction(Fn);
241 /// getI32Imm - Return a target constant with the specified value, of type
243 inline SDValue getI32Imm(uint32_t Imm) {
244 return CurDAG->getTargetConstant(Imm, MVT::i32);
247 /// getI64Imm - Return a target constant with the specified value, of type
249 inline SDValue getI64Imm(uint64_t Imm) {
250 return CurDAG->getTargetConstant(Imm, MVT::i64);
253 /// getSmallIPtrImm - Return a target constant of pointer type.
254 inline SDValue getSmallIPtrImm(unsigned Imm) {
255 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
258 /// Select - Convert the specified operand from a target-independent to a
259 /// target-specific node if it hasn't already been changed.
260 SDNode *Select(SDValue Op);
262 //! Returns true if the address N is an A-form (local store) address
263 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
266 //! D-form address predicate
267 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
270 /// Alternate D-form address using i7 offset predicate
271 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
274 /// D-form address selection workhorse
275 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
276 SDValue &Base, int minOffset, int maxOffset);
278 //! Address predicate if N can be expressed as an indexed [r+r] operation.
279 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
282 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
283 /// inline asm expressions.
284 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
286 std::vector<SDValue> &OutOps) {
288 switch (ConstraintCode) {
289 default: return true;
291 if (!SelectDFormAddr(Op, Op, Op0, Op1)
292 && !SelectAFormAddr(Op, Op, Op0, Op1))
293 SelectXFormAddr(Op, Op, Op0, Op1);
295 case 'o': // offsetable
296 if (!SelectDFormAddr(Op, Op, Op0, Op1)
297 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
299 AddToISelQueue(Op0); // r+0.
300 Op1 = getSmallIPtrImm(0);
303 case 'v': // not offsetable
305 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
307 SelectAddrIdxOnly(Op, Op, Op0, Op1);
312 OutOps.push_back(Op0);
313 OutOps.push_back(Op1);
317 /// InstructionSelect - This callback is invoked by
318 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
319 virtual void InstructionSelect();
321 virtual const char *getPassName() const {
322 return "Cell SPU DAG->DAG Pattern Instruction Selection";
325 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
326 /// this target when scheduling the DAG.
327 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
328 const TargetInstrInfo *II = TM.getInstrInfo();
329 assert(II && "No InstrInfo?");
330 return new SPUHazardRecognizer(*II);
333 // Include the pieces autogenerated from the target description.
334 #include "SPUGenDAGISel.inc"
339 /// InstructionSelect - This callback is invoked by
340 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
342 SPUDAGToDAGISel::InstructionSelect()
346 // Select target instructions for the DAG.
348 CurDAG->RemoveDeadNodes();
352 \arg Op The ISD instructio operand
353 \arg N The address to be tested
354 \arg Base The base address
355 \arg Index The base address index
358 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
360 // These match the addr256k operand type:
361 MVT OffsVT = MVT::i16;
362 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
364 switch (N.getOpcode()) {
366 case ISD::ConstantPool:
367 case ISD::GlobalAddress:
368 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
372 case ISD::TargetConstant:
373 case ISD::TargetGlobalAddress:
374 case ISD::TargetJumpTable:
375 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
376 << "A-form address.\n";
380 case SPUISD::AFormAddr:
381 // Just load from memory if there's only a single use of the location,
382 // otherwise, this will get handled below with D-form offset addresses
384 SDValue Op0 = N.getOperand(0);
385 switch (Op0.getOpcode()) {
386 case ISD::TargetConstantPool:
387 case ISD::TargetJumpTable:
392 case ISD::TargetGlobalAddress: {
393 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
394 GlobalValue *GV = GSDN->getGlobal();
395 if (GV->getAlignment() == 16) {
410 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
412 const int minDForm2Offset = -(1 << 7);
413 const int maxDForm2Offset = (1 << 7) - 1;
414 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
419 \arg Op The ISD instruction (ignored)
420 \arg N The address to be tested
421 \arg Base Base address register/pointer
422 \arg Index Base address index
424 Examine the input address by a base register plus a signed 10-bit
425 displacement, [r+I10] (D-form address).
427 \return true if \a N is a D-form address with \a Base and \a Index set
428 to non-empty SDValue instances.
431 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
433 return DFormAddressPredicate(Op, N, Base, Index,
434 SPUFrameInfo::minFrameOffset(),
435 SPUFrameInfo::maxFrameOffset());
439 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
440 SDValue &Index, int minOffset,
442 unsigned Opc = N.getOpcode();
443 MVT PtrTy = SPUtli.getPointerTy();
445 if (Opc == ISD::FrameIndex) {
446 // Stack frame index must be less than 512 (divided by 16):
447 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
448 int FI = int(FIN->getIndex());
449 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
451 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
452 Base = CurDAG->getTargetConstant(0, PtrTy);
453 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
456 } else if (Opc == ISD::ADD) {
457 // Generated by getelementptr
458 const SDValue Op0 = N.getOperand(0);
459 const SDValue Op1 = N.getOperand(1);
461 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
462 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
463 Base = CurDAG->getTargetConstant(0, PtrTy);
466 } else if (Op1.getOpcode() == ISD::Constant
467 || Op1.getOpcode() == ISD::TargetConstant) {
468 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
469 int32_t offset = int32_t(CN->getSExtValue());
471 if (Op0.getOpcode() == ISD::FrameIndex) {
472 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
473 int FI = int(FIN->getIndex());
474 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
475 << " frame index = " << FI << "\n");
477 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
478 Base = CurDAG->getTargetConstant(offset, PtrTy);
479 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
482 } else if (offset > minOffset && offset < maxOffset) {
483 Base = CurDAG->getTargetConstant(offset, PtrTy);
487 } else if (Op0.getOpcode() == ISD::Constant
488 || Op0.getOpcode() == ISD::TargetConstant) {
489 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
490 int32_t offset = int32_t(CN->getSExtValue());
492 if (Op1.getOpcode() == ISD::FrameIndex) {
493 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
494 int FI = int(FIN->getIndex());
495 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
496 << " frame index = " << FI << "\n");
498 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
499 Base = CurDAG->getTargetConstant(offset, PtrTy);
500 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
503 } else if (offset > minOffset && offset < maxOffset) {
504 Base = CurDAG->getTargetConstant(offset, PtrTy);
509 } else if (Opc == SPUISD::IndirectAddr) {
510 // Indirect with constant offset -> D-Form address
511 const SDValue Op0 = N.getOperand(0);
512 const SDValue Op1 = N.getOperand(1);
514 if (Op0.getOpcode() == SPUISD::Hi
515 && Op1.getOpcode() == SPUISD::Lo) {
516 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
517 Base = CurDAG->getTargetConstant(0, PtrTy);
520 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
524 if (isa<ConstantSDNode>(Op1)) {
525 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
526 offset = int32_t(CN->getSExtValue());
528 } else if (isa<ConstantSDNode>(Op0)) {
529 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
530 offset = int32_t(CN->getSExtValue());
534 if (offset >= minOffset && offset <= maxOffset) {
535 Base = CurDAG->getTargetConstant(offset, PtrTy);
540 } else if (Opc == SPUISD::AFormAddr) {
541 Base = CurDAG->getTargetConstant(0, N.getValueType());
544 } else if (Opc == SPUISD::LDRESULT) {
545 Base = CurDAG->getTargetConstant(0, N.getValueType());
553 \arg Op The ISD instruction operand
554 \arg N The address operand
555 \arg Base The base pointer operand
556 \arg Index The offset/index operand
558 If the address \a N can be expressed as a [r + s10imm] address, returns false.
559 Otherwise, creates two operands, Base and Index that will become the [r+r]
563 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
565 if (SelectAFormAddr(Op, N, Base, Index)
566 || SelectDFormAddr(Op, N, Base, Index))
569 // All else fails, punt and use an X-form address:
570 Base = N.getOperand(0);
571 Index = N.getOperand(1);
575 //! Convert the operand from a target-independent to a target-specific node
579 SPUDAGToDAGISel::Select(SDValue Op) {
580 SDNode *N = Op.getNode();
581 unsigned Opc = N->getOpcode();
584 MVT OpVT = Op.getValueType();
587 if (N->isMachineOpcode()) {
588 return NULL; // Already selected.
589 } else if (Opc == ISD::FrameIndex) {
590 // Selects to (add $sp, FI * stackSlotSize)
592 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
593 MVT PtrVT = SPUtli.getPointerTy();
595 // Adjust stack slot to actual offset in frame:
596 if (isS10Constant(FI)) {
597 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
601 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
602 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
605 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
609 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
610 Ops[1] = CurDAG->getConstant(FI, PtrVT);
613 AddToISelQueue(Ops[1]);
615 } else if (Opc == ISD::ZERO_EXTEND) {
616 // (zero_extend:i16 (and:i8 <arg>, <const>))
617 const SDValue &Op1 = N->getOperand(0);
619 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
620 if (Op1.getOpcode() == ISD::AND) {
621 // Fold this into a single ANDHI. This is often seen in expansions of i1
622 // to i8, then i8 to i16 in logical/branching operations.
623 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
624 "<arg>, <const>))\n");
625 NewOpc = SPU::ANDHIi8i16;
626 Ops[0] = Op1.getOperand(0);
627 Ops[1] = Op1.getOperand(1);
631 } else if (Opc == SPUISD::LDRESULT) {
632 // Custom select instructions for LDRESULT
633 MVT VT = N->getValueType(0);
634 SDValue Arg = N->getOperand(0);
635 SDValue Chain = N->getOperand(1);
637 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
639 if (vtm->ldresult_ins == 0) {
640 cerr << "LDRESULT for unsupported type: "
647 Opc = vtm->ldresult_ins;
648 if (vtm->ldresult_imm) {
649 SDValue Zero = CurDAG->getTargetConstant(0, VT);
651 AddToISelQueue(Zero);
652 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
654 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
657 Chain = SDValue(Result, 1);
658 AddToISelQueue(Chain);
661 } else if (Opc == SPUISD::IndirectAddr) {
662 SDValue Op0 = Op.getOperand(0);
663 if (Op0.getOpcode() == SPUISD::LDRESULT) {
664 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
665 // (IndirectAddr (LDRESULT, imm))
666 SDValue Op1 = Op.getOperand(1);
667 MVT VT = Op.getValueType();
669 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
670 DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
671 DEBUG(cerr << "\nOp1 = ");
672 DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
675 if (Op1.getOpcode() == ISD::Constant) {
676 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
677 Op1 = CurDAG->getTargetConstant(CN->getZExtValue(), VT);
678 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
690 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
692 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
694 return SelectCode(Op);
697 /// createPPCISelDag - This pass converts a legalized DAG into a
698 /// SPU-specific DAG, ready for instruction scheduling.
700 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
701 return new SPUDAGToDAGISel(TM);