1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "SPUFrameLowering.h"
19 #include "SPUTargetMachine.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/raw_ostream.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI32IntS10Immediate(ConstantSDNode *CN)
44 return isInt<10>(CN->getSExtValue());
47 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
49 isI32IntU10Immediate(ConstantSDNode *CN)
51 return isUInt<10>(CN->getSExtValue());
54 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
56 isI16IntS10Immediate(ConstantSDNode *CN)
58 return isInt<10>(CN->getSExtValue());
61 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
63 isI16IntU10Immediate(ConstantSDNode *CN)
65 return isUInt<10>((short) CN->getZExtValue());
68 //! ConstantSDNode predicate for signed 16-bit values
70 \arg CN The constant SelectionDAG node holding the value
71 \arg Imm The returned 16-bit value, if returning true
73 This predicate tests the value in \a CN to see whether it can be
74 represented as a 16-bit, sign-extended quantity. Returns true if
78 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
80 EVT vt = CN->getValueType(0);
81 Imm = (short) CN->getZExtValue();
82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
84 } else if (vt == MVT::i32) {
85 int32_t i_val = (int32_t) CN->getZExtValue();
86 short s_val = (short) i_val;
87 return i_val == s_val;
89 int64_t i_val = (int64_t) CN->getZExtValue();
90 short s_val = (short) i_val;
91 return i_val == s_val;
97 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
99 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
101 EVT vt = FPN->getValueType(0);
102 if (vt == MVT::f32) {
103 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
104 int sval = (int) ((val << 16) >> 16);
112 //! Generate the carry-generate shuffle mask.
113 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
114 SmallVector<SDValue, 16 > ShufBytes;
116 // Create the shuffle mask for "rotating" the borrow up one register slot
117 // once the borrow is generated.
118 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
119 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
120 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
121 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
123 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
124 &ShufBytes[0], ShufBytes.size());
127 //! Generate the borrow-generate shuffle mask
128 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
129 SmallVector<SDValue, 16 > ShufBytes;
131 // Create the shuffle mask for "rotating" the borrow up one register slot
132 // once the borrow is generated.
133 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
134 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
135 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
136 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
138 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
139 &ShufBytes[0], ShufBytes.size());
142 //===------------------------------------------------------------------===//
143 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
144 /// instructions for SelectionDAG operations.
146 class SPUDAGToDAGISel :
147 public SelectionDAGISel
149 const SPUTargetMachine &TM;
150 const SPUTargetLowering &SPUtli;
151 unsigned GlobalBaseReg;
154 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
155 SelectionDAGISel(tm),
157 SPUtli(*tm.getTargetLowering())
160 virtual bool runOnMachineFunction(MachineFunction &MF) {
161 // Make sure we re-emit a set of the global base reg if necessary
163 SelectionDAGISel::runOnMachineFunction(MF);
167 /// getI32Imm - Return a target constant with the specified value, of type
169 inline SDValue getI32Imm(uint32_t Imm) {
170 return CurDAG->getTargetConstant(Imm, MVT::i32);
173 /// getSmallIPtrImm - Return a target constant of pointer type.
174 inline SDValue getSmallIPtrImm(unsigned Imm) {
175 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
178 SDNode *emitBuildVector(SDNode *bvNode) {
179 EVT vecVT = bvNode->getValueType(0);
180 DebugLoc dl = bvNode->getDebugLoc();
182 // Check to see if this vector can be represented as a CellSPU immediate
183 // constant by invoking all of the instruction selection predicates:
184 if (((vecVT == MVT::v8i16) &&
185 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
186 ((vecVT == MVT::v4i32) &&
187 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
188 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
189 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
191 ((vecVT == MVT::v2i64) &&
192 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
193 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
194 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
195 HandleSDNode Dummy(SDValue(bvNode, 0));
196 if (SDNode *N = Select(bvNode))
198 return Dummy.getValue().getNode();
201 // No, need to emit a constant pool spill:
202 std::vector<Constant*> CV;
204 for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
205 ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
206 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
209 const Constant *CP = ConstantVector::get(CV);
210 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
211 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
212 SDValue CGPoolOffset =
213 SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
215 HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
216 CurDAG->getEntryNode(), CGPoolOffset,
217 MachinePointerInfo::getConstantPool(),
218 false, false, false, Alignment));
219 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
220 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
222 return Dummy.getValue().getNode();
225 /// Select - Convert the specified operand from a target-independent to a
226 /// target-specific node if it hasn't already been changed.
227 SDNode *Select(SDNode *N);
229 //! Emit the instruction sequence for i64 shl
230 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
232 //! Emit the instruction sequence for i64 srl
233 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
235 //! Emit the instruction sequence for i64 sra
236 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
238 //! Emit the necessary sequence for loading i64 constants:
239 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
241 //! Alternate instruction emit sequence for loading i64 constants
242 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
244 //! Returns true if the address N is an A-form (local store) address
245 bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
248 //! D-form address predicate
249 bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
252 /// Alternate D-form address using i7 offset predicate
253 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
256 /// D-form address selection workhorse
257 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
258 SDValue &Base, int minOffset, int maxOffset);
260 //! Address predicate if N can be expressed as an indexed [r+r] operation.
261 bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
264 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
265 /// inline asm expressions.
266 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
268 std::vector<SDValue> &OutOps) {
270 switch (ConstraintCode) {
271 default: return true;
273 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
274 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
275 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
277 case 'o': // offsetable
278 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
279 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
281 Op1 = getSmallIPtrImm(0);
284 case 'v': // not offsetable
286 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
288 SelectAddrIdxOnly(Op, Op, Op0, Op1);
293 OutOps.push_back(Op0);
294 OutOps.push_back(Op1);
298 virtual const char *getPassName() const {
299 return "Cell SPU DAG->DAG Pattern Instruction Selection";
303 SDValue getRC( MVT );
305 // Include the pieces autogenerated from the target description.
306 #include "SPUGenDAGISel.inc"
311 \arg Op The ISD instruction operand
312 \arg N The address to be tested
313 \arg Base The base address
314 \arg Index The base address index
317 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
319 // These match the addr256k operand type:
320 EVT OffsVT = MVT::i16;
321 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
324 switch (N.getOpcode()) {
326 val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
327 Base = CurDAG->getTargetConstant( val , MVT::i32);
330 case ISD::ConstantPool:
331 case ISD::GlobalAddress:
332 report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
335 case ISD::TargetConstant:
336 case ISD::TargetGlobalAddress:
337 case ISD::TargetJumpTable:
338 report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
339 "not wrapped as A-form address.");
342 case SPUISD::AFormAddr:
343 // Just load from memory if there's only a single use of the location,
344 // otherwise, this will get handled below with D-form offset addresses
346 SDValue Op0 = N.getOperand(0);
347 switch (Op0.getOpcode()) {
348 case ISD::TargetConstantPool:
349 case ISD::TargetJumpTable:
354 case ISD::TargetGlobalAddress: {
355 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
356 const GlobalValue *GV = GSDN->getGlobal();
357 if (GV->getAlignment() == 16) {
372 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
374 const int minDForm2Offset = -(1 << 7);
375 const int maxDForm2Offset = (1 << 7) - 1;
376 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
381 \arg Op The ISD instruction (ignored)
382 \arg N The address to be tested
383 \arg Base Base address register/pointer
384 \arg Index Base address index
386 Examine the input address by a base register plus a signed 10-bit
387 displacement, [r+I10] (D-form address).
389 \return true if \a N is a D-form address with \a Base and \a Index set
390 to non-empty SDValue instances.
393 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
395 return DFormAddressPredicate(Op, N, Base, Index,
396 SPUFrameLowering::minFrameOffset(),
397 SPUFrameLowering::maxFrameOffset());
401 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
402 SDValue &Index, int minOffset,
404 unsigned Opc = N.getOpcode();
405 EVT PtrTy = SPUtli.getPointerTy();
407 if (Opc == ISD::FrameIndex) {
408 // Stack frame index must be less than 512 (divided by 16):
409 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
410 int FI = int(FIN->getIndex());
411 DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
413 if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
414 Base = CurDAG->getTargetConstant(0, PtrTy);
415 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
418 } else if (Opc == ISD::ADD) {
419 // Generated by getelementptr
420 const SDValue Op0 = N.getOperand(0);
421 const SDValue Op1 = N.getOperand(1);
423 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
424 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
425 Base = CurDAG->getTargetConstant(0, PtrTy);
428 } else if (Op1.getOpcode() == ISD::Constant
429 || Op1.getOpcode() == ISD::TargetConstant) {
430 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
431 int32_t offset = int32_t(CN->getSExtValue());
433 if (Op0.getOpcode() == ISD::FrameIndex) {
434 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
435 int FI = int(FIN->getIndex());
436 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
437 << " frame index = " << FI << "\n");
439 if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
440 Base = CurDAG->getTargetConstant(offset, PtrTy);
441 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
444 } else if (offset > minOffset && offset < maxOffset) {
445 Base = CurDAG->getTargetConstant(offset, PtrTy);
449 } else if (Op0.getOpcode() == ISD::Constant
450 || Op0.getOpcode() == ISD::TargetConstant) {
451 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
452 int32_t offset = int32_t(CN->getSExtValue());
454 if (Op1.getOpcode() == ISD::FrameIndex) {
455 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
456 int FI = int(FIN->getIndex());
457 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
458 << " frame index = " << FI << "\n");
460 if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
461 Base = CurDAG->getTargetConstant(offset, PtrTy);
462 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
465 } else if (offset > minOffset && offset < maxOffset) {
466 Base = CurDAG->getTargetConstant(offset, PtrTy);
471 } else if (Opc == SPUISD::IndirectAddr) {
472 // Indirect with constant offset -> D-Form address
473 const SDValue Op0 = N.getOperand(0);
474 const SDValue Op1 = N.getOperand(1);
476 if (Op0.getOpcode() == SPUISD::Hi
477 && Op1.getOpcode() == SPUISD::Lo) {
478 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
479 Base = CurDAG->getTargetConstant(0, PtrTy);
482 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
486 if (isa<ConstantSDNode>(Op1)) {
487 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
488 offset = int32_t(CN->getSExtValue());
490 } else if (isa<ConstantSDNode>(Op0)) {
491 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
492 offset = int32_t(CN->getSExtValue());
496 if (offset >= minOffset && offset <= maxOffset) {
497 Base = CurDAG->getTargetConstant(offset, PtrTy);
502 } else if (Opc == SPUISD::AFormAddr) {
503 Base = CurDAG->getTargetConstant(0, N.getValueType());
506 } else if (Opc == SPUISD::LDRESULT) {
507 Base = CurDAG->getTargetConstant(0, N.getValueType());
510 } else if (Opc == ISD::Register
511 ||Opc == ISD::CopyFromReg
513 ||Opc == ISD::Constant) {
514 unsigned OpOpc = Op->getOpcode();
516 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
517 // Direct load/store without getelementptr
520 Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
522 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
523 if (Offs.getOpcode() == ISD::UNDEF)
524 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
531 /* If otherwise unadorned, default to D-form address with 0 offset: */
532 if (Opc == ISD::CopyFromReg) {
533 Index = N.getOperand(1);
538 Base = CurDAG->getTargetConstant(0, Index.getValueType());
547 \arg Op The ISD instruction operand
548 \arg N The address operand
549 \arg Base The base pointer operand
550 \arg Index The offset/index operand
552 If the address \a N can be expressed as an A-form or D-form address, returns
553 false. Otherwise, creates two operands, Base and Index that will become the
554 (r)(r) X-form address.
557 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
559 if (!SelectAFormAddr(Op, N, Base, Index)
560 && !SelectDFormAddr(Op, N, Base, Index)) {
561 // If the address is neither A-form or D-form, punt and use an X-form
563 Base = N.getOperand(1);
564 Index = N.getOperand(0);
572 Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue
573 to be used as the last parameter of a
574 CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call
575 \arg VT the value type for which we want a register class
577 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
578 switch( VT.SimpleTy ) {
580 return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
583 return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
586 return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
589 return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
592 return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
595 return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
603 return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
606 assert( false && "add a new case here" );
611 //! Convert the operand from a target-independent to a target-specific node
615 SPUDAGToDAGISel::Select(SDNode *N) {
616 unsigned Opc = N->getOpcode();
619 EVT OpVT = N->getValueType(0);
621 DebugLoc dl = N->getDebugLoc();
623 if (N->isMachineOpcode())
624 return NULL; // Already selected.
626 if (Opc == ISD::FrameIndex) {
627 int FI = cast<FrameIndexSDNode>(N)->getIndex();
628 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
629 SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
638 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
639 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
640 N->getValueType(0), TFI),
644 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
645 // Catch the i64 constants that end up here. Note: The backend doesn't
646 // attempt to legalize the constant (it's useless because DAGCombiner
647 // will insert 64-bit constants and we can't stop it).
648 return SelectI64Constant(N, OpVT, N->getDebugLoc());
649 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
650 && OpVT == MVT::i64) {
651 SDValue Op0 = N->getOperand(0);
652 EVT Op0VT = Op0.getValueType();
653 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
654 Op0VT, (128 / Op0VT.getSizeInBits()));
655 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
656 OpVT, (128 / OpVT.getSizeInBits()));
659 switch (Op0VT.getSimpleVT().SimpleTy) {
661 report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
664 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
665 CurDAG->getConstant(0x80808080, MVT::i32),
666 CurDAG->getConstant(0x00010203, MVT::i32),
667 CurDAG->getConstant(0x80808080, MVT::i32),
668 CurDAG->getConstant(0x08090a0b, MVT::i32));
672 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
673 CurDAG->getConstant(0x80808080, MVT::i32),
674 CurDAG->getConstant(0x80800203, MVT::i32),
675 CurDAG->getConstant(0x80808080, MVT::i32),
676 CurDAG->getConstant(0x80800a0b, MVT::i32));
680 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
681 CurDAG->getConstant(0x80808080, MVT::i32),
682 CurDAG->getConstant(0x80808003, MVT::i32),
683 CurDAG->getConstant(0x80808080, MVT::i32),
684 CurDAG->getConstant(0x8080800b, MVT::i32));
688 SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
690 HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
694 if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
695 PromScalar = SDValue(N, 0);
697 PromScalar = PromoteScalar.getValue();
699 SDValue zextShuffle =
700 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
701 PromScalar, PromScalar,
702 SDValue(shufMaskLoad, 0));
704 HandleSDNode Dummy2(zextShuffle);
705 if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
706 zextShuffle = SDValue(N, 0);
708 zextShuffle = Dummy2.getValue();
709 HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
712 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
713 SelectCode(Dummy.getValue().getNode());
714 return Dummy.getValue().getNode();
715 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
717 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
719 HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
720 N->getOperand(0), N->getOperand(1),
721 SDValue(CGLoad, 0)));
723 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
724 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
726 return Dummy.getValue().getNode();
727 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
729 emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
731 HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
732 N->getOperand(0), N->getOperand(1),
733 SDValue(CGLoad, 0)));
735 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
736 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
738 return Dummy.getValue().getNode();
739 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
741 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
743 HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
744 N->getOperand(0), N->getOperand(1),
745 SDValue(CGLoad, 0)));
746 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
747 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
749 return Dummy.getValue().getNode();
750 } else if (Opc == ISD::TRUNCATE) {
751 SDValue Op0 = N->getOperand(0);
752 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
754 && Op0.getValueType() == MVT::i64) {
755 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
757 // Take advantage of the fact that the upper 32 bits are in the
758 // i32 preferred slot and avoid shuffle gymnastics:
759 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
761 unsigned shift_amt = unsigned(CN->getZExtValue());
763 if (shift_amt >= 32) {
765 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
766 Op0.getOperand(0), getRC(MVT::i32));
770 // Take care of the additional shift, if present:
771 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
772 unsigned Opc = SPU::ROTMAIr32_i32;
774 if (Op0.getOpcode() == ISD::SRL)
777 hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
785 } else if (Opc == ISD::SHL) {
786 if (OpVT == MVT::i64)
787 return SelectSHLi64(N, OpVT);
788 } else if (Opc == ISD::SRL) {
789 if (OpVT == MVT::i64)
790 return SelectSRLi64(N, OpVT);
791 } else if (Opc == ISD::SRA) {
792 if (OpVT == MVT::i64)
793 return SelectSRAi64(N, OpVT);
794 } else if (Opc == ISD::FNEG
795 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
796 DebugLoc dl = N->getDebugLoc();
797 // Check if the pattern is a special form of DFNMS:
798 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
799 SDValue Op0 = N->getOperand(0);
800 if (Op0.getOpcode() == ISD::FSUB) {
801 SDValue Op00 = Op0.getOperand(0);
802 if (Op00.getOpcode() == ISD::FMUL) {
803 unsigned Opc = SPU::DFNMSf64;
804 if (OpVT == MVT::v2f64)
805 Opc = SPU::DFNMSv2f64;
807 return CurDAG->getMachineNode(Opc, dl, OpVT,
814 SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
815 SDNode *signMask = 0;
816 unsigned Opc = SPU::XORfneg64;
818 if (OpVT == MVT::f64) {
819 signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
820 } else if (OpVT == MVT::v2f64) {
821 Opc = SPU::XORfnegvec;
822 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
824 negConst, negConst).getNode());
827 return CurDAG->getMachineNode(Opc, dl, OpVT,
828 N->getOperand(0), SDValue(signMask, 0));
829 } else if (Opc == ISD::FABS) {
830 if (OpVT == MVT::f64) {
831 SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
832 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
833 N->getOperand(0), SDValue(signMask, 0));
834 } else if (OpVT == MVT::v2f64) {
835 SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
836 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
838 SDNode *signMask = emitBuildVector(absVec.getNode());
839 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
840 N->getOperand(0), SDValue(signMask, 0));
842 } else if (Opc == SPUISD::LDRESULT) {
843 // Custom select instructions for LDRESULT
844 EVT VT = N->getValueType(0);
845 SDValue Arg = N->getOperand(0);
846 SDValue Chain = N->getOperand(1);
849 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
851 getRC( VT.getSimpleVT()), Chain);
854 } else if (Opc == SPUISD::IndirectAddr) {
855 // Look at the operands: SelectCode() will catch the cases that aren't
856 // specifically handled here.
858 // SPUInstrInfo catches the following patterns:
859 // (SPUindirect (SPUhi ...), (SPUlo ...))
860 // (SPUindirect $sp, imm)
861 EVT VT = N->getValueType(0);
862 SDValue Op0 = N->getOperand(0);
863 SDValue Op1 = N->getOperand(1);
866 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
867 || (Op0.getOpcode() == ISD::Register
868 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
869 && RN->getReg() != SPU::R1))) {
872 if (Op1.getOpcode() == ISD::Constant) {
873 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
874 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
875 if (isInt<10>(CN->getSExtValue())) {
879 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
892 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
894 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
896 return SelectCode(N);
900 * Emit the instruction sequence for i64 left shifts. The basic algorithm
901 * is to fill the bottom two word slots with zeros so that zeros are shifted
902 * in as the entire quadword is shifted left.
904 * \note This code could also be used to implement v2i64 shl.
906 * @param Op The shl operand
907 * @param OpVT Op's machine value value type (doesn't need to be passed, but
908 * makes life easier.)
909 * @return The SDNode with the entire instruction sequence
912 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
913 SDValue Op0 = N->getOperand(0);
914 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
915 OpVT, (128 / OpVT.getSizeInBits()));
916 SDValue ShiftAmt = N->getOperand(1);
917 EVT ShiftAmtVT = ShiftAmt.getValueType();
918 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
920 DebugLoc dl = N->getDebugLoc();
922 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
923 Op0, getRC(MVT::v2i64) );
924 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
925 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
926 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
927 CurDAG->getTargetConstant(0, OpVT));
928 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
929 SDValue(ZeroFill, 0),
931 SDValue(SelMask, 0));
933 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
934 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
935 unsigned bits = unsigned(CN->getZExtValue()) & 7;
939 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
941 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
946 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
947 SDValue((Shift != 0 ? Shift : VecOp0), 0),
948 CurDAG->getTargetConstant(bits, ShiftAmtVT));
952 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
954 CurDAG->getTargetConstant(3, ShiftAmtVT));
956 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
958 CurDAG->getTargetConstant(7, ShiftAmtVT));
960 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
961 SDValue(VecOp0, 0), SDValue(Bytes, 0));
963 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
964 SDValue(Shift, 0), SDValue(Bits, 0));
967 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
968 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
972 * Emit the instruction sequence for i64 logical right shifts.
974 * @param Op The shl operand
975 * @param OpVT Op's machine value value type (doesn't need to be passed, but
976 * makes life easier.)
977 * @return The SDNode with the entire instruction sequence
980 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
981 SDValue Op0 = N->getOperand(0);
982 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
983 OpVT, (128 / OpVT.getSizeInBits()));
984 SDValue ShiftAmt = N->getOperand(1);
985 EVT ShiftAmtVT = ShiftAmt.getValueType();
986 SDNode *VecOp0, *Shift = 0;
987 DebugLoc dl = N->getDebugLoc();
989 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
990 Op0, getRC(MVT::v2i64) );
992 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
993 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
994 unsigned bits = unsigned(CN->getZExtValue()) & 7;
998 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1000 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1005 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1006 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1007 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1011 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1013 CurDAG->getTargetConstant(3, ShiftAmtVT));
1015 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1017 CurDAG->getTargetConstant(7, ShiftAmtVT));
1019 // Ensure that the shift amounts are negated!
1020 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1022 CurDAG->getTargetConstant(0, ShiftAmtVT));
1024 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1026 CurDAG->getTargetConstant(0, ShiftAmtVT));
1029 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1030 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1032 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1033 SDValue(Shift, 0), SDValue(Bits, 0));
1036 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1037 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1041 * Emit the instruction sequence for i64 arithmetic right shifts.
1043 * @param Op The shl operand
1044 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1045 * makes life easier.)
1046 * @return The SDNode with the entire instruction sequence
1049 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1050 // Promote Op0 to vector
1051 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1052 OpVT, (128 / OpVT.getSizeInBits()));
1053 SDValue ShiftAmt = N->getOperand(1);
1054 EVT ShiftAmtVT = ShiftAmt.getValueType();
1055 DebugLoc dl = N->getDebugLoc();
1058 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1059 VecVT, N->getOperand(0), getRC(MVT::v2i64));
1061 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1063 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1064 SDValue(VecOp0, 0), SignRotAmt);
1065 SDNode *UpperHalfSign =
1066 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1067 MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32));
1069 SDNode *UpperHalfSignMask =
1070 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1071 SDNode *UpperLowerMask =
1072 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1073 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1074 SDNode *UpperLowerSelect =
1075 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1076 SDValue(UpperHalfSignMask, 0),
1078 SDValue(UpperLowerMask, 0));
1082 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1083 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1084 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1089 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1090 SDValue(UpperLowerSelect, 0),
1091 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1097 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1098 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1099 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1103 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1104 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1107 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1108 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1110 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1111 SDValue(Shift, 0), SDValue(NegShift, 0));
1114 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1115 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1119 Do the necessary magic necessary to load a i64 constant
1121 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1123 ConstantSDNode *CN = cast<ConstantSDNode>(N);
1124 return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1127 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1129 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1131 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1133 // Here's where it gets interesting, because we have to parse out the
1134 // subtree handed back in i64vec:
1136 if (i64vec.getOpcode() == ISD::BITCAST) {
1137 // The degenerate case where the upper and lower bits in the splat are
1139 SDValue Op0 = i64vec.getOperand(0);
1141 ReplaceUses(i64vec, Op0);
1142 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1143 SDValue(emitBuildVector(Op0.getNode()), 0),
1145 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1146 SDValue lhs = i64vec.getOperand(0);
1147 SDValue rhs = i64vec.getOperand(1);
1148 SDValue shufmask = i64vec.getOperand(2);
1150 if (lhs.getOpcode() == ISD::BITCAST) {
1151 ReplaceUses(lhs, lhs.getOperand(0));
1152 lhs = lhs.getOperand(0);
1155 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1157 : emitBuildVector(lhs.getNode()));
1159 if (rhs.getOpcode() == ISD::BITCAST) {
1160 ReplaceUses(rhs, rhs.getOperand(0));
1161 rhs = rhs.getOperand(0);
1164 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1166 : emitBuildVector(rhs.getNode()));
1168 if (shufmask.getOpcode() == ISD::BITCAST) {
1169 ReplaceUses(shufmask, shufmask.getOperand(0));
1170 shufmask = shufmask.getOperand(0);
1173 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1174 ? shufmask.getNode()
1175 : emitBuildVector(shufmask.getNode()));
1178 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1179 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1180 SDValue(shufMaskNode, 0));
1181 HandleSDNode Dummy(shufNode);
1182 SDNode *SN = SelectCode(Dummy.getValue().getNode());
1183 if (SN == 0) SN = Dummy.getValue().getNode();
1185 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1186 OpVT, SDValue(SN, 0), getRC(MVT::i64));
1187 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1188 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1189 SDValue(emitBuildVector(i64vec.getNode()), 0),
1192 report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1197 /// createSPUISelDag - This pass converts a legalized DAG into a
1198 /// SPU-specific DAG, ready for instruction scheduling.
1200 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1201 return new SPUDAGToDAGISel(TM);