1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
41 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
43 isI64IntS10Immediate(ConstantSDNode *CN)
45 return isS10Constant(CN->getSignExtended());
48 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
50 isI32IntS10Immediate(ConstantSDNode *CN)
52 return isS10Constant(CN->getSignExtended());
56 //! SDNode predicate for sign-extended, 10-bit immediate values
58 isI32IntS10Immediate(SDNode *N)
60 return (N->getOpcode() == ISD::Constant
61 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
65 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
67 isI32IntU10Immediate(ConstantSDNode *CN)
69 return isU10Constant(CN->getSignExtended());
72 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
74 isI16IntS10Immediate(ConstantSDNode *CN)
76 return isS10Constant(CN->getSignExtended());
79 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
81 isI16IntS10Immediate(SDNode *N)
83 return (N->getOpcode() == ISD::Constant
84 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
87 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
89 isI16IntU10Immediate(ConstantSDNode *CN)
91 return isU10Constant((short) CN->getValue());
94 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
96 isI16IntU10Immediate(SDNode *N)
98 return (N->getOpcode() == ISD::Constant
99 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
102 //! ConstantSDNode predicate for signed 16-bit values
104 \arg CN The constant SelectionDAG node holding the value
105 \arg Imm The returned 16-bit value, if returning true
107 This predicate tests the value in \a CN to see whether it can be
108 represented as a 16-bit, sign-extended quantity. Returns true if
112 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
114 MVT::ValueType vt = CN->getValueType(0);
115 Imm = (short) CN->getValue();
116 if (vt >= MVT::i1 && vt <= MVT::i16) {
118 } else if (vt == MVT::i32) {
119 int32_t i_val = (int32_t) CN->getValue();
120 short s_val = (short) i_val;
121 return i_val == s_val;
123 int64_t i_val = (int64_t) CN->getValue();
124 short s_val = (short) i_val;
125 return i_val == s_val;
131 //! SDNode predicate for signed 16-bit values.
133 isIntS16Immediate(SDNode *N, short &Imm)
135 return (N->getOpcode() == ISD::Constant
136 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
139 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
141 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
143 MVT::ValueType vt = FPN->getValueType(0);
144 if (vt == MVT::f32) {
145 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
146 int sval = (int) ((val << 16) >> 16);
155 isHighLow(const SDOperand &Op)
157 return (Op.getOpcode() == SPUISD::IndirectAddr
158 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
159 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
160 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
161 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
164 //===------------------------------------------------------------------===//
165 //! MVT::ValueType to "useful stuff" mapping structure:
167 struct valtype_map_s {
169 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
170 bool ldresult_imm; /// LDRESULT instruction requires immediate?
171 int prefslot_byte; /// Byte offset of the "preferred" slot
174 const valtype_map_s valtype_map[] = {
175 { MVT::i1, 0, false, 3 },
176 { MVT::i8, SPU::ORBIr8, true, 3 },
177 { MVT::i16, SPU::ORHIr16, true, 2 },
178 { MVT::i32, SPU::ORIr32, true, 0 },
179 { MVT::i64, SPU::ORr64, false, 0 },
180 { MVT::f32, SPU::ORf32, false, 0 },
181 { MVT::f64, SPU::ORf64, false, 0 },
182 // vector types... (sigh!)
183 { MVT::v16i8, 0, false, 0 },
184 { MVT::v8i16, 0, false, 0 },
185 { MVT::v4i32, 0, false, 0 },
186 { MVT::v2i64, 0, false, 0 },
187 { MVT::v4f32, 0, false, 0 },
188 { MVT::v2f64, 0, false, 0 }
191 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
193 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
195 const valtype_map_s *retval = 0;
196 for (size_t i = 0; i < n_valtype_map; ++i) {
197 if (valtype_map[i].VT == VT) {
198 retval = valtype_map + i;
206 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
207 << MVT::getValueTypeString(VT)
219 //===--------------------------------------------------------------------===//
220 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
221 /// instructions for SelectionDAG operations.
223 class SPUDAGToDAGISel :
224 public SelectionDAGISel
226 SPUTargetMachine &TM;
227 SPUTargetLowering &SPUtli;
228 unsigned GlobalBaseReg;
231 SPUDAGToDAGISel(SPUTargetMachine &tm) :
232 SelectionDAGISel(*tm.getTargetLowering()),
234 SPUtli(*tm.getTargetLowering())
237 virtual bool runOnFunction(Function &Fn) {
238 // Make sure we re-emit a set of the global base reg if necessary
240 SelectionDAGISel::runOnFunction(Fn);
244 /// getI32Imm - Return a target constant with the specified value, of type
246 inline SDOperand getI32Imm(uint32_t Imm) {
247 return CurDAG->getTargetConstant(Imm, MVT::i32);
250 /// getI64Imm - Return a target constant with the specified value, of type
252 inline SDOperand getI64Imm(uint64_t Imm) {
253 return CurDAG->getTargetConstant(Imm, MVT::i64);
256 /// getSmallIPtrImm - Return a target constant of pointer type.
257 inline SDOperand getSmallIPtrImm(unsigned Imm) {
258 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
261 /// Select - Convert the specified operand from a target-independent to a
262 /// target-specific node if it hasn't already been changed.
263 SDNode *Select(SDOperand Op);
265 //! Returns true if the address N is an A-form (local store) address
266 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
269 //! D-form address predicate
270 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
273 /// Alternate D-form address using i7 offset predicate
274 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
277 /// D-form address selection workhorse
278 bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
279 SDOperand &Base, int minOffset, int maxOffset);
281 //! Address predicate if N can be expressed as an indexed [r+r] operation.
282 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
285 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
286 /// inline asm expressions.
287 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
289 std::vector<SDOperand> &OutOps,
292 switch (ConstraintCode) {
293 default: return true;
295 if (!SelectDFormAddr(Op, Op, Op0, Op1)
296 && !SelectAFormAddr(Op, Op, Op0, Op1))
297 SelectXFormAddr(Op, Op, Op0, Op1);
299 case 'o': // offsetable
300 if (!SelectDFormAddr(Op, Op, Op0, Op1)
301 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
303 AddToISelQueue(Op0); // r+0.
304 Op1 = getSmallIPtrImm(0);
307 case 'v': // not offsetable
309 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
311 SelectAddrIdxOnly(Op, Op, Op0, Op1);
316 OutOps.push_back(Op0);
317 OutOps.push_back(Op1);
321 /// InstructionSelectBasicBlock - This callback is invoked by
322 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
323 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
325 virtual const char *getPassName() const {
326 return "Cell SPU DAG->DAG Pattern Instruction Selection";
329 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
330 /// this target when scheduling the DAG.
331 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
332 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
333 assert(II && "No InstrInfo?");
334 return new SPUHazardRecognizer(*II);
337 // Include the pieces autogenerated from the target description.
338 #include "SPUGenDAGISel.inc"
343 /// InstructionSelectBasicBlock - This callback is invoked by
344 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
346 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
350 // Select target instructions for the DAG.
351 DAG.setRoot(SelectRoot(DAG.getRoot()));
352 DAG.RemoveDeadNodes();
354 // Emit machine code to BB.
355 ScheduleAndEmitDAG(DAG);
359 \arg Op The ISD instructio operand
360 \arg N The address to be tested
361 \arg Base The base address
362 \arg Index The base address index
365 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
367 // These match the addr256k operand type:
368 MVT::ValueType OffsVT = MVT::i16;
369 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
371 switch (N.getOpcode()) {
373 case ISD::ConstantPool:
374 case ISD::GlobalAddress:
375 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
379 case ISD::TargetConstant:
380 case ISD::TargetGlobalAddress:
381 case ISD::TargetJumpTable:
382 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
383 << "A-form address.\n";
387 case SPUISD::AFormAddr:
388 // Just load from memory if there's only a single use of the location,
389 // otherwise, this will get handled below with D-form offset addresses
391 SDOperand Op0 = N.getOperand(0);
392 switch (Op0.getOpcode()) {
393 case ISD::TargetConstantPool:
394 case ISD::TargetJumpTable:
399 case ISD::TargetGlobalAddress: {
400 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
401 GlobalValue *GV = GSDN->getGlobal();
402 if (GV->getAlignment() == 16) {
417 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
419 const int minDForm2Offset = -(1 << 7);
420 const int maxDForm2Offset = (1 << 7) - 1;
421 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
426 \arg Op The ISD instruction (ignored)
427 \arg N The address to be tested
428 \arg Base Base address register/pointer
429 \arg Index Base address index
431 Examine the input address by a base register plus a signed 10-bit
432 displacement, [r+I10] (D-form address).
434 \return true if \a N is a D-form address with \a Base and \a Index set
435 to non-empty SDOperand instances.
438 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
440 return DFormAddressPredicate(Op, N, Base, Index,
441 SPUFrameInfo::minFrameOffset(),
442 SPUFrameInfo::maxFrameOffset());
446 SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
447 SDOperand &Index, int minOffset,
449 unsigned Opc = N.getOpcode();
450 unsigned PtrTy = SPUtli.getPointerTy();
452 if (Opc == ISD::FrameIndex) {
453 // Stack frame index must be less than 512 (divided by 16):
454 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
455 int FI = int(FIN->getIndex());
456 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
458 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
459 Base = CurDAG->getTargetConstant(0, PtrTy);
460 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
463 } else if (Opc == ISD::ADD) {
464 // Generated by getelementptr
465 const SDOperand Op0 = N.getOperand(0);
466 const SDOperand Op1 = N.getOperand(1);
468 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
469 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
470 Base = CurDAG->getTargetConstant(0, PtrTy);
473 } else if (Op1.getOpcode() == ISD::Constant
474 || Op1.getOpcode() == ISD::TargetConstant) {
475 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
476 int32_t offset = int32_t(CN->getSignExtended());
478 if (Op0.getOpcode() == ISD::FrameIndex) {
479 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
480 int FI = int(FIN->getIndex());
481 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
482 << " frame index = " << FI << "\n");
484 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
485 Base = CurDAG->getTargetConstant(offset, PtrTy);
486 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
489 } else if (offset > minOffset && offset < maxOffset) {
490 Base = CurDAG->getTargetConstant(offset, PtrTy);
494 } else if (Op0.getOpcode() == ISD::Constant
495 || Op0.getOpcode() == ISD::TargetConstant) {
496 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
497 int32_t offset = int32_t(CN->getSignExtended());
499 if (Op1.getOpcode() == ISD::FrameIndex) {
500 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
501 int FI = int(FIN->getIndex());
502 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
503 << " frame index = " << FI << "\n");
505 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
506 Base = CurDAG->getTargetConstant(offset, PtrTy);
507 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
510 } else if (offset > minOffset && offset < maxOffset) {
511 Base = CurDAG->getTargetConstant(offset, PtrTy);
516 } else if (Opc == SPUISD::IndirectAddr) {
517 // Indirect with constant offset -> D-Form address
518 const SDOperand Op0 = N.getOperand(0);
519 const SDOperand Op1 = N.getOperand(1);
521 if (Op0.getOpcode() == SPUISD::Hi
522 && Op1.getOpcode() == SPUISD::Lo) {
523 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
524 Base = CurDAG->getTargetConstant(0, PtrTy);
527 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
531 if (isa<ConstantSDNode>(Op1)) {
532 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
533 offset = int32_t(CN->getSignExtended());
535 } else if (isa<ConstantSDNode>(Op0)) {
536 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
537 offset = int32_t(CN->getSignExtended());
541 if (offset >= minOffset && offset <= maxOffset) {
542 Base = CurDAG->getTargetConstant(offset, PtrTy);
547 } else if (Opc == SPUISD::AFormAddr) {
548 Base = CurDAG->getTargetConstant(0, N.getValueType());
551 } else if (Opc == SPUISD::LDRESULT) {
552 Base = CurDAG->getTargetConstant(0, N.getValueType());
560 \arg Op The ISD instruction operand
561 \arg N The address operand
562 \arg Base The base pointer operand
563 \arg Index The offset/index operand
565 If the address \a N can be expressed as a [r + s10imm] address, returns false.
566 Otherwise, creates two operands, Base and Index that will become the [r+r]
570 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
572 if (SelectAFormAddr(Op, N, Base, Index)
573 || SelectDFormAddr(Op, N, Base, Index))
576 // All else fails, punt and use an X-form address:
577 Base = N.getOperand(0);
578 Index = N.getOperand(1);
582 //! Convert the operand from a target-independent to a target-specific node
586 SPUDAGToDAGISel::Select(SDOperand Op) {
588 unsigned Opc = N->getOpcode();
591 MVT::ValueType OpVT = Op.getValueType();
594 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
595 return NULL; // Already selected.
596 } else if (Opc == ISD::FrameIndex) {
597 // Selects to (add $sp, FI * stackSlotSize)
599 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
600 MVT::ValueType PtrVT = SPUtli.getPointerTy();
602 // Adjust stack slot to actual offset in frame:
603 if (isS10Constant(FI)) {
604 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
608 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
609 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
612 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
616 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
617 Ops[1] = CurDAG->getConstant(FI, PtrVT);
620 AddToISelQueue(Ops[1]);
622 } else if (Opc == ISD::ZERO_EXTEND) {
623 // (zero_extend:i16 (and:i8 <arg>, <const>))
624 const SDOperand &Op1 = N->getOperand(0);
626 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
627 if (Op1.getOpcode() == ISD::AND) {
628 // Fold this into a single ANDHI. This is often seen in expansions of i1
629 // to i8, then i8 to i16 in logical/branching operations.
630 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
631 "<arg>, <const>))\n");
632 NewOpc = SPU::ANDHIi8i16;
633 Ops[0] = Op1.getOperand(0);
634 Ops[1] = Op1.getOperand(1);
638 } else if (Opc == SPUISD::LDRESULT) {
639 // Custom select instructions for LDRESULT
640 unsigned VT = N->getValueType(0);
641 SDOperand Arg = N->getOperand(0);
642 SDOperand Chain = N->getOperand(1);
644 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
646 if (vtm->ldresult_ins == 0) {
647 cerr << "LDRESULT for unsupported type: "
648 << MVT::getValueTypeString(VT)
654 Opc = vtm->ldresult_ins;
655 if (vtm->ldresult_imm) {
656 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
658 AddToISelQueue(Zero);
659 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
661 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
664 Chain = SDOperand(Result, 1);
665 AddToISelQueue(Chain);
668 } else if (Opc == SPUISD::IndirectAddr) {
669 SDOperand Op0 = Op.getOperand(0);
670 if (Op0.getOpcode() == SPUISD::LDRESULT) {
671 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
672 // (IndirectAddr (LDRESULT, imm))
673 SDOperand Op1 = Op.getOperand(1);
674 MVT::ValueType VT = Op.getValueType();
676 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
677 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
678 DEBUG(cerr << "\nOp1 = ");
679 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
682 if (Op1.getOpcode() == ISD::Constant) {
683 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
684 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
685 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
697 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
699 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
701 return SelectCode(Op);
704 /// createPPCISelDag - This pass converts a legalized DAG into a
705 /// SPU-specific DAG, ready for instruction scheduling.
707 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
708 return new SPUDAGToDAGISel(TM);