1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSignExtended());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSignExtended());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant(CN->getSignExtended());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant(CN->getSignExtended());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDOperand &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 bool ldresult_imm; /// LDRESULT instruction requires immediate?
170 int prefslot_byte; /// Byte offset of the "preferred" slot
173 const valtype_map_s valtype_map[] = {
174 { MVT::i1, 0, false, 3 },
175 { MVT::i8, SPU::ORBIr8, true, 3 },
176 { MVT::i16, SPU::ORHIr16, true, 2 },
177 { MVT::i32, SPU::ORIr32, true, 0 },
178 { MVT::i64, SPU::ORr64, false, 0 },
179 { MVT::f32, SPU::ORf32, false, 0 },
180 { MVT::f64, SPU::ORf64, false, 0 },
181 // vector types... (sigh!)
182 { MVT::v16i8, 0, false, 0 },
183 { MVT::v8i16, 0, false, 0 },
184 { MVT::v4i32, 0, false, 0 },
185 { MVT::v2i64, 0, false, 0 },
186 { MVT::v4f32, 0, false, 0 },
187 { MVT::v2f64, 0, false, 0 }
190 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
192 const valtype_map_s *getValueTypeMapEntry(MVT VT)
194 const valtype_map_s *retval = 0;
195 for (size_t i = 0; i < n_valtype_map; ++i) {
196 if (valtype_map[i].VT == VT) {
197 retval = valtype_map + i;
205 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
218 //===--------------------------------------------------------------------===//
219 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
220 /// instructions for SelectionDAG operations.
222 class SPUDAGToDAGISel :
223 public SelectionDAGISel
225 SPUTargetMachine &TM;
226 SPUTargetLowering &SPUtli;
227 unsigned GlobalBaseReg;
230 SPUDAGToDAGISel(SPUTargetMachine &tm) :
231 SelectionDAGISel(*tm.getTargetLowering()),
233 SPUtli(*tm.getTargetLowering())
236 virtual bool runOnFunction(Function &Fn) {
237 // Make sure we re-emit a set of the global base reg if necessary
239 SelectionDAGISel::runOnFunction(Fn);
243 /// getI32Imm - Return a target constant with the specified value, of type
245 inline SDOperand getI32Imm(uint32_t Imm) {
246 return CurDAG->getTargetConstant(Imm, MVT::i32);
249 /// getI64Imm - Return a target constant with the specified value, of type
251 inline SDOperand getI64Imm(uint64_t Imm) {
252 return CurDAG->getTargetConstant(Imm, MVT::i64);
255 /// getSmallIPtrImm - Return a target constant of pointer type.
256 inline SDOperand getSmallIPtrImm(unsigned Imm) {
257 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
260 /// Select - Convert the specified operand from a target-independent to a
261 /// target-specific node if it hasn't already been changed.
262 SDNode *Select(SDOperand Op);
264 //! Returns true if the address N is an A-form (local store) address
265 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
268 //! D-form address predicate
269 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
272 /// Alternate D-form address using i7 offset predicate
273 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
276 /// D-form address selection workhorse
277 bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
278 SDOperand &Base, int minOffset, int maxOffset);
280 //! Address predicate if N can be expressed as an indexed [r+r] operation.
281 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
284 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
285 /// inline asm expressions.
286 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
288 std::vector<SDOperand> &OutOps,
291 switch (ConstraintCode) {
292 default: return true;
294 if (!SelectDFormAddr(Op, Op, Op0, Op1)
295 && !SelectAFormAddr(Op, Op, Op0, Op1))
296 SelectXFormAddr(Op, Op, Op0, Op1);
298 case 'o': // offsetable
299 if (!SelectDFormAddr(Op, Op, Op0, Op1)
300 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
302 AddToISelQueue(Op0); // r+0.
303 Op1 = getSmallIPtrImm(0);
306 case 'v': // not offsetable
308 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
310 SelectAddrIdxOnly(Op, Op, Op0, Op1);
315 OutOps.push_back(Op0);
316 OutOps.push_back(Op1);
320 /// InstructionSelectBasicBlock - This callback is invoked by
321 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
322 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
324 virtual const char *getPassName() const {
325 return "Cell SPU DAG->DAG Pattern Instruction Selection";
328 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
329 /// this target when scheduling the DAG.
330 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
331 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
332 assert(II && "No InstrInfo?");
333 return new SPUHazardRecognizer(*II);
336 // Include the pieces autogenerated from the target description.
337 #include "SPUGenDAGISel.inc"
342 /// InstructionSelectBasicBlock - This callback is invoked by
343 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
345 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
349 // Select target instructions for the DAG.
350 DAG.setRoot(SelectRoot(DAG.getRoot()));
351 DAG.RemoveDeadNodes();
353 // Emit machine code to BB.
354 ScheduleAndEmitDAG(DAG);
358 \arg Op The ISD instructio operand
359 \arg N The address to be tested
360 \arg Base The base address
361 \arg Index The base address index
364 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
366 // These match the addr256k operand type:
367 MVT OffsVT = MVT::i16;
368 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
370 switch (N.getOpcode()) {
372 case ISD::ConstantPool:
373 case ISD::GlobalAddress:
374 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
378 case ISD::TargetConstant:
379 case ISD::TargetGlobalAddress:
380 case ISD::TargetJumpTable:
381 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
382 << "A-form address.\n";
386 case SPUISD::AFormAddr:
387 // Just load from memory if there's only a single use of the location,
388 // otherwise, this will get handled below with D-form offset addresses
390 SDOperand Op0 = N.getOperand(0);
391 switch (Op0.getOpcode()) {
392 case ISD::TargetConstantPool:
393 case ISD::TargetJumpTable:
398 case ISD::TargetGlobalAddress: {
399 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
400 GlobalValue *GV = GSDN->getGlobal();
401 if (GV->getAlignment() == 16) {
416 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
418 const int minDForm2Offset = -(1 << 7);
419 const int maxDForm2Offset = (1 << 7) - 1;
420 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
425 \arg Op The ISD instruction (ignored)
426 \arg N The address to be tested
427 \arg Base Base address register/pointer
428 \arg Index Base address index
430 Examine the input address by a base register plus a signed 10-bit
431 displacement, [r+I10] (D-form address).
433 \return true if \a N is a D-form address with \a Base and \a Index set
434 to non-empty SDOperand instances.
437 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
439 return DFormAddressPredicate(Op, N, Base, Index,
440 SPUFrameInfo::minFrameOffset(),
441 SPUFrameInfo::maxFrameOffset());
445 SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
446 SDOperand &Index, int minOffset,
448 unsigned Opc = N.getOpcode();
449 MVT PtrTy = SPUtli.getPointerTy();
451 if (Opc == ISD::FrameIndex) {
452 // Stack frame index must be less than 512 (divided by 16):
453 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
454 int FI = int(FIN->getIndex());
455 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
457 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
458 Base = CurDAG->getTargetConstant(0, PtrTy);
459 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
462 } else if (Opc == ISD::ADD) {
463 // Generated by getelementptr
464 const SDOperand Op0 = N.getOperand(0);
465 const SDOperand Op1 = N.getOperand(1);
467 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
468 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
469 Base = CurDAG->getTargetConstant(0, PtrTy);
472 } else if (Op1.getOpcode() == ISD::Constant
473 || Op1.getOpcode() == ISD::TargetConstant) {
474 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
475 int32_t offset = int32_t(CN->getSignExtended());
477 if (Op0.getOpcode() == ISD::FrameIndex) {
478 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
479 int FI = int(FIN->getIndex());
480 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
481 << " frame index = " << FI << "\n");
483 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
484 Base = CurDAG->getTargetConstant(offset, PtrTy);
485 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
488 } else if (offset > minOffset && offset < maxOffset) {
489 Base = CurDAG->getTargetConstant(offset, PtrTy);
493 } else if (Op0.getOpcode() == ISD::Constant
494 || Op0.getOpcode() == ISD::TargetConstant) {
495 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
496 int32_t offset = int32_t(CN->getSignExtended());
498 if (Op1.getOpcode() == ISD::FrameIndex) {
499 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
500 int FI = int(FIN->getIndex());
501 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
502 << " frame index = " << FI << "\n");
504 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
505 Base = CurDAG->getTargetConstant(offset, PtrTy);
506 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
509 } else if (offset > minOffset && offset < maxOffset) {
510 Base = CurDAG->getTargetConstant(offset, PtrTy);
515 } else if (Opc == SPUISD::IndirectAddr) {
516 // Indirect with constant offset -> D-Form address
517 const SDOperand Op0 = N.getOperand(0);
518 const SDOperand Op1 = N.getOperand(1);
520 if (Op0.getOpcode() == SPUISD::Hi
521 && Op1.getOpcode() == SPUISD::Lo) {
522 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
523 Base = CurDAG->getTargetConstant(0, PtrTy);
526 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
530 if (isa<ConstantSDNode>(Op1)) {
531 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
532 offset = int32_t(CN->getSignExtended());
534 } else if (isa<ConstantSDNode>(Op0)) {
535 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
536 offset = int32_t(CN->getSignExtended());
540 if (offset >= minOffset && offset <= maxOffset) {
541 Base = CurDAG->getTargetConstant(offset, PtrTy);
546 } else if (Opc == SPUISD::AFormAddr) {
547 Base = CurDAG->getTargetConstant(0, N.getValueType());
550 } else if (Opc == SPUISD::LDRESULT) {
551 Base = CurDAG->getTargetConstant(0, N.getValueType());
559 \arg Op The ISD instruction operand
560 \arg N The address operand
561 \arg Base The base pointer operand
562 \arg Index The offset/index operand
564 If the address \a N can be expressed as a [r + s10imm] address, returns false.
565 Otherwise, creates two operands, Base and Index that will become the [r+r]
569 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
571 if (SelectAFormAddr(Op, N, Base, Index)
572 || SelectDFormAddr(Op, N, Base, Index))
575 // All else fails, punt and use an X-form address:
576 Base = N.getOperand(0);
577 Index = N.getOperand(1);
581 //! Convert the operand from a target-independent to a target-specific node
585 SPUDAGToDAGISel::Select(SDOperand Op) {
587 unsigned Opc = N->getOpcode();
590 MVT OpVT = Op.getValueType();
593 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
594 return NULL; // Already selected.
595 } else if (Opc == ISD::FrameIndex) {
596 // Selects to (add $sp, FI * stackSlotSize)
598 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
599 MVT PtrVT = SPUtli.getPointerTy();
601 // Adjust stack slot to actual offset in frame:
602 if (isS10Constant(FI)) {
603 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
607 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
608 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
611 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
615 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
616 Ops[1] = CurDAG->getConstant(FI, PtrVT);
619 AddToISelQueue(Ops[1]);
621 } else if (Opc == ISD::ZERO_EXTEND) {
622 // (zero_extend:i16 (and:i8 <arg>, <const>))
623 const SDOperand &Op1 = N->getOperand(0);
625 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
626 if (Op1.getOpcode() == ISD::AND) {
627 // Fold this into a single ANDHI. This is often seen in expansions of i1
628 // to i8, then i8 to i16 in logical/branching operations.
629 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
630 "<arg>, <const>))\n");
631 NewOpc = SPU::ANDHIi8i16;
632 Ops[0] = Op1.getOperand(0);
633 Ops[1] = Op1.getOperand(1);
637 } else if (Opc == SPUISD::LDRESULT) {
638 // Custom select instructions for LDRESULT
639 MVT VT = N->getValueType(0);
640 SDOperand Arg = N->getOperand(0);
641 SDOperand Chain = N->getOperand(1);
643 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
645 if (vtm->ldresult_ins == 0) {
646 cerr << "LDRESULT for unsupported type: "
653 Opc = vtm->ldresult_ins;
654 if (vtm->ldresult_imm) {
655 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
657 AddToISelQueue(Zero);
658 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
660 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
663 Chain = SDOperand(Result, 1);
664 AddToISelQueue(Chain);
667 } else if (Opc == SPUISD::IndirectAddr) {
668 SDOperand Op0 = Op.getOperand(0);
669 if (Op0.getOpcode() == SPUISD::LDRESULT) {
670 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
671 // (IndirectAddr (LDRESULT, imm))
672 SDOperand Op1 = Op.getOperand(1);
673 MVT VT = Op.getValueType();
675 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
676 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
677 DEBUG(cerr << "\nOp1 = ");
678 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
681 if (Op1.getOpcode() == ISD::Constant) {
682 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
683 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
684 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
696 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
698 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
700 return SelectCode(Op);
703 /// createPPCISelDag - This pass converts a legalized DAG into a
704 /// SPU-specific DAG, ready for instruction scheduling.
706 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
707 return new SPUDAGToDAGISel(TM);