1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "SPUFrameInfo.h"
19 #include "SPURegisterNames.h"
20 #include "SPUTargetMachine.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Constants.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/raw_ostream.h"
42 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
44 isI64IntS10Immediate(ConstantSDNode *CN)
46 return isInt<10>(CN->getSExtValue());
49 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
51 isI32IntS10Immediate(ConstantSDNode *CN)
53 return isInt<10>(CN->getSExtValue());
56 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
58 isI32IntU10Immediate(ConstantSDNode *CN)
60 return isUInt<10>(CN->getSExtValue());
63 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
65 isI16IntS10Immediate(ConstantSDNode *CN)
67 return isInt<10>(CN->getSExtValue());
70 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
72 isI16IntS10Immediate(SDNode *N)
74 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
75 return (CN != 0 && isI16IntS10Immediate(CN));
78 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
80 isI16IntU10Immediate(ConstantSDNode *CN)
82 return isUInt<10>((short) CN->getZExtValue());
85 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
87 isI16IntU10Immediate(SDNode *N)
89 return (N->getOpcode() == ISD::Constant
90 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
93 //! ConstantSDNode predicate for signed 16-bit values
95 \arg CN The constant SelectionDAG node holding the value
96 \arg Imm The returned 16-bit value, if returning true
98 This predicate tests the value in \a CN to see whether it can be
99 represented as a 16-bit, sign-extended quantity. Returns true if
103 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
105 EVT vt = CN->getValueType(0);
106 Imm = (short) CN->getZExtValue();
107 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
109 } else if (vt == MVT::i32) {
110 int32_t i_val = (int32_t) CN->getZExtValue();
111 short s_val = (short) i_val;
112 return i_val == s_val;
114 int64_t i_val = (int64_t) CN->getZExtValue();
115 short s_val = (short) i_val;
116 return i_val == s_val;
122 //! SDNode predicate for signed 16-bit values.
124 isIntS16Immediate(SDNode *N, short &Imm)
126 return (N->getOpcode() == ISD::Constant
127 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
130 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
132 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
134 EVT vt = FPN->getValueType(0);
135 if (vt == MVT::f32) {
136 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
137 int sval = (int) ((val << 16) >> 16);
146 isHighLow(const SDValue &Op)
148 return (Op.getOpcode() == SPUISD::IndirectAddr
149 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
150 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
151 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
152 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
155 //===------------------------------------------------------------------===//
156 //! EVT to "useful stuff" mapping structure:
158 struct valtype_map_s {
160 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
161 bool ldresult_imm; /// LDRESULT instruction requires immediate?
162 unsigned lrinst; /// LR instruction
165 const valtype_map_s valtype_map[] = {
166 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
167 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
168 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
169 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
170 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
171 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
172 // vector types... (sigh!)
173 { MVT::v16i8, 0, false, SPU::LRv16i8 },
174 { MVT::v8i16, 0, false, SPU::LRv8i16 },
175 { MVT::v4i32, 0, false, SPU::LRv4i32 },
176 { MVT::v2i64, 0, false, SPU::LRv2i64 },
177 { MVT::v4f32, 0, false, SPU::LRv4f32 },
178 { MVT::v2f64, 0, false, SPU::LRv2f64 }
181 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
183 const valtype_map_s *getValueTypeMapEntry(EVT VT)
185 const valtype_map_s *retval = 0;
186 for (size_t i = 0; i < n_valtype_map; ++i) {
187 if (valtype_map[i].VT == VT) {
188 retval = valtype_map + i;
196 report_fatal_error("SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns"
197 "NULL for " + Twine(VT.getEVTString()));
204 //! Generate the carry-generate shuffle mask.
205 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
206 SmallVector<SDValue, 16 > ShufBytes;
208 // Create the shuffle mask for "rotating" the borrow up one register slot
209 // once the borrow is generated.
210 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
211 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
212 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
213 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
215 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
216 &ShufBytes[0], ShufBytes.size());
219 //! Generate the borrow-generate shuffle mask
220 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
221 SmallVector<SDValue, 16 > ShufBytes;
223 // Create the shuffle mask for "rotating" the borrow up one register slot
224 // once the borrow is generated.
225 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
226 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
227 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
228 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
230 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
231 &ShufBytes[0], ShufBytes.size());
234 //===------------------------------------------------------------------===//
235 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
236 /// instructions for SelectionDAG operations.
238 class SPUDAGToDAGISel :
239 public SelectionDAGISel
241 const SPUTargetMachine &TM;
242 const SPUTargetLowering &SPUtli;
243 unsigned GlobalBaseReg;
246 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
247 SelectionDAGISel(tm),
249 SPUtli(*tm.getTargetLowering())
252 virtual bool runOnMachineFunction(MachineFunction &MF) {
253 // Make sure we re-emit a set of the global base reg if necessary
255 SelectionDAGISel::runOnMachineFunction(MF);
259 /// getI32Imm - Return a target constant with the specified value, of type
261 inline SDValue getI32Imm(uint32_t Imm) {
262 return CurDAG->getTargetConstant(Imm, MVT::i32);
265 /// getI64Imm - Return a target constant with the specified value, of type
267 inline SDValue getI64Imm(uint64_t Imm) {
268 return CurDAG->getTargetConstant(Imm, MVT::i64);
271 /// getSmallIPtrImm - Return a target constant of pointer type.
272 inline SDValue getSmallIPtrImm(unsigned Imm) {
273 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
276 SDNode *emitBuildVector(SDNode *bvNode) {
277 EVT vecVT = bvNode->getValueType(0);
278 DebugLoc dl = bvNode->getDebugLoc();
280 // Check to see if this vector can be represented as a CellSPU immediate
281 // constant by invoking all of the instruction selection predicates:
282 if (((vecVT == MVT::v8i16) &&
283 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
284 ((vecVT == MVT::v4i32) &&
285 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
286 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
287 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
288 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
289 ((vecVT == MVT::v2i64) &&
290 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
291 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
292 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
293 HandleSDNode Dummy(SDValue(bvNode, 0));
294 if (SDNode *N = Select(bvNode))
296 return Dummy.getValue().getNode();
299 // No, need to emit a constant pool spill:
300 std::vector<Constant*> CV;
302 for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
303 ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
304 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
307 const Constant *CP = ConstantVector::get(CV);
308 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
309 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
310 SDValue CGPoolOffset =
311 SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
313 HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
314 CurDAG->getEntryNode(), CGPoolOffset,
315 PseudoSourceValue::getConstantPool(),0,
316 false, false, Alignment));
317 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
318 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
320 return Dummy.getValue().getNode();
323 /// Select - Convert the specified operand from a target-independent to a
324 /// target-specific node if it hasn't already been changed.
325 SDNode *Select(SDNode *N);
327 //! Emit the instruction sequence for i64 shl
328 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
330 //! Emit the instruction sequence for i64 srl
331 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
333 //! Emit the instruction sequence for i64 sra
334 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
336 //! Emit the necessary sequence for loading i64 constants:
337 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
339 //! Alternate instruction emit sequence for loading i64 constants
340 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
342 //! Returns true if the address N is an A-form (local store) address
343 bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
346 //! D-form address predicate
347 bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
350 /// Alternate D-form address using i7 offset predicate
351 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
354 /// D-form address selection workhorse
355 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
356 SDValue &Base, int minOffset, int maxOffset);
358 //! Address predicate if N can be expressed as an indexed [r+r] operation.
359 bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
362 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
363 /// inline asm expressions.
364 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
366 std::vector<SDValue> &OutOps) {
368 switch (ConstraintCode) {
369 default: return true;
371 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
372 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
373 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
375 case 'o': // offsetable
376 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
377 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
379 Op1 = getSmallIPtrImm(0);
382 case 'v': // not offsetable
384 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
386 SelectAddrIdxOnly(Op, Op, Op0, Op1);
391 OutOps.push_back(Op0);
392 OutOps.push_back(Op1);
396 virtual const char *getPassName() const {
397 return "Cell SPU DAG->DAG Pattern Instruction Selection";
400 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
401 /// this target when scheduling the DAG.
402 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
403 const TargetInstrInfo *II = TM.getInstrInfo();
404 assert(II && "No InstrInfo?");
405 return new SPUHazardRecognizer(*II);
408 // Include the pieces autogenerated from the target description.
409 #include "SPUGenDAGISel.inc"
414 \arg Op The ISD instruction operand
415 \arg N The address to be tested
416 \arg Base The base address
417 \arg Index The base address index
420 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
422 // These match the addr256k operand type:
423 EVT OffsVT = MVT::i16;
424 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
426 switch (N.getOpcode()) {
428 case ISD::ConstantPool:
429 case ISD::GlobalAddress:
430 report_fatal_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
433 case ISD::TargetConstant:
434 case ISD::TargetGlobalAddress:
435 case ISD::TargetJumpTable:
436 report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
437 "not wrapped as A-form address.");
440 case SPUISD::AFormAddr:
441 // Just load from memory if there's only a single use of the location,
442 // otherwise, this will get handled below with D-form offset addresses
444 SDValue Op0 = N.getOperand(0);
445 switch (Op0.getOpcode()) {
446 case ISD::TargetConstantPool:
447 case ISD::TargetJumpTable:
452 case ISD::TargetGlobalAddress: {
453 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
454 const GlobalValue *GV = GSDN->getGlobal();
455 if (GV->getAlignment() == 16) {
470 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
472 const int minDForm2Offset = -(1 << 7);
473 const int maxDForm2Offset = (1 << 7) - 1;
474 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
479 \arg Op The ISD instruction (ignored)
480 \arg N The address to be tested
481 \arg Base Base address register/pointer
482 \arg Index Base address index
484 Examine the input address by a base register plus a signed 10-bit
485 displacement, [r+I10] (D-form address).
487 \return true if \a N is a D-form address with \a Base and \a Index set
488 to non-empty SDValue instances.
491 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
493 return DFormAddressPredicate(Op, N, Base, Index,
494 SPUFrameInfo::minFrameOffset(),
495 SPUFrameInfo::maxFrameOffset());
499 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
500 SDValue &Index, int minOffset,
502 unsigned Opc = N.getOpcode();
503 EVT PtrTy = SPUtli.getPointerTy();
505 if (Opc == ISD::FrameIndex) {
506 // Stack frame index must be less than 512 (divided by 16):
507 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
508 int FI = int(FIN->getIndex());
509 DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
511 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
512 Base = CurDAG->getTargetConstant(0, PtrTy);
513 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
516 } else if (Opc == ISD::ADD) {
517 // Generated by getelementptr
518 const SDValue Op0 = N.getOperand(0);
519 const SDValue Op1 = N.getOperand(1);
521 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
522 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
523 Base = CurDAG->getTargetConstant(0, PtrTy);
526 } else if (Op1.getOpcode() == ISD::Constant
527 || Op1.getOpcode() == ISD::TargetConstant) {
528 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
529 int32_t offset = int32_t(CN->getSExtValue());
531 if (Op0.getOpcode() == ISD::FrameIndex) {
532 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
533 int FI = int(FIN->getIndex());
534 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
535 << " frame index = " << FI << "\n");
537 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
538 Base = CurDAG->getTargetConstant(offset, PtrTy);
539 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
542 } else if (offset > minOffset && offset < maxOffset) {
543 Base = CurDAG->getTargetConstant(offset, PtrTy);
547 } else if (Op0.getOpcode() == ISD::Constant
548 || Op0.getOpcode() == ISD::TargetConstant) {
549 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
550 int32_t offset = int32_t(CN->getSExtValue());
552 if (Op1.getOpcode() == ISD::FrameIndex) {
553 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
554 int FI = int(FIN->getIndex());
555 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
556 << " frame index = " << FI << "\n");
558 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
559 Base = CurDAG->getTargetConstant(offset, PtrTy);
560 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
563 } else if (offset > minOffset && offset < maxOffset) {
564 Base = CurDAG->getTargetConstant(offset, PtrTy);
569 } else if (Opc == SPUISD::IndirectAddr) {
570 // Indirect with constant offset -> D-Form address
571 const SDValue Op0 = N.getOperand(0);
572 const SDValue Op1 = N.getOperand(1);
574 if (Op0.getOpcode() == SPUISD::Hi
575 && Op1.getOpcode() == SPUISD::Lo) {
576 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
577 Base = CurDAG->getTargetConstant(0, PtrTy);
580 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
584 if (isa<ConstantSDNode>(Op1)) {
585 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
586 offset = int32_t(CN->getSExtValue());
588 } else if (isa<ConstantSDNode>(Op0)) {
589 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
590 offset = int32_t(CN->getSExtValue());
594 if (offset >= minOffset && offset <= maxOffset) {
595 Base = CurDAG->getTargetConstant(offset, PtrTy);
600 } else if (Opc == SPUISD::AFormAddr) {
601 Base = CurDAG->getTargetConstant(0, N.getValueType());
604 } else if (Opc == SPUISD::LDRESULT) {
605 Base = CurDAG->getTargetConstant(0, N.getValueType());
608 } else if (Opc == ISD::Register
609 ||Opc == ISD::CopyFromReg
611 ||Opc == ISD::Constant) {
612 unsigned OpOpc = Op->getOpcode();
614 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
615 // Direct load/store without getelementptr
618 Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
620 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
621 if (Offs.getOpcode() == ISD::UNDEF)
622 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
629 /* If otherwise unadorned, default to D-form address with 0 offset: */
630 if (Opc == ISD::CopyFromReg) {
631 Index = N.getOperand(1);
636 Base = CurDAG->getTargetConstant(0, Index.getValueType());
645 \arg Op The ISD instruction operand
646 \arg N The address operand
647 \arg Base The base pointer operand
648 \arg Index The offset/index operand
650 If the address \a N can be expressed as an A-form or D-form address, returns
651 false. Otherwise, creates two operands, Base and Index that will become the
652 (r)(r) X-form address.
655 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
657 if (!SelectAFormAddr(Op, N, Base, Index)
658 && !SelectDFormAddr(Op, N, Base, Index)) {
659 // If the address is neither A-form or D-form, punt and use an X-form
661 Base = N.getOperand(1);
662 Index = N.getOperand(0);
669 //! Convert the operand from a target-independent to a target-specific node
673 SPUDAGToDAGISel::Select(SDNode *N) {
674 unsigned Opc = N->getOpcode();
677 EVT OpVT = N->getValueType(0);
679 DebugLoc dl = N->getDebugLoc();
681 if (N->isMachineOpcode())
682 return NULL; // Already selected.
684 if (Opc == ISD::FrameIndex) {
685 int FI = cast<FrameIndexSDNode>(N)->getIndex();
686 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
687 SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
696 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
697 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
698 N->getValueType(0), TFI, Imm0),
702 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
703 // Catch the i64 constants that end up here. Note: The backend doesn't
704 // attempt to legalize the constant (it's useless because DAGCombiner
705 // will insert 64-bit constants and we can't stop it).
706 return SelectI64Constant(N, OpVT, N->getDebugLoc());
707 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
708 && OpVT == MVT::i64) {
709 SDValue Op0 = N->getOperand(0);
710 EVT Op0VT = Op0.getValueType();
711 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
712 Op0VT, (128 / Op0VT.getSizeInBits()));
713 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
714 OpVT, (128 / OpVT.getSizeInBits()));
717 switch (Op0VT.getSimpleVT().SimpleTy) {
719 report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
722 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
723 CurDAG->getConstant(0x80808080, MVT::i32),
724 CurDAG->getConstant(0x00010203, MVT::i32),
725 CurDAG->getConstant(0x80808080, MVT::i32),
726 CurDAG->getConstant(0x08090a0b, MVT::i32));
730 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
731 CurDAG->getConstant(0x80808080, MVT::i32),
732 CurDAG->getConstant(0x80800203, MVT::i32),
733 CurDAG->getConstant(0x80808080, MVT::i32),
734 CurDAG->getConstant(0x80800a0b, MVT::i32));
738 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
739 CurDAG->getConstant(0x80808080, MVT::i32),
740 CurDAG->getConstant(0x80808003, MVT::i32),
741 CurDAG->getConstant(0x80808080, MVT::i32),
742 CurDAG->getConstant(0x8080800b, MVT::i32));
746 SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
748 HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
752 if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
753 PromScalar = SDValue(N, 0);
755 PromScalar = PromoteScalar.getValue();
757 SDValue zextShuffle =
758 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
759 PromScalar, PromScalar,
760 SDValue(shufMaskLoad, 0));
762 HandleSDNode Dummy2(zextShuffle);
763 if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
764 zextShuffle = SDValue(N, 0);
766 zextShuffle = Dummy2.getValue();
767 HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
770 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
771 SelectCode(Dummy.getValue().getNode());
772 return Dummy.getValue().getNode();
773 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
775 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
777 HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
778 N->getOperand(0), N->getOperand(1),
779 SDValue(CGLoad, 0)));
781 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
782 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
784 return Dummy.getValue().getNode();
785 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
787 emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
789 HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
790 N->getOperand(0), N->getOperand(1),
791 SDValue(CGLoad, 0)));
793 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
794 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
796 return Dummy.getValue().getNode();
797 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
799 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
801 HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
802 N->getOperand(0), N->getOperand(1),
803 SDValue(CGLoad, 0)));
804 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
805 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
807 return Dummy.getValue().getNode();
808 } else if (Opc == ISD::TRUNCATE) {
809 SDValue Op0 = N->getOperand(0);
810 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
812 && Op0.getValueType() == MVT::i64) {
813 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
815 // Take advantage of the fact that the upper 32 bits are in the
816 // i32 preferred slot and avoid shuffle gymnastics:
817 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
819 unsigned shift_amt = unsigned(CN->getZExtValue());
821 if (shift_amt >= 32) {
823 CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT,
828 // Take care of the additional shift, if present:
829 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
830 unsigned Opc = SPU::ROTMAIr32_i32;
832 if (Op0.getOpcode() == ISD::SRL)
835 hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
843 } else if (Opc == ISD::SHL) {
844 if (OpVT == MVT::i64)
845 return SelectSHLi64(N, OpVT);
846 } else if (Opc == ISD::SRL) {
847 if (OpVT == MVT::i64)
848 return SelectSRLi64(N, OpVT);
849 } else if (Opc == ISD::SRA) {
850 if (OpVT == MVT::i64)
851 return SelectSRAi64(N, OpVT);
852 } else if (Opc == ISD::FNEG
853 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
854 DebugLoc dl = N->getDebugLoc();
855 // Check if the pattern is a special form of DFNMS:
856 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
857 SDValue Op0 = N->getOperand(0);
858 if (Op0.getOpcode() == ISD::FSUB) {
859 SDValue Op00 = Op0.getOperand(0);
860 if (Op00.getOpcode() == ISD::FMUL) {
861 unsigned Opc = SPU::DFNMSf64;
862 if (OpVT == MVT::v2f64)
863 Opc = SPU::DFNMSv2f64;
865 return CurDAG->getMachineNode(Opc, dl, OpVT,
872 SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
873 SDNode *signMask = 0;
874 unsigned Opc = SPU::XORfneg64;
876 if (OpVT == MVT::f64) {
877 signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
878 } else if (OpVT == MVT::v2f64) {
879 Opc = SPU::XORfnegvec;
880 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
882 negConst, negConst).getNode());
885 return CurDAG->getMachineNode(Opc, dl, OpVT,
886 N->getOperand(0), SDValue(signMask, 0));
887 } else if (Opc == ISD::FABS) {
888 if (OpVT == MVT::f64) {
889 SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
890 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
891 N->getOperand(0), SDValue(signMask, 0));
892 } else if (OpVT == MVT::v2f64) {
893 SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
894 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
896 SDNode *signMask = emitBuildVector(absVec.getNode());
897 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
898 N->getOperand(0), SDValue(signMask, 0));
900 } else if (Opc == SPUISD::LDRESULT) {
901 // Custom select instructions for LDRESULT
902 EVT VT = N->getValueType(0);
903 SDValue Arg = N->getOperand(0);
904 SDValue Chain = N->getOperand(1);
906 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
908 if (vtm->ldresult_ins == 0) {
909 report_fatal_error("LDRESULT for unsupported type: " +
910 Twine(VT.getEVTString()));
913 Opc = vtm->ldresult_ins;
914 if (vtm->ldresult_imm) {
915 SDValue Zero = CurDAG->getTargetConstant(0, VT);
917 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
919 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
923 } else if (Opc == SPUISD::IndirectAddr) {
924 // Look at the operands: SelectCode() will catch the cases that aren't
925 // specifically handled here.
927 // SPUInstrInfo catches the following patterns:
928 // (SPUindirect (SPUhi ...), (SPUlo ...))
929 // (SPUindirect $sp, imm)
930 EVT VT = N->getValueType(0);
931 SDValue Op0 = N->getOperand(0);
932 SDValue Op1 = N->getOperand(1);
935 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
936 || (Op0.getOpcode() == ISD::Register
937 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
938 && RN->getReg() != SPU::R1))) {
941 if (Op1.getOpcode() == ISD::Constant) {
942 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
943 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
944 if (isInt<10>(CN->getSExtValue())) {
948 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
961 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
963 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
965 return SelectCode(N);
969 * Emit the instruction sequence for i64 left shifts. The basic algorithm
970 * is to fill the bottom two word slots with zeros so that zeros are shifted
971 * in as the entire quadword is shifted left.
973 * \note This code could also be used to implement v2i64 shl.
975 * @param Op The shl operand
976 * @param OpVT Op's machine value value type (doesn't need to be passed, but
977 * makes life easier.)
978 * @return The SDNode with the entire instruction sequence
981 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
982 SDValue Op0 = N->getOperand(0);
983 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
984 OpVT, (128 / OpVT.getSizeInBits()));
985 SDValue ShiftAmt = N->getOperand(1);
986 EVT ShiftAmtVT = ShiftAmt.getValueType();
987 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
989 DebugLoc dl = N->getDebugLoc();
991 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
992 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
993 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
994 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
995 CurDAG->getTargetConstant(0, OpVT));
996 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
997 SDValue(ZeroFill, 0),
999 SDValue(SelMask, 0));
1001 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1002 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1003 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1007 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
1009 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1014 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
1015 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1016 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1020 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1022 CurDAG->getTargetConstant(3, ShiftAmtVT));
1024 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1026 CurDAG->getTargetConstant(7, ShiftAmtVT));
1028 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
1029 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1031 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
1032 SDValue(Shift, 0), SDValue(Bits, 0));
1035 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1039 * Emit the instruction sequence for i64 logical right shifts.
1041 * @param Op The shl operand
1042 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1043 * makes life easier.)
1044 * @return The SDNode with the entire instruction sequence
1047 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
1048 SDValue Op0 = N->getOperand(0);
1049 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1050 OpVT, (128 / OpVT.getSizeInBits()));
1051 SDValue ShiftAmt = N->getOperand(1);
1052 EVT ShiftAmtVT = ShiftAmt.getValueType();
1053 SDNode *VecOp0, *Shift = 0;
1054 DebugLoc dl = N->getDebugLoc();
1056 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1058 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1059 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1060 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1064 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1066 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1071 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1072 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1073 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1077 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1079 CurDAG->getTargetConstant(3, ShiftAmtVT));
1081 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1083 CurDAG->getTargetConstant(7, ShiftAmtVT));
1085 // Ensure that the shift amounts are negated!
1086 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1088 CurDAG->getTargetConstant(0, ShiftAmtVT));
1090 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1092 CurDAG->getTargetConstant(0, ShiftAmtVT));
1095 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1096 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1098 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1099 SDValue(Shift, 0), SDValue(Bits, 0));
1102 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1106 * Emit the instruction sequence for i64 arithmetic right shifts.
1108 * @param Op The shl operand
1109 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1110 * makes life easier.)
1111 * @return The SDNode with the entire instruction sequence
1114 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1115 // Promote Op0 to vector
1116 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1117 OpVT, (128 / OpVT.getSizeInBits()));
1118 SDValue ShiftAmt = N->getOperand(1);
1119 EVT ShiftAmtVT = ShiftAmt.getValueType();
1120 DebugLoc dl = N->getDebugLoc();
1123 CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0));
1125 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1127 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1128 SDValue(VecOp0, 0), SignRotAmt);
1129 SDNode *UpperHalfSign =
1130 CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1132 SDNode *UpperHalfSignMask =
1133 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1134 SDNode *UpperLowerMask =
1135 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1136 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1137 SDNode *UpperLowerSelect =
1138 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1139 SDValue(UpperHalfSignMask, 0),
1141 SDValue(UpperLowerMask, 0));
1145 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1146 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1147 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1152 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1153 SDValue(UpperLowerSelect, 0),
1154 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1160 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1161 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1162 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1166 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1167 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1170 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1171 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1173 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1174 SDValue(Shift, 0), SDValue(NegShift, 0));
1177 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1181 Do the necessary magic necessary to load a i64 constant
1183 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1185 ConstantSDNode *CN = cast<ConstantSDNode>(N);
1186 return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1189 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1191 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1193 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1195 // Here's where it gets interesting, because we have to parse out the
1196 // subtree handed back in i64vec:
1198 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1199 // The degenerate case where the upper and lower bits in the splat are
1201 SDValue Op0 = i64vec.getOperand(0);
1203 ReplaceUses(i64vec, Op0);
1204 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1205 SDValue(emitBuildVector(Op0.getNode()), 0));
1206 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1207 SDValue lhs = i64vec.getOperand(0);
1208 SDValue rhs = i64vec.getOperand(1);
1209 SDValue shufmask = i64vec.getOperand(2);
1211 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1212 ReplaceUses(lhs, lhs.getOperand(0));
1213 lhs = lhs.getOperand(0);
1216 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1218 : emitBuildVector(lhs.getNode()));
1220 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1221 ReplaceUses(rhs, rhs.getOperand(0));
1222 rhs = rhs.getOperand(0);
1225 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1227 : emitBuildVector(rhs.getNode()));
1229 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1230 ReplaceUses(shufmask, shufmask.getOperand(0));
1231 shufmask = shufmask.getOperand(0);
1234 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1235 ? shufmask.getNode()
1236 : emitBuildVector(shufmask.getNode()));
1239 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1240 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1241 SDValue(shufMaskNode, 0));
1242 HandleSDNode Dummy(shufNode);
1243 SDNode *SN = SelectCode(Dummy.getValue().getNode());
1244 if (SN == 0) SN = Dummy.getValue().getNode();
1246 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(SN, 0));
1247 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1248 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1249 SDValue(emitBuildVector(i64vec.getNode()), 0));
1251 report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1256 /// createSPUISelDag - This pass converts a legalized DAG into a
1257 /// SPU-specific DAG, ready for instruction scheduling.
1259 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1260 return new SPUDAGToDAGISel(TM);