1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSExtValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSExtValue());
54 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
56 isI32IntU10Immediate(ConstantSDNode *CN)
58 return isU10Constant(CN->getSExtValue());
61 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
63 isI16IntS10Immediate(ConstantSDNode *CN)
65 return isS10Constant(CN->getSExtValue());
68 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
70 isI16IntS10Immediate(SDNode *N)
72 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
73 return (CN != 0 && isI16IntS10Immediate(CN));
76 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
78 isI16IntU10Immediate(ConstantSDNode *CN)
80 return isU10Constant((short) CN->getZExtValue());
83 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
85 isI16IntU10Immediate(SDNode *N)
87 return (N->getOpcode() == ISD::Constant
88 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
91 //! ConstantSDNode predicate for signed 16-bit values
93 \arg CN The constant SelectionDAG node holding the value
94 \arg Imm The returned 16-bit value, if returning true
96 This predicate tests the value in \a CN to see whether it can be
97 represented as a 16-bit, sign-extended quantity. Returns true if
101 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
103 MVT vt = CN->getValueType(0);
104 Imm = (short) CN->getZExtValue();
105 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
107 } else if (vt == MVT::i32) {
108 int32_t i_val = (int32_t) CN->getZExtValue();
109 short s_val = (short) i_val;
110 return i_val == s_val;
112 int64_t i_val = (int64_t) CN->getZExtValue();
113 short s_val = (short) i_val;
114 return i_val == s_val;
120 //! SDNode predicate for signed 16-bit values.
122 isIntS16Immediate(SDNode *N, short &Imm)
124 return (N->getOpcode() == ISD::Constant
125 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
128 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
130 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
132 MVT vt = FPN->getValueType(0);
133 if (vt == MVT::f32) {
134 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
135 int sval = (int) ((val << 16) >> 16);
144 isHighLow(const SDValue &Op)
146 return (Op.getOpcode() == SPUISD::IndirectAddr
147 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
148 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
149 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
150 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
153 //===------------------------------------------------------------------===//
154 //! MVT to "useful stuff" mapping structure:
156 struct valtype_map_s {
158 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
159 bool ldresult_imm; /// LDRESULT instruction requires immediate?
160 unsigned lrinst; /// LR instruction
163 const valtype_map_s valtype_map[] = {
164 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
165 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
166 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
167 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
168 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
169 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
170 // vector types... (sigh!)
171 { MVT::v16i8, 0, false, SPU::LRv16i8 },
172 { MVT::v8i16, 0, false, SPU::LRv8i16 },
173 { MVT::v4i32, 0, false, SPU::LRv4i32 },
174 { MVT::v2i64, 0, false, SPU::LRv2i64 },
175 { MVT::v4f32, 0, false, SPU::LRv4f32 },
176 { MVT::v2f64, 0, false, SPU::LRv2f64 }
179 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
181 const valtype_map_s *getValueTypeMapEntry(MVT VT)
183 const valtype_map_s *retval = 0;
184 for (size_t i = 0; i < n_valtype_map; ++i) {
185 if (valtype_map[i].VT == VT) {
186 retval = valtype_map + i;
194 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
207 //===--------------------------------------------------------------------===//
208 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
209 /// instructions for SelectionDAG operations.
211 class SPUDAGToDAGISel :
212 public SelectionDAGISel
214 SPUTargetMachine &TM;
215 SPUTargetLowering &SPUtli;
216 unsigned GlobalBaseReg;
219 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
220 SelectionDAGISel(tm),
222 SPUtli(*tm.getTargetLowering())
225 virtual bool runOnFunction(Function &Fn) {
226 // Make sure we re-emit a set of the global base reg if necessary
228 SelectionDAGISel::runOnFunction(Fn);
232 /// getI32Imm - Return a target constant with the specified value, of type
234 inline SDValue getI32Imm(uint32_t Imm) {
235 return CurDAG->getTargetConstant(Imm, MVT::i32);
238 /// getI64Imm - Return a target constant with the specified value, of type
240 inline SDValue getI64Imm(uint64_t Imm) {
241 return CurDAG->getTargetConstant(Imm, MVT::i64);
244 /// getSmallIPtrImm - Return a target constant of pointer type.
245 inline SDValue getSmallIPtrImm(unsigned Imm) {
246 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
249 SDNode *emitBuildVector(SDValue build_vec) {
250 MVT vecVT = build_vec.getValueType();
251 SDNode *bvNode = build_vec.getNode();
253 // Check to see if this vector can be represented as a CellSPU immediate
254 // constant by invoking all of the instruction selection predicates:
255 if (((vecVT == MVT::v8i16) &&
256 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
257 ((vecVT == MVT::v4i32) &&
258 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
259 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
260 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
261 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
262 ((vecVT == MVT::v2i64) &&
263 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
264 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
265 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
266 return Select(build_vec);
268 // No, need to emit a constant pool spill:
269 std::vector<Constant*> CV;
271 for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
272 ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
273 CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
276 Constant *CP = ConstantVector::get(CV);
277 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
278 unsigned Alignment = 1 << cast<ConstantPoolSDNode > (CPIdx)->getAlignment();
279 SDValue CGPoolOffset =
280 SPU::LowerConstantPool(CPIdx, *CurDAG,
281 SPUtli.getSPUTargetMachine());
282 return SelectCode(CurDAG->getLoad(build_vec.getValueType(),
283 CurDAG->getEntryNode(), CGPoolOffset,
284 PseudoSourceValue::getConstantPool(), 0,
288 /// Select - Convert the specified operand from a target-independent to a
289 /// target-specific node if it hasn't already been changed.
290 SDNode *Select(SDValue Op);
292 //! Emit the instruction sequence for i64 shl
293 SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
295 //! Emit the instruction sequence for i64 srl
296 SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
298 //! Emit the instruction sequence for i64 sra
299 SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
301 //! Emit the necessary sequence for loading i64 constants:
302 SDNode *SelectI64Constant(SDValue &Op, MVT OpVT);
304 //! Returns true if the address N is an A-form (local store) address
305 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
308 //! D-form address predicate
309 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
312 /// Alternate D-form address using i7 offset predicate
313 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
316 /// D-form address selection workhorse
317 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
318 SDValue &Base, int minOffset, int maxOffset);
320 //! Address predicate if N can be expressed as an indexed [r+r] operation.
321 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
324 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
325 /// inline asm expressions.
326 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
328 std::vector<SDValue> &OutOps) {
330 switch (ConstraintCode) {
331 default: return true;
333 if (!SelectDFormAddr(Op, Op, Op0, Op1)
334 && !SelectAFormAddr(Op, Op, Op0, Op1))
335 SelectXFormAddr(Op, Op, Op0, Op1);
337 case 'o': // offsetable
338 if (!SelectDFormAddr(Op, Op, Op0, Op1)
339 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
341 Op1 = getSmallIPtrImm(0);
344 case 'v': // not offsetable
346 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
348 SelectAddrIdxOnly(Op, Op, Op0, Op1);
353 OutOps.push_back(Op0);
354 OutOps.push_back(Op1);
358 /// InstructionSelect - This callback is invoked by
359 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
360 virtual void InstructionSelect();
362 virtual const char *getPassName() const {
363 return "Cell SPU DAG->DAG Pattern Instruction Selection";
366 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
367 /// this target when scheduling the DAG.
368 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
369 const TargetInstrInfo *II = TM.getInstrInfo();
370 assert(II && "No InstrInfo?");
371 return new SPUHazardRecognizer(*II);
374 // Include the pieces autogenerated from the target description.
375 #include "SPUGenDAGISel.inc"
380 /// InstructionSelect - This callback is invoked by
381 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
383 SPUDAGToDAGISel::InstructionSelect()
387 // Select target instructions for the DAG.
389 CurDAG->RemoveDeadNodes();
393 \arg Op The ISD instruction operand
394 \arg N The address to be tested
395 \arg Base The base address
396 \arg Index The base address index
399 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
401 // These match the addr256k operand type:
402 MVT OffsVT = MVT::i16;
403 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
405 switch (N.getOpcode()) {
407 case ISD::ConstantPool:
408 case ISD::GlobalAddress:
409 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
413 case ISD::TargetConstant:
414 case ISD::TargetGlobalAddress:
415 case ISD::TargetJumpTable:
416 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
417 << "A-form address.\n";
421 case SPUISD::AFormAddr:
422 // Just load from memory if there's only a single use of the location,
423 // otherwise, this will get handled below with D-form offset addresses
425 SDValue Op0 = N.getOperand(0);
426 switch (Op0.getOpcode()) {
427 case ISD::TargetConstantPool:
428 case ISD::TargetJumpTable:
433 case ISD::TargetGlobalAddress: {
434 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
435 GlobalValue *GV = GSDN->getGlobal();
436 if (GV->getAlignment() == 16) {
451 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
453 const int minDForm2Offset = -(1 << 7);
454 const int maxDForm2Offset = (1 << 7) - 1;
455 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
460 \arg Op The ISD instruction (ignored)
461 \arg N The address to be tested
462 \arg Base Base address register/pointer
463 \arg Index Base address index
465 Examine the input address by a base register plus a signed 10-bit
466 displacement, [r+I10] (D-form address).
468 \return true if \a N is a D-form address with \a Base and \a Index set
469 to non-empty SDValue instances.
472 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
474 return DFormAddressPredicate(Op, N, Base, Index,
475 SPUFrameInfo::minFrameOffset(),
476 SPUFrameInfo::maxFrameOffset());
480 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
481 SDValue &Index, int minOffset,
483 unsigned Opc = N.getOpcode();
484 MVT PtrTy = SPUtli.getPointerTy();
486 if (Opc == ISD::FrameIndex) {
487 // Stack frame index must be less than 512 (divided by 16):
488 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
489 int FI = int(FIN->getIndex());
490 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
492 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
493 Base = CurDAG->getTargetConstant(0, PtrTy);
494 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
497 } else if (Opc == ISD::ADD) {
498 // Generated by getelementptr
499 const SDValue Op0 = N.getOperand(0);
500 const SDValue Op1 = N.getOperand(1);
502 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
503 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
504 Base = CurDAG->getTargetConstant(0, PtrTy);
507 } else if (Op1.getOpcode() == ISD::Constant
508 || Op1.getOpcode() == ISD::TargetConstant) {
509 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
510 int32_t offset = int32_t(CN->getSExtValue());
512 if (Op0.getOpcode() == ISD::FrameIndex) {
513 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
514 int FI = int(FIN->getIndex());
515 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
516 << " frame index = " << FI << "\n");
518 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
519 Base = CurDAG->getTargetConstant(offset, PtrTy);
520 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
523 } else if (offset > minOffset && offset < maxOffset) {
524 Base = CurDAG->getTargetConstant(offset, PtrTy);
528 } else if (Op0.getOpcode() == ISD::Constant
529 || Op0.getOpcode() == ISD::TargetConstant) {
530 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
531 int32_t offset = int32_t(CN->getSExtValue());
533 if (Op1.getOpcode() == ISD::FrameIndex) {
534 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
535 int FI = int(FIN->getIndex());
536 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
537 << " frame index = " << FI << "\n");
539 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
540 Base = CurDAG->getTargetConstant(offset, PtrTy);
541 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
544 } else if (offset > minOffset && offset < maxOffset) {
545 Base = CurDAG->getTargetConstant(offset, PtrTy);
550 } else if (Opc == SPUISD::IndirectAddr) {
551 // Indirect with constant offset -> D-Form address
552 const SDValue Op0 = N.getOperand(0);
553 const SDValue Op1 = N.getOperand(1);
555 if (Op0.getOpcode() == SPUISD::Hi
556 && Op1.getOpcode() == SPUISD::Lo) {
557 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
558 Base = CurDAG->getTargetConstant(0, PtrTy);
561 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
565 if (isa<ConstantSDNode>(Op1)) {
566 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
567 offset = int32_t(CN->getSExtValue());
569 } else if (isa<ConstantSDNode>(Op0)) {
570 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
571 offset = int32_t(CN->getSExtValue());
575 if (offset >= minOffset && offset <= maxOffset) {
576 Base = CurDAG->getTargetConstant(offset, PtrTy);
581 } else if (Opc == SPUISD::AFormAddr) {
582 Base = CurDAG->getTargetConstant(0, N.getValueType());
585 } else if (Opc == SPUISD::LDRESULT) {
586 Base = CurDAG->getTargetConstant(0, N.getValueType());
589 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
590 unsigned OpOpc = Op.getOpcode();
592 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
593 // Direct load/store without getelementptr
596 // Get the register from CopyFromReg
597 if (Opc == ISD::CopyFromReg)
598 Addr = N.getOperand(1);
600 Addr = N; // Register
602 Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
604 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
605 if (Offs.getOpcode() == ISD::UNDEF)
606 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
613 /* If otherwise unadorned, default to D-form address with 0 offset: */
614 if (Opc == ISD::CopyFromReg) {
615 Index = N.getOperand(1);
620 Base = CurDAG->getTargetConstant(0, Index.getValueType());
629 \arg Op The ISD instruction operand
630 \arg N The address operand
631 \arg Base The base pointer operand
632 \arg Index The offset/index operand
634 If the address \a N can be expressed as an A-form or D-form address, returns
635 false. Otherwise, creates two operands, Base and Index that will become the
636 (r)(r) X-form address.
639 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
641 if (!SelectAFormAddr(Op, N, Base, Index)
642 && !SelectDFormAddr(Op, N, Base, Index)) {
643 // If the address is neither A-form or D-form, punt and use an X-form
645 Base = N.getOperand(1);
646 Index = N.getOperand(0);
653 //! Convert the operand from a target-independent to a target-specific node
657 SPUDAGToDAGISel::Select(SDValue Op) {
658 SDNode *N = Op.getNode();
659 unsigned Opc = N->getOpcode();
662 MVT OpVT = Op.getValueType();
665 if (N->isMachineOpcode()) {
666 return NULL; // Already selected.
669 if (Opc == ISD::FrameIndex) {
670 int FI = cast<FrameIndexSDNode>(N)->getIndex();
671 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
672 SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
681 Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
682 Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(),
686 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
687 // Catch the i64 constants that end up here. Note: The backend doesn't
688 // attempt to legalize the constant (it's useless because DAGCombiner
689 // will insert 64-bit constants and we can't stop it).
690 return SelectI64Constant(Op, OpVT);
691 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
692 && OpVT == MVT::i64) {
693 SDValue Op0 = Op.getOperand(0);
694 MVT Op0VT = Op0.getValueType();
695 MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
696 MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
699 switch (Op0VT.getSimpleVT()) {
701 cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
706 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
707 CurDAG->getConstant(0x80808080, MVT::i32),
708 CurDAG->getConstant(0x00010203, MVT::i32),
709 CurDAG->getConstant(0x80808080, MVT::i32),
710 CurDAG->getConstant(0x08090a0b, MVT::i32));
714 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
715 CurDAG->getConstant(0x80808080, MVT::i32),
716 CurDAG->getConstant(0x80800203, MVT::i32),
717 CurDAG->getConstant(0x80808080, MVT::i32),
718 CurDAG->getConstant(0x80800a0b, MVT::i32));
722 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
723 CurDAG->getConstant(0x80808080, MVT::i32),
724 CurDAG->getConstant(0x80808003, MVT::i32),
725 CurDAG->getConstant(0x80808080, MVT::i32),
726 CurDAG->getConstant(0x8080800b, MVT::i32));
730 SDNode *shufMaskLoad = emitBuildVector(shufMask);
731 SDNode *PromoteScalar =
732 SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0));
734 SDValue zextShuffle =
735 CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
736 SDValue(PromoteScalar, 0),
737 SDValue(PromoteScalar, 0),
738 SDValue(shufMaskLoad, 0));
740 // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
741 // re-use it in the VEC2PREFSLOT selection without needing to explicitly
742 // call SelectCode (it's already done for us.)
743 SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle));
744 return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT,
746 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
748 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
750 return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
751 Op.getOperand(0), Op.getOperand(1),
752 SDValue(CGLoad, 0)));
753 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
755 emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
757 return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
758 Op.getOperand(0), Op.getOperand(1),
759 SDValue(CGLoad, 0)));
760 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
762 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
764 return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
765 Op.getOperand(0), Op.getOperand(1),
766 SDValue(CGLoad, 0)));
767 } else if (Opc == ISD::TRUNCATE) {
768 SDValue Op0 = Op.getOperand(0);
769 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
771 && Op0.getValueType() == MVT::i64) {
772 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
774 // Take advantage of the fact that the upper 32 bits are in the
775 // i32 preferred slot and avoid shuffle gymnastics:
776 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
778 unsigned shift_amt = unsigned(CN->getZExtValue());
780 if (shift_amt >= 32) {
782 CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0));
786 // Take care of the additional shift, if present:
787 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
788 unsigned Opc = SPU::ROTMAIr32_i32;
790 if (Op0.getOpcode() == ISD::SRL)
793 hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift);
800 } else if (Opc == ISD::SHL) {
801 if (OpVT == MVT::i64) {
802 return SelectSHLi64(Op, OpVT);
804 } else if (Opc == ISD::SRL) {
805 if (OpVT == MVT::i64) {
806 return SelectSRLi64(Op, OpVT);
808 } else if (Opc == ISD::SRA) {
809 if (OpVT == MVT::i64) {
810 return SelectSRAi64(Op, OpVT);
812 } else if (Opc == SPUISD::LDRESULT) {
813 // Custom select instructions for LDRESULT
814 MVT VT = N->getValueType(0);
815 SDValue Arg = N->getOperand(0);
816 SDValue Chain = N->getOperand(1);
818 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
820 if (vtm->ldresult_ins == 0) {
821 cerr << "LDRESULT for unsupported type: "
827 Opc = vtm->ldresult_ins;
828 if (vtm->ldresult_imm) {
829 SDValue Zero = CurDAG->getTargetConstant(0, VT);
831 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
833 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
837 } else if (Opc == SPUISD::IndirectAddr) {
838 // Look at the operands: SelectCode() will catch the cases that aren't
839 // specifically handled here.
841 // SPUInstrInfo catches the following patterns:
842 // (SPUindirect (SPUhi ...), (SPUlo ...))
843 // (SPUindirect $sp, imm)
844 MVT VT = Op.getValueType();
845 SDValue Op0 = N->getOperand(0);
846 SDValue Op1 = N->getOperand(1);
849 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
850 || (Op0.getOpcode() == ISD::Register
851 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
852 && RN->getReg() != SPU::R1))) {
854 if (Op1.getOpcode() == ISD::Constant) {
855 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
856 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
857 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
867 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
869 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
871 return SelectCode(Op);
875 * Emit the instruction sequence for i64 left shifts. The basic algorithm
876 * is to fill the bottom two word slots with zeros so that zeros are shifted
877 * in as the entire quadword is shifted left.
879 * \note This code could also be used to implement v2i64 shl.
881 * @param Op The shl operand
882 * @param OpVT Op's machine value value type (doesn't need to be passed, but
883 * makes life easier.)
884 * @return The SDNode with the entire instruction sequence
887 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
888 SDValue Op0 = Op.getOperand(0);
889 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
890 SDValue ShiftAmt = Op.getOperand(1);
891 MVT ShiftAmtVT = ShiftAmt.getValueType();
892 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
895 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
896 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
897 SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal);
898 ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT,
899 CurDAG->getTargetConstant(0, OpVT));
900 VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
901 SDValue(ZeroFill, 0),
903 SDValue(SelMask, 0));
905 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
906 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
907 unsigned bits = unsigned(CN->getZExtValue()) & 7;
911 CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT,
913 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
918 CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT,
919 SDValue((Shift != 0 ? Shift : VecOp0), 0),
920 CurDAG->getTargetConstant(bits, ShiftAmtVT));
924 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
926 CurDAG->getTargetConstant(3, ShiftAmtVT));
928 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
930 CurDAG->getTargetConstant(7, ShiftAmtVT));
932 CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT,
933 SDValue(VecOp0, 0), SDValue(Bytes, 0));
935 CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT,
936 SDValue(Shift, 0), SDValue(Bits, 0));
939 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
943 * Emit the instruction sequence for i64 logical right shifts.
945 * @param Op The shl operand
946 * @param OpVT Op's machine value value type (doesn't need to be passed, but
947 * makes life easier.)
948 * @return The SDNode with the entire instruction sequence
951 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
952 SDValue Op0 = Op.getOperand(0);
953 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
954 SDValue ShiftAmt = Op.getOperand(1);
955 MVT ShiftAmtVT = ShiftAmt.getValueType();
956 SDNode *VecOp0, *Shift = 0;
958 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
960 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
961 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
962 unsigned bits = unsigned(CN->getZExtValue()) & 7;
966 CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT,
968 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
973 CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT,
974 SDValue((Shift != 0 ? Shift : VecOp0), 0),
975 CurDAG->getTargetConstant(bits, ShiftAmtVT));
979 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
981 CurDAG->getTargetConstant(3, ShiftAmtVT));
983 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
985 CurDAG->getTargetConstant(7, ShiftAmtVT));
987 // Ensure that the shift amounts are negated!
988 Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
990 CurDAG->getTargetConstant(0, ShiftAmtVT));
992 Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
994 CurDAG->getTargetConstant(0, ShiftAmtVT));
997 CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT,
998 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1000 CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT,
1001 SDValue(Shift, 0), SDValue(Bits, 0));
1004 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
1008 * Emit the instruction sequence for i64 arithmetic right shifts.
1010 * @param Op The shl operand
1011 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1012 * makes life easier.)
1013 * @return The SDNode with the entire instruction sequence
1016 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
1017 // Promote Op0 to vector
1018 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1019 SDValue ShiftAmt = Op.getOperand(1);
1020 MVT ShiftAmtVT = ShiftAmt.getValueType();
1023 CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0));
1025 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1027 CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64,
1028 SDValue(VecOp0, 0), SignRotAmt);
1029 SDNode *UpperHalfSign =
1030 CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0));
1032 SDNode *UpperHalfSignMask =
1033 CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0));
1034 SDNode *UpperLowerMask =
1035 CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT,
1036 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1037 SDNode *UpperLowerSelect =
1038 CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
1039 SDValue(UpperHalfSignMask, 0),
1041 SDValue(UpperLowerMask, 0));
1045 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1046 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1047 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1052 CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT,
1053 SDValue(UpperLowerSelect, 0),
1054 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1060 CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT,
1061 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1062 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1066 CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
1067 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1070 CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT,
1071 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1073 CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT,
1074 SDValue(Shift, 0), SDValue(NegShift, 0));
1077 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
1081 Do the necessary magic necessary to load a i64 constant
1083 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) {
1084 ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
1085 MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
1087 SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue());
1089 // Here's where it gets interesting, because we have to parse out the
1090 // subtree handed back in i64vec:
1092 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1093 // The degenerate case where the upper and lower bits in the splat are
1095 SDValue Op0 = i64vec.getOperand(0);
1097 ReplaceUses(i64vec, Op0);
1098 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT,
1099 SDValue(emitBuildVector(Op0), 0));
1100 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1101 SDValue lhs = i64vec.getOperand(0);
1102 SDValue rhs = i64vec.getOperand(1);
1103 SDValue shufmask = i64vec.getOperand(2);
1105 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1106 ReplaceUses(lhs, lhs.getOperand(0));
1107 lhs = lhs.getOperand(0);
1110 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1112 : emitBuildVector(lhs));
1114 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1115 ReplaceUses(rhs, rhs.getOperand(0));
1116 rhs = rhs.getOperand(0);
1119 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1121 : emitBuildVector(rhs));
1123 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1124 ReplaceUses(shufmask, shufmask.getOperand(0));
1125 shufmask = shufmask.getOperand(0);
1128 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1129 ? shufmask.getNode()
1130 : emitBuildVector(shufmask));
1133 Select(CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
1134 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1135 SDValue(shufMaskNode, 0)));
1137 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(shufNode, 0));
1139 cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
1144 /// createSPUISelDag - This pass converts a legalized DAG into a
1145 /// SPU-specific DAG, ready for instruction scheduling.
1147 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1148 return new SPUDAGToDAGISel(TM);