1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
38 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
40 isI64IntS10Immediate(ConstantSDNode *CN)
42 return isS10Constant(CN->getSExtValue());
45 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
47 isI32IntS10Immediate(ConstantSDNode *CN)
49 return isS10Constant(CN->getSExtValue());
53 //! SDNode predicate for sign-extended, 10-bit immediate values
55 isI32IntS10Immediate(SDNode *N)
57 return (N->getOpcode() == ISD::Constant
58 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
62 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
64 isI32IntU10Immediate(ConstantSDNode *CN)
66 return isU10Constant(CN->getSExtValue());
69 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
71 isI16IntS10Immediate(ConstantSDNode *CN)
73 return isS10Constant(CN->getSExtValue());
76 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
78 isI16IntS10Immediate(SDNode *N)
80 return (N->getOpcode() == ISD::Constant
81 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
84 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
86 isI16IntU10Immediate(ConstantSDNode *CN)
88 return isU10Constant((short) CN->getZExtValue());
91 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
93 isI16IntU10Immediate(SDNode *N)
95 return (N->getOpcode() == ISD::Constant
96 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
99 //! ConstantSDNode predicate for signed 16-bit values
101 \arg CN The constant SelectionDAG node holding the value
102 \arg Imm The returned 16-bit value, if returning true
104 This predicate tests the value in \a CN to see whether it can be
105 represented as a 16-bit, sign-extended quantity. Returns true if
109 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
111 MVT vt = CN->getValueType(0);
112 Imm = (short) CN->getZExtValue();
113 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
115 } else if (vt == MVT::i32) {
116 int32_t i_val = (int32_t) CN->getZExtValue();
117 short s_val = (short) i_val;
118 return i_val == s_val;
120 int64_t i_val = (int64_t) CN->getZExtValue();
121 short s_val = (short) i_val;
122 return i_val == s_val;
128 //! SDNode predicate for signed 16-bit values.
130 isIntS16Immediate(SDNode *N, short &Imm)
132 return (N->getOpcode() == ISD::Constant
133 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
136 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
138 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
140 MVT vt = FPN->getValueType(0);
141 if (vt == MVT::f32) {
142 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
143 int sval = (int) ((val << 16) >> 16);
152 isHighLow(const SDValue &Op)
154 return (Op.getOpcode() == SPUISD::IndirectAddr
155 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
156 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
157 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
158 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
161 //===------------------------------------------------------------------===//
162 //! MVT to "useful stuff" mapping structure:
164 struct valtype_map_s {
166 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
167 bool ldresult_imm; /// LDRESULT instruction requires immediate?
168 int prefslot_byte; /// Byte offset of the "preferred" slot
171 const valtype_map_s valtype_map[] = {
172 { MVT::i1, 0, false, 3 },
173 { MVT::i8, SPU::ORBIr8, true, 3 },
174 { MVT::i16, SPU::ORHIr16, true, 2 },
175 { MVT::i32, SPU::ORIr32, true, 0 },
176 { MVT::i64, SPU::ORr64, false, 0 },
177 { MVT::f32, SPU::ORf32, false, 0 },
178 { MVT::f64, SPU::ORf64, false, 0 },
179 // vector types... (sigh!)
180 { MVT::v16i8, 0, false, 0 },
181 { MVT::v8i16, 0, false, 0 },
182 { MVT::v4i32, 0, false, 0 },
183 { MVT::v2i64, 0, false, 0 },
184 { MVT::v4f32, 0, false, 0 },
185 { MVT::v2f64, 0, false, 0 }
188 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
190 const valtype_map_s *getValueTypeMapEntry(MVT VT)
192 const valtype_map_s *retval = 0;
193 for (size_t i = 0; i < n_valtype_map; ++i) {
194 if (valtype_map[i].VT == VT) {
195 retval = valtype_map + i;
203 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
216 //===--------------------------------------------------------------------===//
217 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
218 /// instructions for SelectionDAG operations.
220 class SPUDAGToDAGISel :
221 public SelectionDAGISel
223 SPUTargetMachine &TM;
224 SPUTargetLowering &SPUtli;
225 unsigned GlobalBaseReg;
228 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
229 SelectionDAGISel(*tm.getTargetLowering()),
231 SPUtli(*tm.getTargetLowering())
234 virtual bool runOnFunction(Function &Fn) {
235 // Make sure we re-emit a set of the global base reg if necessary
237 SelectionDAGISel::runOnFunction(Fn);
241 /// getI32Imm - Return a target constant with the specified value, of type
243 inline SDValue getI32Imm(uint32_t Imm) {
244 return CurDAG->getTargetConstant(Imm, MVT::i32);
247 /// getI64Imm - Return a target constant with the specified value, of type
249 inline SDValue getI64Imm(uint64_t Imm) {
250 return CurDAG->getTargetConstant(Imm, MVT::i64);
253 /// getSmallIPtrImm - Return a target constant of pointer type.
254 inline SDValue getSmallIPtrImm(unsigned Imm) {
255 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
258 /// Select - Convert the specified operand from a target-independent to a
259 /// target-specific node if it hasn't already been changed.
260 SDNode *Select(SDValue Op);
262 //! Returns true if the address N is an A-form (local store) address
263 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
266 //! D-form address predicate
267 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
270 /// Alternate D-form address using i7 offset predicate
271 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
274 /// D-form address selection workhorse
275 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
276 SDValue &Base, int minOffset, int maxOffset);
278 //! Address predicate if N can be expressed as an indexed [r+r] operation.
279 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
282 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
283 /// inline asm expressions.
284 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
286 std::vector<SDValue> &OutOps) {
288 switch (ConstraintCode) {
289 default: return true;
291 if (!SelectDFormAddr(Op, Op, Op0, Op1)
292 && !SelectAFormAddr(Op, Op, Op0, Op1))
293 SelectXFormAddr(Op, Op, Op0, Op1);
295 case 'o': // offsetable
296 if (!SelectDFormAddr(Op, Op, Op0, Op1)
297 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
299 Op1 = getSmallIPtrImm(0);
302 case 'v': // not offsetable
304 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
306 SelectAddrIdxOnly(Op, Op, Op0, Op1);
311 OutOps.push_back(Op0);
312 OutOps.push_back(Op1);
316 /// InstructionSelect - This callback is invoked by
317 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
318 virtual void InstructionSelect();
320 virtual const char *getPassName() const {
321 return "Cell SPU DAG->DAG Pattern Instruction Selection";
324 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
325 /// this target when scheduling the DAG.
326 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
327 const TargetInstrInfo *II = TM.getInstrInfo();
328 assert(II && "No InstrInfo?");
329 return new SPUHazardRecognizer(*II);
332 // Include the pieces autogenerated from the target description.
333 #include "SPUGenDAGISel.inc"
338 /// InstructionSelect - This callback is invoked by
339 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
341 SPUDAGToDAGISel::InstructionSelect()
345 // Select target instructions for the DAG.
347 CurDAG->RemoveDeadNodes();
351 \arg Op The ISD instructio operand
352 \arg N The address to be tested
353 \arg Base The base address
354 \arg Index The base address index
357 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
359 // These match the addr256k operand type:
360 MVT OffsVT = MVT::i16;
361 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
363 switch (N.getOpcode()) {
365 case ISD::ConstantPool:
366 case ISD::GlobalAddress:
367 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
371 case ISD::TargetConstant:
372 case ISD::TargetGlobalAddress:
373 case ISD::TargetJumpTable:
374 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
375 << "A-form address.\n";
379 case SPUISD::AFormAddr:
380 // Just load from memory if there's only a single use of the location,
381 // otherwise, this will get handled below with D-form offset addresses
383 SDValue Op0 = N.getOperand(0);
384 switch (Op0.getOpcode()) {
385 case ISD::TargetConstantPool:
386 case ISD::TargetJumpTable:
391 case ISD::TargetGlobalAddress: {
392 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
393 GlobalValue *GV = GSDN->getGlobal();
394 if (GV->getAlignment() == 16) {
409 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
411 const int minDForm2Offset = -(1 << 7);
412 const int maxDForm2Offset = (1 << 7) - 1;
413 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
418 \arg Op The ISD instruction (ignored)
419 \arg N The address to be tested
420 \arg Base Base address register/pointer
421 \arg Index Base address index
423 Examine the input address by a base register plus a signed 10-bit
424 displacement, [r+I10] (D-form address).
426 \return true if \a N is a D-form address with \a Base and \a Index set
427 to non-empty SDValue instances.
430 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
432 return DFormAddressPredicate(Op, N, Base, Index,
433 SPUFrameInfo::minFrameOffset(),
434 SPUFrameInfo::maxFrameOffset());
438 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
439 SDValue &Index, int minOffset,
441 unsigned Opc = N.getOpcode();
442 MVT PtrTy = SPUtli.getPointerTy();
444 if (Opc == ISD::FrameIndex) {
445 // Stack frame index must be less than 512 (divided by 16):
446 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
447 int FI = int(FIN->getIndex());
448 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
450 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
451 Base = CurDAG->getTargetConstant(0, PtrTy);
452 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
455 } else if (Opc == ISD::ADD) {
456 // Generated by getelementptr
457 const SDValue Op0 = N.getOperand(0);
458 const SDValue Op1 = N.getOperand(1);
460 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
461 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
462 Base = CurDAG->getTargetConstant(0, PtrTy);
465 } else if (Op1.getOpcode() == ISD::Constant
466 || Op1.getOpcode() == ISD::TargetConstant) {
467 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
468 int32_t offset = int32_t(CN->getSExtValue());
470 if (Op0.getOpcode() == ISD::FrameIndex) {
471 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
472 int FI = int(FIN->getIndex());
473 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
474 << " frame index = " << FI << "\n");
476 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
477 Base = CurDAG->getTargetConstant(offset, PtrTy);
478 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
481 } else if (offset > minOffset && offset < maxOffset) {
482 Base = CurDAG->getTargetConstant(offset, PtrTy);
486 } else if (Op0.getOpcode() == ISD::Constant
487 || Op0.getOpcode() == ISD::TargetConstant) {
488 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
489 int32_t offset = int32_t(CN->getSExtValue());
491 if (Op1.getOpcode() == ISD::FrameIndex) {
492 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
493 int FI = int(FIN->getIndex());
494 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
495 << " frame index = " << FI << "\n");
497 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
498 Base = CurDAG->getTargetConstant(offset, PtrTy);
499 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
502 } else if (offset > minOffset && offset < maxOffset) {
503 Base = CurDAG->getTargetConstant(offset, PtrTy);
508 } else if (Opc == SPUISD::IndirectAddr) {
509 // Indirect with constant offset -> D-Form address
510 const SDValue Op0 = N.getOperand(0);
511 const SDValue Op1 = N.getOperand(1);
513 if (Op0.getOpcode() == SPUISD::Hi
514 && Op1.getOpcode() == SPUISD::Lo) {
515 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
516 Base = CurDAG->getTargetConstant(0, PtrTy);
519 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
523 if (isa<ConstantSDNode>(Op1)) {
524 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
525 offset = int32_t(CN->getSExtValue());
527 } else if (isa<ConstantSDNode>(Op0)) {
528 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
529 offset = int32_t(CN->getSExtValue());
533 if (offset >= minOffset && offset <= maxOffset) {
534 Base = CurDAG->getTargetConstant(offset, PtrTy);
539 } else if (Opc == SPUISD::AFormAddr) {
540 Base = CurDAG->getTargetConstant(0, N.getValueType());
543 } else if (Opc == SPUISD::LDRESULT) {
544 Base = CurDAG->getTargetConstant(0, N.getValueType());
547 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
548 unsigned OpOpc = Op.getOpcode();
550 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
551 // Direct load/store without getelementptr
554 // Get the register from CopyFromReg
555 if (Opc == ISD::CopyFromReg)
556 Addr = N.getOperand(1);
558 Addr = N; // Register
560 if (OpOpc == ISD::STORE)
561 Offs = Op.getOperand(3);
563 Offs = Op.getOperand(2); // LOAD
565 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
566 if (Offs.getOpcode() == ISD::UNDEF)
567 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
580 \arg Op The ISD instruction operand
581 \arg N The address operand
582 \arg Base The base pointer operand
583 \arg Index The offset/index operand
585 If the address \a N can be expressed as an A-form or D-form address, returns
586 false. Otherwise, creates two operands, Base and Index that will become the
587 (r)(r) X-form address.
590 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
592 if (!SelectAFormAddr(Op, N, Base, Index)
593 && !SelectDFormAddr(Op, N, Base, Index)) {
594 // If the address is neither A-form or D-form, punt and use an X-form
596 Base = N.getOperand(0);
597 Index = N.getOperand(1);
604 //! Convert the operand from a target-independent to a target-specific node
608 SPUDAGToDAGISel::Select(SDValue Op) {
609 SDNode *N = Op.getNode();
610 unsigned Opc = N->getOpcode();
613 MVT OpVT = Op.getValueType();
616 if (N->isMachineOpcode()) {
617 return NULL; // Already selected.
618 } else if (Opc == ISD::FrameIndex) {
619 // Selects to (add $sp, FI * stackSlotSize)
621 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
622 MVT PtrVT = SPUtli.getPointerTy();
624 // Adjust stack slot to actual offset in frame:
625 if (isS10Constant(FI)) {
626 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
630 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
631 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
634 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
638 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
639 Ops[1] = CurDAG->getConstant(FI, PtrVT);
642 } else if (Opc == ISD::ZERO_EXTEND) {
643 // (zero_extend:i16 (and:i8 <arg>, <const>))
644 const SDValue &Op1 = N->getOperand(0);
646 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
647 if (Op1.getOpcode() == ISD::AND) {
648 // Fold this into a single ANDHI. This is often seen in expansions of i1
649 // to i8, then i8 to i16 in logical/branching operations.
650 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
651 "<arg>, <const>))\n");
652 NewOpc = SPU::ANDHIi8i16;
653 Ops[0] = Op1.getOperand(0);
654 Ops[1] = Op1.getOperand(1);
658 } else if (Opc == SPUISD::LDRESULT) {
659 // Custom select instructions for LDRESULT
660 MVT VT = N->getValueType(0);
661 SDValue Arg = N->getOperand(0);
662 SDValue Chain = N->getOperand(1);
664 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
666 if (vtm->ldresult_ins == 0) {
667 cerr << "LDRESULT for unsupported type: "
673 Opc = vtm->ldresult_ins;
674 if (vtm->ldresult_imm) {
675 SDValue Zero = CurDAG->getTargetConstant(0, VT);
677 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
679 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
682 Chain = SDValue(Result, 1);
685 } else if (Opc == SPUISD::IndirectAddr) {
686 SDValue Op0 = Op.getOperand(0);
687 if (Op0.getOpcode() == SPUISD::LDRESULT) {
688 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
689 // (IndirectAddr (LDRESULT, imm))
690 SDValue Op1 = Op.getOperand(1);
691 MVT VT = Op.getValueType();
693 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
694 DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
695 DEBUG(cerr << "\nOp1 = ");
696 DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
699 if (Op1.getOpcode() == ISD::Constant) {
700 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
701 Op1 = CurDAG->getTargetConstant(CN->getZExtValue(), VT);
702 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
712 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
714 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
716 return SelectCode(Op);
719 /// createPPCISelDag - This pass converts a legalized DAG into a
720 /// SPU-specific DAG, ready for instruction scheduling.
722 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
723 return new SPUDAGToDAGISel(TM);