1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSExtValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSExtValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant(CN->getSExtValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant(CN->getSExtValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getZExtValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT vt = CN->getValueType(0);
114 Imm = (short) CN->getZExtValue();
115 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getZExtValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getZExtValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDValue &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 bool ldresult_imm; /// LDRESULT instruction requires immediate?
170 unsigned lrinst; /// LR instruction
173 const valtype_map_s valtype_map[] = {
174 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
175 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
176 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
177 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
178 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
179 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
180 // vector types... (sigh!)
181 { MVT::v16i8, 0, false, SPU::LRv16i8 },
182 { MVT::v8i16, 0, false, SPU::LRv8i16 },
183 { MVT::v4i32, 0, false, SPU::LRv4i32 },
184 { MVT::v2i64, 0, false, SPU::LRv2i64 },
185 { MVT::v4f32, 0, false, SPU::LRv4f32 },
186 { MVT::v2f64, 0, false, SPU::LRv2f64 }
189 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
191 const valtype_map_s *getValueTypeMapEntry(MVT VT)
193 const valtype_map_s *retval = 0;
194 for (size_t i = 0; i < n_valtype_map; ++i) {
195 if (valtype_map[i].VT == VT) {
196 retval = valtype_map + i;
204 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
217 //===--------------------------------------------------------------------===//
218 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
219 /// instructions for SelectionDAG operations.
221 class SPUDAGToDAGISel :
222 public SelectionDAGISel
224 SPUTargetMachine &TM;
225 SPUTargetLowering &SPUtli;
226 unsigned GlobalBaseReg;
229 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
230 SelectionDAGISel(tm),
232 SPUtli(*tm.getTargetLowering())
235 virtual bool runOnFunction(Function &Fn) {
236 // Make sure we re-emit a set of the global base reg if necessary
238 SelectionDAGISel::runOnFunction(Fn);
242 /// getI32Imm - Return a target constant with the specified value, of type
244 inline SDValue getI32Imm(uint32_t Imm) {
245 return CurDAG->getTargetConstant(Imm, MVT::i32);
248 /// getI64Imm - Return a target constant with the specified value, of type
250 inline SDValue getI64Imm(uint64_t Imm) {
251 return CurDAG->getTargetConstant(Imm, MVT::i64);
254 /// getSmallIPtrImm - Return a target constant of pointer type.
255 inline SDValue getSmallIPtrImm(unsigned Imm) {
256 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
259 SDNode *emitBuildVector(SDValue build_vec) {
260 MVT vecVT = build_vec.getValueType();
261 SDNode *bvNode = build_vec.getNode();
262 bool canBeSelected = false;
264 // Check to see if this vector can be represented as a CellSPU immediate
266 if (vecVT == MVT::v8i16) {
267 if (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0) {
268 canBeSelected = true;
270 } else if (vecVT == MVT::v4i32) {
271 if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
272 || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
273 || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0)
274 || (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0)) {
275 canBeSelected = true;
277 } else if (vecVT == MVT::v2i64) {
278 if ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)
279 || (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)
280 || (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)) {
281 canBeSelected = true;
286 return Select(build_vec);
289 // No, need to emit a constant pool spill:
290 std::vector<Constant*> CV;
292 for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
293 ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
294 CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
297 Constant *CP = ConstantVector::get(CV);
298 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
299 unsigned Alignment = 1 << cast<ConstantPoolSDNode > (CPIdx)->getAlignment();
300 SDValue CGPoolOffset =
301 SPU::LowerConstantPool(CPIdx, *CurDAG,
302 SPUtli.getSPUTargetMachine());
303 return SelectCode(CurDAG->getLoad(build_vec.getValueType(),
304 CurDAG->getEntryNode(), CGPoolOffset,
305 PseudoSourceValue::getConstantPool(), 0,
309 /// Select - Convert the specified operand from a target-independent to a
310 /// target-specific node if it hasn't already been changed.
311 SDNode *Select(SDValue Op);
313 //! Emit the instruction sequence for i64 shl
314 SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
316 //! Emit the instruction sequence for i64 srl
317 SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
319 //! Emit the instruction sequence for i64 sra
320 SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
322 //! Emit the necessary sequence for loading i64 constants:
323 SDNode *SelectI64Constant(SDValue &Op, MVT OpVT);
325 //! Returns true if the address N is an A-form (local store) address
326 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
329 //! D-form address predicate
330 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
333 /// Alternate D-form address using i7 offset predicate
334 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
337 /// D-form address selection workhorse
338 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
339 SDValue &Base, int minOffset, int maxOffset);
341 //! Address predicate if N can be expressed as an indexed [r+r] operation.
342 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
345 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
346 /// inline asm expressions.
347 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
349 std::vector<SDValue> &OutOps) {
351 switch (ConstraintCode) {
352 default: return true;
354 if (!SelectDFormAddr(Op, Op, Op0, Op1)
355 && !SelectAFormAddr(Op, Op, Op0, Op1))
356 SelectXFormAddr(Op, Op, Op0, Op1);
358 case 'o': // offsetable
359 if (!SelectDFormAddr(Op, Op, Op0, Op1)
360 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
362 Op1 = getSmallIPtrImm(0);
365 case 'v': // not offsetable
367 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
369 SelectAddrIdxOnly(Op, Op, Op0, Op1);
374 OutOps.push_back(Op0);
375 OutOps.push_back(Op1);
379 /// InstructionSelect - This callback is invoked by
380 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
381 virtual void InstructionSelect();
383 virtual const char *getPassName() const {
384 return "Cell SPU DAG->DAG Pattern Instruction Selection";
387 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
388 /// this target when scheduling the DAG.
389 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
390 const TargetInstrInfo *II = TM.getInstrInfo();
391 assert(II && "No InstrInfo?");
392 return new SPUHazardRecognizer(*II);
395 // Include the pieces autogenerated from the target description.
396 #include "SPUGenDAGISel.inc"
401 /// InstructionSelect - This callback is invoked by
402 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
404 SPUDAGToDAGISel::InstructionSelect()
408 // Select target instructions for the DAG.
410 CurDAG->RemoveDeadNodes();
414 \arg Op The ISD instructio operand
415 \arg N The address to be tested
416 \arg Base The base address
417 \arg Index The base address index
420 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
422 // These match the addr256k operand type:
423 MVT OffsVT = MVT::i16;
424 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
426 switch (N.getOpcode()) {
428 case ISD::ConstantPool:
429 case ISD::GlobalAddress:
430 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
434 case ISD::TargetConstant:
435 case ISD::TargetGlobalAddress:
436 case ISD::TargetJumpTable:
437 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
438 << "A-form address.\n";
442 case SPUISD::AFormAddr:
443 // Just load from memory if there's only a single use of the location,
444 // otherwise, this will get handled below with D-form offset addresses
446 SDValue Op0 = N.getOperand(0);
447 switch (Op0.getOpcode()) {
448 case ISD::TargetConstantPool:
449 case ISD::TargetJumpTable:
454 case ISD::TargetGlobalAddress: {
455 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
456 GlobalValue *GV = GSDN->getGlobal();
457 if (GV->getAlignment() == 16) {
472 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
474 const int minDForm2Offset = -(1 << 7);
475 const int maxDForm2Offset = (1 << 7) - 1;
476 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
481 \arg Op The ISD instruction (ignored)
482 \arg N The address to be tested
483 \arg Base Base address register/pointer
484 \arg Index Base address index
486 Examine the input address by a base register plus a signed 10-bit
487 displacement, [r+I10] (D-form address).
489 \return true if \a N is a D-form address with \a Base and \a Index set
490 to non-empty SDValue instances.
493 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
495 return DFormAddressPredicate(Op, N, Base, Index,
496 SPUFrameInfo::minFrameOffset(),
497 SPUFrameInfo::maxFrameOffset());
501 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
502 SDValue &Index, int minOffset,
504 unsigned Opc = N.getOpcode();
505 MVT PtrTy = SPUtli.getPointerTy();
507 if (Opc == ISD::FrameIndex) {
508 // Stack frame index must be less than 512 (divided by 16):
509 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
510 int FI = int(FIN->getIndex());
511 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
513 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
514 Base = CurDAG->getTargetConstant(0, PtrTy);
515 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
518 } else if (Opc == ISD::ADD) {
519 // Generated by getelementptr
520 const SDValue Op0 = N.getOperand(0);
521 const SDValue Op1 = N.getOperand(1);
523 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
524 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
525 Base = CurDAG->getTargetConstant(0, PtrTy);
528 } else if (Op1.getOpcode() == ISD::Constant
529 || Op1.getOpcode() == ISD::TargetConstant) {
530 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
531 int32_t offset = int32_t(CN->getSExtValue());
533 if (Op0.getOpcode() == ISD::FrameIndex) {
534 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
535 int FI = int(FIN->getIndex());
536 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
537 << " frame index = " << FI << "\n");
539 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
540 Base = CurDAG->getTargetConstant(offset, PtrTy);
541 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
544 } else if (offset > minOffset && offset < maxOffset) {
545 Base = CurDAG->getTargetConstant(offset, PtrTy);
549 } else if (Op0.getOpcode() == ISD::Constant
550 || Op0.getOpcode() == ISD::TargetConstant) {
551 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
552 int32_t offset = int32_t(CN->getSExtValue());
554 if (Op1.getOpcode() == ISD::FrameIndex) {
555 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
556 int FI = int(FIN->getIndex());
557 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
558 << " frame index = " << FI << "\n");
560 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
561 Base = CurDAG->getTargetConstant(offset, PtrTy);
562 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
565 } else if (offset > minOffset && offset < maxOffset) {
566 Base = CurDAG->getTargetConstant(offset, PtrTy);
571 } else if (Opc == SPUISD::IndirectAddr) {
572 // Indirect with constant offset -> D-Form address
573 const SDValue Op0 = N.getOperand(0);
574 const SDValue Op1 = N.getOperand(1);
576 if (Op0.getOpcode() == SPUISD::Hi
577 && Op1.getOpcode() == SPUISD::Lo) {
578 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
579 Base = CurDAG->getTargetConstant(0, PtrTy);
582 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
586 if (isa<ConstantSDNode>(Op1)) {
587 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
588 offset = int32_t(CN->getSExtValue());
590 } else if (isa<ConstantSDNode>(Op0)) {
591 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
592 offset = int32_t(CN->getSExtValue());
596 if (offset >= minOffset && offset <= maxOffset) {
597 Base = CurDAG->getTargetConstant(offset, PtrTy);
602 } else if (Opc == SPUISD::AFormAddr) {
603 Base = CurDAG->getTargetConstant(0, N.getValueType());
606 } else if (Opc == SPUISD::LDRESULT) {
607 Base = CurDAG->getTargetConstant(0, N.getValueType());
610 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
611 unsigned OpOpc = Op.getOpcode();
613 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
614 // Direct load/store without getelementptr
617 // Get the register from CopyFromReg
618 if (Opc == ISD::CopyFromReg)
619 Addr = N.getOperand(1);
621 Addr = N; // Register
623 Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
625 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
626 if (Offs.getOpcode() == ISD::UNDEF)
627 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
634 /* If otherwise unadorned, default to D-form address with 0 offset: */
635 if (Opc == ISD::CopyFromReg) {
636 Index = N.getOperand(1);
641 Base = CurDAG->getTargetConstant(0, Index.getValueType());
650 \arg Op The ISD instruction operand
651 \arg N The address operand
652 \arg Base The base pointer operand
653 \arg Index The offset/index operand
655 If the address \a N can be expressed as an A-form or D-form address, returns
656 false. Otherwise, creates two operands, Base and Index that will become the
657 (r)(r) X-form address.
660 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
662 if (!SelectAFormAddr(Op, N, Base, Index)
663 && !SelectDFormAddr(Op, N, Base, Index)) {
664 // If the address is neither A-form or D-form, punt and use an X-form
666 Base = N.getOperand(1);
667 Index = N.getOperand(0);
674 //! Convert the operand from a target-independent to a target-specific node
678 SPUDAGToDAGISel::Select(SDValue Op) {
679 SDNode *N = Op.getNode();
680 unsigned Opc = N->getOpcode();
683 MVT OpVT = Op.getValueType();
686 if (N->isMachineOpcode()) {
687 return NULL; // Already selected.
690 if (Opc == ISD::FrameIndex) {
691 int FI = cast<FrameIndexSDNode>(N)->getIndex();
692 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
693 SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
702 Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
703 Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(),
707 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
708 // Catch the i64 constants that end up here. Note: The backend doesn't
709 // attempt to legalize the constant (it's useless because DAGCombiner
710 // will insert 64-bit constants and we can't stop it).
711 return SelectI64Constant(Op, OpVT);
712 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
713 && OpVT == MVT::i64) {
714 SDValue Op0 = Op.getOperand(0);
715 MVT Op0VT = Op0.getValueType();
716 MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
717 MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
720 switch (Op0VT.getSimpleVT()) {
722 cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
727 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
728 CurDAG->getConstant(0x80808080, MVT::i32),
729 CurDAG->getConstant(0x00010203, MVT::i32),
730 CurDAG->getConstant(0x80808080, MVT::i32),
731 CurDAG->getConstant(0x08090a0b, MVT::i32));
735 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
736 CurDAG->getConstant(0x80808080, MVT::i32),
737 CurDAG->getConstant(0x80800203, MVT::i32),
738 CurDAG->getConstant(0x80808080, MVT::i32),
739 CurDAG->getConstant(0x80800a0b, MVT::i32));
743 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
744 CurDAG->getConstant(0x80808080, MVT::i32),
745 CurDAG->getConstant(0x80808003, MVT::i32),
746 CurDAG->getConstant(0x80808080, MVT::i32),
747 CurDAG->getConstant(0x8080800b, MVT::i32));
751 SDNode *shufMaskLoad = emitBuildVector(shufMask);
752 SDNode *PromoteScalar =
753 SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0));
755 SDValue zextShuffle =
756 CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
757 SDValue(PromoteScalar, 0),
758 SDValue(PromoteScalar, 0),
759 SDValue(shufMaskLoad, 0));
761 // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
762 // re-use it in the VEC2PREFSLOT selection without needing to explicitly
763 // call SelectCode (it's already done for us.)
764 SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle));
765 return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT,
767 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
769 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
771 return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
772 Op.getOperand(0), Op.getOperand(1),
773 SDValue(CGLoad, 0)));
774 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
776 emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
778 return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
779 Op.getOperand(0), Op.getOperand(1),
780 SDValue(CGLoad, 0)));
781 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
783 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
785 return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
786 Op.getOperand(0), Op.getOperand(1),
787 SDValue(CGLoad, 0)));
788 } else if (Opc == ISD::TRUNCATE) {
789 SDValue Op0 = Op.getOperand(0);
790 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
792 && Op0.getValueType() == MVT::i64) {
793 // Catch the (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32 to
794 // take advantage of the fact that the upper 32 bits are in the
795 // i32 preferred slot and avoid all kinds of other shuffle gymnastics:
796 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
798 unsigned shift_amt = unsigned(CN->getZExtValue());
800 if (shift_amt >= 32) {
802 CurDAG->getTargetNode(SPU::ORr32_r64, OpVT, Op0.getOperand(0));
806 // Take care of the additional shift, if present:
807 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
808 unsigned Opc = SPU::ROTMAIr32_i32;
810 if (Op0.getOpcode() == ISD::SRL)
813 hi32 = CurDAG->getTargetNode(Opc, OpVT, SDValue(hi32, 0), shift);
820 } else if (Opc == ISD::SHL) {
821 if (OpVT == MVT::i64) {
822 return SelectSHLi64(Op, OpVT);
824 } else if (Opc == ISD::SRL) {
825 if (OpVT == MVT::i64) {
826 return SelectSRLi64(Op, OpVT);
828 } else if (Opc == ISD::SRA) {
829 if (OpVT == MVT::i64) {
830 return SelectSRAi64(Op, OpVT);
832 } else if (Opc == SPUISD::LDRESULT) {
833 // Custom select instructions for LDRESULT
834 MVT VT = N->getValueType(0);
835 SDValue Arg = N->getOperand(0);
836 SDValue Chain = N->getOperand(1);
838 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
840 if (vtm->ldresult_ins == 0) {
841 cerr << "LDRESULT for unsupported type: "
847 Opc = vtm->ldresult_ins;
848 if (vtm->ldresult_imm) {
849 SDValue Zero = CurDAG->getTargetConstant(0, VT);
851 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
853 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
857 } else if (Opc == SPUISD::IndirectAddr) {
858 // Look at the operands: SelectCode() will catch the cases that aren't
859 // specifically handled here.
861 // SPUInstrInfo catches the following patterns:
862 // (SPUindirect (SPUhi ...), (SPUlo ...))
863 // (SPUindirect $sp, imm)
864 MVT VT = Op.getValueType();
865 SDValue Op0 = N->getOperand(0);
866 SDValue Op1 = N->getOperand(1);
869 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
870 || (Op0.getOpcode() == ISD::Register
871 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
872 && RN->getReg() != SPU::R1))) {
874 if (Op1.getOpcode() == ISD::Constant) {
875 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
876 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
877 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
887 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
889 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
891 return SelectCode(Op);
895 * Emit the instruction sequence for i64 left shifts. The basic algorithm
896 * is to fill the bottom two word slots with zeros so that zeros are shifted
897 * in as the entire quadword is shifted left.
899 * \note This code could also be used to implement v2i64 shl.
901 * @param Op The shl operand
902 * @param OpVT Op's machine value value type (doesn't need to be passed, but
903 * makes life easier.)
904 * @return The SDNode with the entire instruction sequence
907 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
908 SDValue Op0 = Op.getOperand(0);
909 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
910 SDValue ShiftAmt = Op.getOperand(1);
911 MVT ShiftAmtVT = ShiftAmt.getValueType();
912 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
915 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
916 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
917 SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal);
918 ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT,
919 CurDAG->getTargetConstant(0, OpVT));
920 VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
921 SDValue(ZeroFill, 0),
923 SDValue(SelMask, 0));
925 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
926 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
927 unsigned bits = unsigned(CN->getZExtValue()) & 7;
931 CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT,
933 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
938 CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT,
939 SDValue((Shift != 0 ? Shift : VecOp0), 0),
940 CurDAG->getTargetConstant(bits, ShiftAmtVT));
944 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
946 CurDAG->getTargetConstant(3, ShiftAmtVT));
948 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
950 CurDAG->getTargetConstant(7, ShiftAmtVT));
952 CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT,
953 SDValue(VecOp0, 0), SDValue(Bytes, 0));
955 CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT,
956 SDValue(Shift, 0), SDValue(Bits, 0));
959 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
963 * Emit the instruction sequence for i64 logical right shifts.
965 * @param Op The shl operand
966 * @param OpVT Op's machine value value type (doesn't need to be passed, but
967 * makes life easier.)
968 * @return The SDNode with the entire instruction sequence
971 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
972 SDValue Op0 = Op.getOperand(0);
973 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
974 SDValue ShiftAmt = Op.getOperand(1);
975 MVT ShiftAmtVT = ShiftAmt.getValueType();
976 SDNode *VecOp0, *Shift = 0;
978 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
980 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
981 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
982 unsigned bits = unsigned(CN->getZExtValue()) & 7;
986 CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT,
988 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
993 CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT,
994 SDValue((Shift != 0 ? Shift : VecOp0), 0),
995 CurDAG->getTargetConstant(bits, ShiftAmtVT));
999 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
1001 CurDAG->getTargetConstant(3, ShiftAmtVT));
1003 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
1005 CurDAG->getTargetConstant(7, ShiftAmtVT));
1007 // Ensure that the shift amounts are negated!
1008 Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
1010 CurDAG->getTargetConstant(0, ShiftAmtVT));
1012 Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
1014 CurDAG->getTargetConstant(0, ShiftAmtVT));
1017 CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT,
1018 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1020 CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT,
1021 SDValue(Shift, 0), SDValue(Bits, 0));
1024 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
1028 * Emit the instruction sequence for i64 arithmetic right shifts.
1030 * @param Op The shl operand
1031 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1032 * makes life easier.)
1033 * @return The SDNode with the entire instruction sequence
1036 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
1037 // Promote Op0 to vector
1038 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1039 SDValue ShiftAmt = Op.getOperand(1);
1040 MVT ShiftAmtVT = ShiftAmt.getValueType();
1043 CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0));
1045 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1047 CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64,
1048 SDValue(VecOp0, 0), SignRotAmt);
1049 SDNode *UpperHalfSign =
1050 CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0));
1052 SDNode *UpperHalfSignMask =
1053 CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0));
1054 SDNode *UpperLowerMask =
1055 CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT,
1056 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1057 SDNode *UpperLowerSelect =
1058 CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
1059 SDValue(UpperHalfSignMask, 0),
1061 SDValue(UpperLowerMask, 0));
1065 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1066 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1067 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1072 CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT,
1073 SDValue(UpperLowerSelect, 0),
1074 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1080 CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT,
1081 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1082 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1086 CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
1087 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1090 CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT,
1091 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1093 CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT,
1094 SDValue(Shift, 0), SDValue(NegShift, 0));
1097 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
1101 Do the necessary magic necessary to load a i64 constant
1103 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT) {
1104 ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
1105 MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
1107 SPU::LowerSplat_v2i64(OpVecVT, *CurDAG, CN->getZExtValue());
1109 // Here's where it gets interesting, because we have to parse out the
1110 // subtree handed back in i64vec:
1112 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1113 // The degenerate case where the upper and lower bits in the splat are
1115 SDValue Op0 = i64vec.getOperand(0);
1116 ReplaceUses(i64vec, Op0);
1118 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT,
1119 SDValue(emitBuildVector(Op0), 0));
1120 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1121 SDValue lhs = i64vec.getOperand(0);
1122 SDValue rhs = i64vec.getOperand(1);
1123 SDValue shufmask = i64vec.getOperand(2);
1125 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1126 ReplaceUses(lhs, lhs.getOperand(0));
1127 lhs = lhs.getOperand(0);
1130 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1132 : emitBuildVector(lhs));
1134 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1135 ReplaceUses(rhs, rhs.getOperand(0));
1136 rhs = rhs.getOperand(0);
1139 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1141 : emitBuildVector(rhs));
1143 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1144 ReplaceUses(shufmask, shufmask.getOperand(0));
1145 shufmask = shufmask.getOperand(0);
1148 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1149 ? shufmask.getNode()
1150 : emitBuildVector(shufmask));
1153 Select(CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
1154 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1155 SDValue(shufMaskNode, 0)));
1157 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(shufNode, 0));
1159 cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
1164 /// createSPUISelDag - This pass converts a legalized DAG into a
1165 /// SPU-specific DAG, ready for instruction scheduling.
1167 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1168 return new SPUDAGToDAGISel(TM);