1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
41 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
43 isI64IntS10Immediate(ConstantSDNode *CN)
45 return isS10Constant(CN->getSignExtended());
48 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
50 isI32IntS10Immediate(ConstantSDNode *CN)
52 return isS10Constant(CN->getSignExtended());
56 //! SDNode predicate for sign-extended, 10-bit immediate values
58 isI32IntS10Immediate(SDNode *N)
60 return (N->getOpcode() == ISD::Constant
61 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
65 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
67 isI32IntU10Immediate(ConstantSDNode *CN)
69 return isU10Constant(CN->getSignExtended());
72 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
74 isI16IntS10Immediate(ConstantSDNode *CN)
76 return isS10Constant(CN->getSignExtended());
79 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
81 isI16IntS10Immediate(SDNode *N)
83 return (N->getOpcode() == ISD::Constant
84 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
87 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
89 isI16IntU10Immediate(ConstantSDNode *CN)
91 return isU10Constant((short) CN->getValue());
94 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
96 isI16IntU10Immediate(SDNode *N)
98 return (N->getOpcode() == ISD::Constant
99 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
102 //! ConstantSDNode predicate for signed 16-bit values
104 \arg CN The constant SelectionDAG node holding the value
105 \arg Imm The returned 16-bit value, if returning true
107 This predicate tests the value in \a CN to see whether it can be
108 represented as a 16-bit, sign-extended quantity. Returns true if
112 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
114 MVT::ValueType vt = CN->getValueType(0);
115 Imm = (short) CN->getValue();
116 if (vt >= MVT::i1 && vt <= MVT::i16) {
118 } else if (vt == MVT::i32) {
119 int32_t i_val = (int32_t) CN->getValue();
120 short s_val = (short) i_val;
121 return i_val == s_val;
123 int64_t i_val = (int64_t) CN->getValue();
124 short s_val = (short) i_val;
125 return i_val == s_val;
131 //! SDNode predicate for signed 16-bit values.
133 isIntS16Immediate(SDNode *N, short &Imm)
135 return (N->getOpcode() == ISD::Constant
136 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
139 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
141 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
143 MVT::ValueType vt = FPN->getValueType(0);
144 if (vt == MVT::f32) {
145 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
146 int sval = (int) ((val << 16) >> 16);
155 isHighLow(const SDOperand &Op)
157 return (Op.getOpcode() == SPUISD::IndirectAddr
158 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
159 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
160 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
161 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
164 //===------------------------------------------------------------------===//
165 //! MVT::ValueType to "useful stuff" mapping structure:
167 struct valtype_map_s {
169 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
170 bool ldresult_imm; /// LDRESULT instruction requires immediate?
171 int prefslot_byte; /// Byte offset of the "preferred" slot
174 const valtype_map_s valtype_map[] = {
175 { MVT::i1, 0, false, 3 },
176 { MVT::i8, SPU::ORBIr8, true, 3 },
177 { MVT::i16, SPU::ORHIr16, true, 2 },
178 { MVT::i32, SPU::ORIr32, true, 0 },
179 { MVT::i64, SPU::ORr64, false, 0 },
180 { MVT::f32, SPU::ORf32, false, 0 },
181 { MVT::f64, SPU::ORf64, false, 0 },
182 // vector types... (sigh!)
183 { MVT::v16i8, 0, false, 0 },
184 { MVT::v8i16, 0, false, 0 },
185 { MVT::v4i32, 0, false, 0 },
186 { MVT::v2i64, 0, false, 0 },
187 { MVT::v4f32, 0, false, 0 },
188 { MVT::v2f64, 0, false, 0 }
191 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
193 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
195 const valtype_map_s *retval = 0;
196 for (size_t i = 0; i < n_valtype_map; ++i) {
197 if (valtype_map[i].VT == VT) {
198 retval = valtype_map + i;
206 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
207 << MVT::getValueTypeString(VT)
217 //===--------------------------------------------------------------------===//
218 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
219 /// instructions for SelectionDAG operations.
221 class SPUDAGToDAGISel :
222 public SelectionDAGISel
224 SPUTargetMachine &TM;
225 SPUTargetLowering &SPUtli;
226 unsigned GlobalBaseReg;
229 SPUDAGToDAGISel(SPUTargetMachine &tm) :
230 SelectionDAGISel(*tm.getTargetLowering()),
232 SPUtli(*tm.getTargetLowering())
235 virtual bool runOnFunction(Function &Fn) {
236 // Make sure we re-emit a set of the global base reg if necessary
238 SelectionDAGISel::runOnFunction(Fn);
242 /// getI32Imm - Return a target constant with the specified value, of type
244 inline SDOperand getI32Imm(uint32_t Imm) {
245 return CurDAG->getTargetConstant(Imm, MVT::i32);
248 /// getI64Imm - Return a target constant with the specified value, of type
250 inline SDOperand getI64Imm(uint64_t Imm) {
251 return CurDAG->getTargetConstant(Imm, MVT::i64);
254 /// getSmallIPtrImm - Return a target constant of pointer type.
255 inline SDOperand getSmallIPtrImm(unsigned Imm) {
256 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
259 /// Select - Convert the specified operand from a target-independent to a
260 /// target-specific node if it hasn't already been changed.
261 SDNode *Select(SDOperand Op);
263 //! Returns true if the address N is an A-form (local store) address
264 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
267 //! D-form address predicate
268 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
271 /// Alternate D-form address using i7 offset predicate
272 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
275 /// D-form address selection workhorse
276 bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
277 SDOperand &Base, int minOffset, int maxOffset);
279 //! Address predicate if N can be expressed as an indexed [r+r] operation.
280 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
283 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
284 /// inline asm expressions.
285 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
287 std::vector<SDOperand> &OutOps,
290 switch (ConstraintCode) {
291 default: return true;
293 if (!SelectDFormAddr(Op, Op, Op0, Op1)
294 && !SelectAFormAddr(Op, Op, Op0, Op1))
295 SelectXFormAddr(Op, Op, Op0, Op1);
297 case 'o': // offsetable
298 if (!SelectDFormAddr(Op, Op, Op0, Op1)
299 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
301 AddToISelQueue(Op0); // r+0.
302 Op1 = getSmallIPtrImm(0);
305 case 'v': // not offsetable
307 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
309 SelectAddrIdxOnly(Op, Op, Op0, Op1);
314 OutOps.push_back(Op0);
315 OutOps.push_back(Op1);
319 /// InstructionSelectBasicBlock - This callback is invoked by
320 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
321 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
323 virtual const char *getPassName() const {
324 return "Cell SPU DAG->DAG Pattern Instruction Selection";
327 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
328 /// this target when scheduling the DAG.
329 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
330 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
331 assert(II && "No InstrInfo?");
332 return new SPUHazardRecognizer(*II);
335 // Include the pieces autogenerated from the target description.
336 #include "SPUGenDAGISel.inc"
339 /// InstructionSelectBasicBlock - This callback is invoked by
340 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
342 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
346 // Select target instructions for the DAG.
347 DAG.setRoot(SelectRoot(DAG.getRoot()));
348 DAG.RemoveDeadNodes();
350 // Emit machine code to BB.
351 ScheduleAndEmitDAG(DAG);
355 \arg Op The ISD instructio operand
356 \arg N The address to be tested
357 \arg Base The base address
358 \arg Index The base address index
361 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
363 // These match the addr256k operand type:
364 MVT::ValueType OffsVT = MVT::i16;
365 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
367 switch (N.getOpcode()) {
369 case ISD::ConstantPool:
370 case ISD::GlobalAddress:
371 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
375 case ISD::TargetConstant:
376 case ISD::TargetGlobalAddress:
377 case ISD::TargetJumpTable:
378 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
379 << "A-form address.\n";
383 case SPUISD::AFormAddr:
384 // Just load from memory if there's only a single use of the location,
385 // otherwise, this will get handled below with D-form offset addresses
387 SDOperand Op0 = N.getOperand(0);
388 switch (Op0.getOpcode()) {
389 case ISD::TargetConstantPool:
390 case ISD::TargetJumpTable:
395 case ISD::TargetGlobalAddress: {
396 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
397 GlobalValue *GV = GSDN->getGlobal();
398 if (GV->getAlignment() == 16) {
413 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
415 const int minDForm2Offset = -(1 << 7);
416 const int maxDForm2Offset = (1 << 7) - 1;
417 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
422 \arg Op The ISD instruction (ignored)
423 \arg N The address to be tested
424 \arg Base Base address register/pointer
425 \arg Index Base address index
427 Examine the input address by a base register plus a signed 10-bit
428 displacement, [r+I10] (D-form address).
430 \return true if \a N is a D-form address with \a Base and \a Index set
431 to non-empty SDOperand instances.
434 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
436 return DFormAddressPredicate(Op, N, Base, Index,
437 SPUFrameInfo::minFrameOffset(),
438 SPUFrameInfo::maxFrameOffset());
442 SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
443 SDOperand &Index, int minOffset,
445 unsigned Opc = N.getOpcode();
446 unsigned PtrTy = SPUtli.getPointerTy();
448 if (Opc == ISD::FrameIndex) {
449 // Stack frame index must be less than 512 (divided by 16):
450 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
451 int FI = int(FIN->getIndex());
452 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
454 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
455 Base = CurDAG->getTargetConstant(0, PtrTy);
456 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
459 } else if (Opc == ISD::ADD) {
460 // Generated by getelementptr
461 const SDOperand Op0 = N.getOperand(0);
462 const SDOperand Op1 = N.getOperand(1);
464 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
465 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
466 Base = CurDAG->getTargetConstant(0, PtrTy);
469 } else if (Op1.getOpcode() == ISD::Constant
470 || Op1.getOpcode() == ISD::TargetConstant) {
471 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
472 int32_t offset = int32_t(CN->getSignExtended());
474 if (Op0.getOpcode() == ISD::FrameIndex) {
475 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
476 int FI = int(FIN->getIndex());
477 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
478 << " frame index = " << FI << "\n");
480 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
481 Base = CurDAG->getTargetConstant(offset, PtrTy);
482 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
485 } else if (offset > minOffset && offset < maxOffset) {
486 Base = CurDAG->getTargetConstant(offset, PtrTy);
490 } else if (Op0.getOpcode() == ISD::Constant
491 || Op0.getOpcode() == ISD::TargetConstant) {
492 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
493 int32_t offset = int32_t(CN->getSignExtended());
495 if (Op1.getOpcode() == ISD::FrameIndex) {
496 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
497 int FI = int(FIN->getIndex());
498 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
499 << " frame index = " << FI << "\n");
501 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
502 Base = CurDAG->getTargetConstant(offset, PtrTy);
503 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
506 } else if (offset > minOffset && offset < maxOffset) {
507 Base = CurDAG->getTargetConstant(offset, PtrTy);
512 } else if (Opc == SPUISD::IndirectAddr) {
513 // Indirect with constant offset -> D-Form address
514 const SDOperand Op0 = N.getOperand(0);
515 const SDOperand Op1 = N.getOperand(1);
517 if (Op0.getOpcode() == SPUISD::Hi
518 && Op1.getOpcode() == SPUISD::Lo) {
519 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
520 Base = CurDAG->getTargetConstant(0, PtrTy);
523 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
527 if (isa<ConstantSDNode>(Op1)) {
528 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
529 offset = int32_t(CN->getSignExtended());
531 } else if (isa<ConstantSDNode>(Op0)) {
532 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
533 offset = int32_t(CN->getSignExtended());
537 if (offset >= minOffset && offset <= maxOffset) {
538 Base = CurDAG->getTargetConstant(offset, PtrTy);
543 } else if (Opc == SPUISD::AFormAddr) {
544 Base = CurDAG->getTargetConstant(0, N.getValueType());
547 } else if (Opc == SPUISD::LDRESULT) {
548 Base = CurDAG->getTargetConstant(0, N.getValueType());
556 \arg Op The ISD instruction operand
557 \arg N The address operand
558 \arg Base The base pointer operand
559 \arg Index The offset/index operand
561 If the address \a N can be expressed as a [r + s10imm] address, returns false.
562 Otherwise, creates two operands, Base and Index that will become the [r+r]
566 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
568 if (SelectAFormAddr(Op, N, Base, Index)
569 || SelectDFormAddr(Op, N, Base, Index))
572 // All else fails, punt and use an X-form address:
573 Base = N.getOperand(0);
574 Index = N.getOperand(1);
578 //! Convert the operand from a target-independent to a target-specific node
582 SPUDAGToDAGISel::Select(SDOperand Op) {
584 unsigned Opc = N->getOpcode();
587 MVT::ValueType OpVT = Op.getValueType();
590 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
591 return NULL; // Already selected.
592 } else if (Opc == ISD::FrameIndex) {
593 // Selects to (add $sp, FI * stackSlotSize)
595 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
596 MVT::ValueType PtrVT = SPUtli.getPointerTy();
598 // Adjust stack slot to actual offset in frame:
599 if (isS10Constant(FI)) {
600 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
604 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
605 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
608 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
612 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
613 Ops[1] = CurDAG->getConstant(FI, PtrVT);
616 AddToISelQueue(Ops[1]);
618 } else if (Opc == ISD::ZERO_EXTEND) {
619 // (zero_extend:i16 (and:i8 <arg>, <const>))
620 const SDOperand &Op1 = N->getOperand(0);
622 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
623 if (Op1.getOpcode() == ISD::AND) {
624 // Fold this into a single ANDHI. This is often seen in expansions of i1
625 // to i8, then i8 to i16 in logical/branching operations.
626 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
627 "<arg>, <const>))\n");
628 NewOpc = SPU::ANDHIi8i16;
629 Ops[0] = Op1.getOperand(0);
630 Ops[1] = Op1.getOperand(1);
634 } else if (Opc == SPUISD::LDRESULT) {
635 // Custom select instructions for LDRESULT
636 unsigned VT = N->getValueType(0);
637 SDOperand Arg = N->getOperand(0);
638 SDOperand Chain = N->getOperand(1);
640 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
642 if (vtm->ldresult_ins == 0) {
643 cerr << "LDRESULT for unsupported type: "
644 << MVT::getValueTypeString(VT)
650 Opc = vtm->ldresult_ins;
651 if (vtm->ldresult_imm) {
652 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
654 AddToISelQueue(Zero);
655 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
657 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
660 Chain = SDOperand(Result, 1);
661 AddToISelQueue(Chain);
664 } else if (Opc == SPUISD::IndirectAddr) {
665 SDOperand Op0 = Op.getOperand(0);
666 if (Op0.getOpcode() == SPUISD::LDRESULT) {
667 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
668 // (IndirectAddr (LDRESULT, imm))
669 SDOperand Op1 = Op.getOperand(1);
670 MVT::ValueType VT = Op.getValueType();
672 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
673 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
674 DEBUG(cerr << "\nOp1 = ");
675 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
678 if (Op1.getOpcode() == ISD::Constant) {
679 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
680 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
681 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
693 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
695 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
697 return SelectCode(Op);
700 /// createPPCISelDag - This pass converts a legalized DAG into a
701 /// SPU-specific DAG, ready for instruction scheduling.
703 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
704 return new SPUDAGToDAGISel(TM);