1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant((int) CN->getValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant((int) CN->getValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant((short) CN->getValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT::ValueType vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt >= MVT::i1 && vt <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT::ValueType vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDOperand &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT::ValueType to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 int prefslot_byte; /// Byte offset of the "preferred" slot
172 const valtype_map_s valtype_map[] = {
174 { MVT::i8, SPU::ORBIr8, 3 },
175 { MVT::i16, SPU::ORHIr16, 2 },
176 { MVT::i32, SPU::ORIr32, 0 },
177 { MVT::i64, SPU::ORIr64, 0 },
180 // vector types... (sigh!)
181 { MVT::v16i8, 0, 0 },
182 { MVT::v8i16, 0, 0 },
183 { MVT::v4i32, 0, 0 },
184 { MVT::v2i64, 0, 0 },
185 { MVT::v4f32, 0, 0 },
189 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
191 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
193 const valtype_map_s *retval = 0;
194 for (size_t i = 0; i < n_valtype_map; ++i) {
195 if (valtype_map[i].VT == VT) {
196 retval = valtype_map + i;
204 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
205 << MVT::getValueTypeString(VT)
215 //===--------------------------------------------------------------------===//
216 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
217 /// instructions for SelectionDAG operations.
219 class SPUDAGToDAGISel :
220 public SelectionDAGISel
222 SPUTargetMachine &TM;
223 SPUTargetLowering &SPUtli;
224 unsigned GlobalBaseReg;
227 SPUDAGToDAGISel(SPUTargetMachine &tm) :
228 SelectionDAGISel(*tm.getTargetLowering()),
230 SPUtli(*tm.getTargetLowering())
233 virtual bool runOnFunction(Function &Fn) {
234 // Make sure we re-emit a set of the global base reg if necessary
236 SelectionDAGISel::runOnFunction(Fn);
240 /// getI32Imm - Return a target constant with the specified value, of type
242 inline SDOperand getI32Imm(uint32_t Imm) {
243 return CurDAG->getTargetConstant(Imm, MVT::i32);
246 /// getI64Imm - Return a target constant with the specified value, of type
248 inline SDOperand getI64Imm(uint64_t Imm) {
249 return CurDAG->getTargetConstant(Imm, MVT::i64);
252 /// getSmallIPtrImm - Return a target constant of pointer type.
253 inline SDOperand getSmallIPtrImm(unsigned Imm) {
254 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
257 /// Select - Convert the specified operand from a target-independent to a
258 /// target-specific node if it hasn't already been changed.
259 SDNode *Select(SDOperand Op);
261 //! Returns true if the address N is an A-form (local store) address
262 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
265 //! D-form address predicate
266 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
269 /// Alternate D-form address using i7 offset predicate
270 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
273 /// D-form address selection workhorse
274 bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
275 SDOperand &Base, int minOffset, int maxOffset);
277 //! Address predicate if N can be expressed as an indexed [r+r] operation.
278 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
281 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
282 /// inline asm expressions.
283 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
285 std::vector<SDOperand> &OutOps,
288 switch (ConstraintCode) {
289 default: return true;
291 if (!SelectDFormAddr(Op, Op, Op0, Op1)
292 && !SelectAFormAddr(Op, Op, Op0, Op1))
293 SelectXFormAddr(Op, Op, Op0, Op1);
295 case 'o': // offsetable
296 if (!SelectDFormAddr(Op, Op, Op0, Op1)
297 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
299 AddToISelQueue(Op0); // r+0.
300 Op1 = getSmallIPtrImm(0);
303 case 'v': // not offsetable
305 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
307 SelectAddrIdxOnly(Op, Op, Op0, Op1);
312 OutOps.push_back(Op0);
313 OutOps.push_back(Op1);
317 /// InstructionSelectBasicBlock - This callback is invoked by
318 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
319 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
321 virtual const char *getPassName() const {
322 return "Cell SPU DAG->DAG Pattern Instruction Selection";
325 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
326 /// this target when scheduling the DAG.
327 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
328 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
329 assert(II && "No InstrInfo?");
330 return new SPUHazardRecognizer(*II);
333 // Include the pieces autogenerated from the target description.
334 #include "SPUGenDAGISel.inc"
337 /// InstructionSelectBasicBlock - This callback is invoked by
338 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
340 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
344 // Select target instructions for the DAG.
345 DAG.setRoot(SelectRoot(DAG.getRoot()));
346 DAG.RemoveDeadNodes();
348 // Emit machine code to BB.
349 ScheduleAndEmitDAG(DAG);
353 \arg Op The ISD instructio operand
354 \arg N The address to be tested
355 \arg Base The base address
356 \arg Index The base address index
359 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
361 // These match the addr256k operand type:
362 MVT::ValueType OffsVT = MVT::i16;
363 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
365 switch (N.getOpcode()) {
367 case ISD::ConstantPool:
368 case ISD::GlobalAddress:
369 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
373 case ISD::TargetConstant:
374 case ISD::TargetGlobalAddress:
375 case ISD::TargetJumpTable:
376 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
377 << "A-form address.\n";
381 case SPUISD::AFormAddr:
382 // Just load from memory if there's only a single use of the location,
383 // otherwise, this will get handled below with D-form offset addresses
385 SDOperand Op0 = N.getOperand(0);
386 switch (Op0.getOpcode()) {
387 case ISD::TargetConstantPool:
388 case ISD::TargetJumpTable:
393 case ISD::TargetGlobalAddress: {
394 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
395 GlobalValue *GV = GSDN->getGlobal();
396 if (GV->getAlignment() == 16) {
411 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
413 return DFormAddressPredicate(Op, N, Disp, Base, -(1 << 7), (1 << 7) - 1);
417 \arg Op The ISD instruction (ignored)
418 \arg N The address to be tested
419 \arg Base Base address register/pointer
420 \arg Index Base address index
422 Examine the input address by a base register plus a signed 10-bit
423 displacement, [r+I10] (D-form address).
425 \return true if \a N is a D-form address with \a Base and \a Index set
426 to non-empty SDOperand instances.
429 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
431 return DFormAddressPredicate(Op, N, Base, Index,
432 SPUFrameInfo::minFrameOffset(),
433 SPUFrameInfo::maxFrameOffset());
437 SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
438 SDOperand &Index, int minOffset,
440 unsigned Opc = N.getOpcode();
441 unsigned PtrTy = SPUtli.getPointerTy();
443 if (Opc == ISD::FrameIndex) {
444 // Stack frame index must be less than 512 (divided by 16):
445 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
446 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
447 << FI->getIndex() << "\n");
448 if (FI->getIndex() < maxOffset) {
449 Base = CurDAG->getTargetConstant(0, PtrTy);
450 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
453 } else if (Opc == ISD::ADD) {
454 // Generated by getelementptr
455 const SDOperand Op0 = N.getOperand(0);
456 const SDOperand Op1 = N.getOperand(1);
458 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
459 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
460 Base = CurDAG->getTargetConstant(0, PtrTy);
463 } else if (Op1.getOpcode() == ISD::Constant
464 || Op1.getOpcode() == ISD::TargetConstant) {
465 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
466 int32_t offset = int32_t(CN->getSignExtended());
468 if (Op0.getOpcode() == ISD::FrameIndex) {
469 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
470 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
471 << " frame index = " << FI->getIndex() << "\n");
473 if (FI->getIndex() < maxOffset) {
474 Base = CurDAG->getTargetConstant(offset, PtrTy);
475 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
478 } else if (offset > minOffset && offset < maxOffset) {
479 Base = CurDAG->getTargetConstant(offset, PtrTy);
483 } else if (Op0.getOpcode() == ISD::Constant
484 || Op0.getOpcode() == ISD::TargetConstant) {
485 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
486 int32_t offset = int32_t(CN->getSignExtended());
488 if (Op1.getOpcode() == ISD::FrameIndex) {
489 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op1);
490 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
491 << " frame index = " << FI->getIndex() << "\n");
493 if (FI->getIndex() < maxOffset) {
494 Base = CurDAG->getTargetConstant(offset, PtrTy);
495 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
498 } else if (offset > minOffset && offset < maxOffset) {
499 Base = CurDAG->getTargetConstant(offset, PtrTy);
504 } else if (Opc == SPUISD::IndirectAddr) {
505 // Indirect with constant offset -> D-Form address
506 const SDOperand Op0 = N.getOperand(0);
507 const SDOperand Op1 = N.getOperand(1);
509 if (Op0.getOpcode() == SPUISD::Hi
510 && Op1.getOpcode() == SPUISD::Lo) {
511 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
512 Base = CurDAG->getTargetConstant(0, PtrTy);
515 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
519 if (isa<ConstantSDNode>(Op1)) {
520 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
521 offset = int32_t(CN->getSignExtended());
523 } else if (isa<ConstantSDNode>(Op0)) {
524 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
525 offset = int32_t(CN->getSignExtended());
529 if (offset >= minOffset && offset <= maxOffset) {
530 Base = CurDAG->getTargetConstant(offset, PtrTy);
535 } else if (Opc == SPUISD::AFormAddr) {
536 Base = CurDAG->getTargetConstant(0, N.getValueType());
539 } else if (Opc == SPUISD::LDRESULT) {
540 Base = CurDAG->getTargetConstant(0, N.getValueType());
548 \arg Op The ISD instruction operand
549 \arg N The address operand
550 \arg Base The base pointer operand
551 \arg Index The offset/index operand
553 If the address \a N can be expressed as a [r + s10imm] address, returns false.
554 Otherwise, creates two operands, Base and Index that will become the [r+r]
558 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
560 if (SelectAFormAddr(Op, N, Base, Index)
561 || SelectDFormAddr(Op, N, Base, Index))
564 // All else fails, punt and use an X-form address:
565 Base = N.getOperand(0);
566 Index = N.getOperand(1);
570 //! Convert the operand from a target-independent to a target-specific node
574 SPUDAGToDAGISel::Select(SDOperand Op) {
576 unsigned Opc = N->getOpcode();
579 MVT::ValueType OpVT = Op.getValueType();
582 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
583 return NULL; // Already selected.
584 } else if (Opc == ISD::FrameIndex) {
585 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
586 int FI = cast<FrameIndexSDNode>(N)->getIndex();
587 MVT::ValueType PtrVT = SPUtli.getPointerTy();
588 SDOperand Zero = CurDAG->getTargetConstant(0, PtrVT);
589 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, PtrVT);
591 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
596 } else if (Opc == ISD::ZERO_EXTEND) {
597 // (zero_extend:i16 (and:i8 <arg>, <const>))
598 const SDOperand &Op1 = N->getOperand(0);
600 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
601 if (Op1.getOpcode() == ISD::AND) {
602 // Fold this into a single ANDHI. This is often seen in expansions of i1
603 // to i8, then i8 to i16 in logical/branching operations.
604 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
605 "<arg>, <const>))\n");
606 NewOpc = SPU::ANDHI1To2;
607 Ops[0] = Op1.getOperand(0);
608 Ops[1] = Op1.getOperand(1);
612 } else if (Opc == SPUISD::LDRESULT) {
613 // Custom select instructions for LDRESULT
614 unsigned VT = N->getValueType(0);
615 SDOperand Arg = N->getOperand(0);
616 SDOperand Chain = N->getOperand(1);
620 if (!MVT::isFloatingPoint(VT)) {
621 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
622 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
624 if (vtm->ldresult_ins == 0) {
625 cerr << "LDRESULT for unsupported type: "
626 << MVT::getValueTypeString(VT)
630 Opc = vtm->ldresult_ins;
632 AddToISelQueue(Zero);
633 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
635 Opc = (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64);
636 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
639 Chain = SDOperand(Result, 1);
640 AddToISelQueue(Chain);
643 } else if (Opc == SPUISD::IndirectAddr) {
644 SDOperand Op0 = Op.getOperand(0);
645 if (Op0.getOpcode() == SPUISD::LDRESULT) {
646 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
647 // (IndirectAddr (LDRESULT, imm))
648 SDOperand Op1 = Op.getOperand(1);
649 MVT::ValueType VT = Op.getValueType();
651 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
652 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
653 DEBUG(cerr << "\nOp1 = ");
654 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
657 if (Op1.getOpcode() == ISD::Constant) {
658 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
659 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
660 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
672 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
674 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
676 return SelectCode(Op);
679 /// createPPCISelDag - This pass converts a legalized DAG into a
680 /// SPU-specific DAG, ready for instruction scheduling.
682 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
683 return new SPUDAGToDAGISel(TM);