1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/raw_ostream.h"
43 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
45 isI64IntS10Immediate(ConstantSDNode *CN)
47 return isS10Constant(CN->getSExtValue());
50 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
52 isI32IntS10Immediate(ConstantSDNode *CN)
54 return isS10Constant(CN->getSExtValue());
57 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
59 isI32IntU10Immediate(ConstantSDNode *CN)
61 return isU10Constant(CN->getSExtValue());
64 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
66 isI16IntS10Immediate(ConstantSDNode *CN)
68 return isS10Constant(CN->getSExtValue());
71 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(SDNode *N)
75 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
76 return (CN != 0 && isI16IntS10Immediate(CN));
79 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
81 isI16IntU10Immediate(ConstantSDNode *CN)
83 return isU10Constant((short) CN->getZExtValue());
86 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
88 isI16IntU10Immediate(SDNode *N)
90 return (N->getOpcode() == ISD::Constant
91 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
94 //! ConstantSDNode predicate for signed 16-bit values
96 \arg CN The constant SelectionDAG node holding the value
97 \arg Imm The returned 16-bit value, if returning true
99 This predicate tests the value in \a CN to see whether it can be
100 represented as a 16-bit, sign-extended quantity. Returns true if
104 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
106 EVT vt = CN->getValueType(0);
107 Imm = (short) CN->getZExtValue();
108 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
110 } else if (vt == MVT::i32) {
111 int32_t i_val = (int32_t) CN->getZExtValue();
112 short s_val = (short) i_val;
113 return i_val == s_val;
115 int64_t i_val = (int64_t) CN->getZExtValue();
116 short s_val = (short) i_val;
117 return i_val == s_val;
123 //! SDNode predicate for signed 16-bit values.
125 isIntS16Immediate(SDNode *N, short &Imm)
127 return (N->getOpcode() == ISD::Constant
128 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
131 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
133 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
135 EVT vt = FPN->getValueType(0);
136 if (vt == MVT::f32) {
137 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
138 int sval = (int) ((val << 16) >> 16);
147 isHighLow(const SDValue &Op)
149 return (Op.getOpcode() == SPUISD::IndirectAddr
150 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
151 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
152 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
153 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
156 //===------------------------------------------------------------------===//
157 //! EVT to "useful stuff" mapping structure:
159 struct valtype_map_s {
161 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
162 bool ldresult_imm; /// LDRESULT instruction requires immediate?
163 unsigned lrinst; /// LR instruction
166 const valtype_map_s valtype_map[] = {
167 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
168 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
169 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
170 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
171 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
172 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
173 // vector types... (sigh!)
174 { MVT::v16i8, 0, false, SPU::LRv16i8 },
175 { MVT::v8i16, 0, false, SPU::LRv8i16 },
176 { MVT::v4i32, 0, false, SPU::LRv4i32 },
177 { MVT::v2i64, 0, false, SPU::LRv2i64 },
178 { MVT::v4f32, 0, false, SPU::LRv4f32 },
179 { MVT::v2f64, 0, false, SPU::LRv2f64 }
182 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
184 const valtype_map_s *getValueTypeMapEntry(EVT VT)
186 const valtype_map_s *retval = 0;
187 for (size_t i = 0; i < n_valtype_map; ++i) {
188 if (valtype_map[i].VT == VT) {
189 retval = valtype_map + i;
198 raw_string_ostream Msg(msg);
199 Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
200 << VT.getEVTString();
201 llvm_report_error(Msg.str());
208 //! Generate the carry-generate shuffle mask.
209 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
210 SmallVector<SDValue, 16 > ShufBytes;
212 // Create the shuffle mask for "rotating" the borrow up one register slot
213 // once the borrow is generated.
214 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
215 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
216 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
217 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
219 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
220 &ShufBytes[0], ShufBytes.size());
223 //! Generate the borrow-generate shuffle mask
224 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
225 SmallVector<SDValue, 16 > ShufBytes;
227 // Create the shuffle mask for "rotating" the borrow up one register slot
228 // once the borrow is generated.
229 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
230 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
231 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
232 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
234 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
235 &ShufBytes[0], ShufBytes.size());
238 //===------------------------------------------------------------------===//
239 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
240 /// instructions for SelectionDAG operations.
242 class SPUDAGToDAGISel :
243 public SelectionDAGISel
245 SPUTargetMachine &TM;
246 SPUTargetLowering &SPUtli;
247 unsigned GlobalBaseReg;
250 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
251 SelectionDAGISel(tm),
253 SPUtli(*tm.getTargetLowering())
256 virtual bool runOnMachineFunction(MachineFunction &MF) {
257 // Make sure we re-emit a set of the global base reg if necessary
259 SelectionDAGISel::runOnMachineFunction(MF);
263 /// getI32Imm - Return a target constant with the specified value, of type
265 inline SDValue getI32Imm(uint32_t Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i32);
269 /// getI64Imm - Return a target constant with the specified value, of type
271 inline SDValue getI64Imm(uint64_t Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i64);
275 /// getSmallIPtrImm - Return a target constant of pointer type.
276 inline SDValue getSmallIPtrImm(unsigned Imm) {
277 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
280 SDNode *emitBuildVector(SDNode *bvNode) {
281 EVT vecVT = bvNode->getValueType(0);
282 EVT eltVT = vecVT.getVectorElementType();
283 DebugLoc dl = bvNode->getDebugLoc();
285 // Check to see if this vector can be represented as a CellSPU immediate
286 // constant by invoking all of the instruction selection predicates:
287 if (((vecVT == MVT::v8i16) &&
288 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
289 ((vecVT == MVT::v4i32) &&
290 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
291 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
292 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
293 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
294 ((vecVT == MVT::v2i64) &&
295 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
296 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
297 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
298 return Select(bvNode);
300 // No, need to emit a constant pool spill:
301 std::vector<Constant*> CV;
303 for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
304 ConstantSDNode *V = dyn_cast<ConstantSDNode > (bvNode->getOperand(i));
305 CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
308 Constant *CP = ConstantVector::get(CV);
309 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
310 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
311 SDValue CGPoolOffset =
312 SPU::LowerConstantPool(CPIdx, *CurDAG,
313 SPUtli.getSPUTargetMachine());
314 return SelectCode(CurDAG->getLoad(vecVT, dl,
315 CurDAG->getEntryNode(), CGPoolOffset,
316 PseudoSourceValue::getConstantPool(), 0,
317 false, false, Alignment).getNode());
320 /// Select - Convert the specified operand from a target-independent to a
321 /// target-specific node if it hasn't already been changed.
322 SDNode *Select(SDNode *N);
324 //! Emit the instruction sequence for i64 shl
325 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
327 //! Emit the instruction sequence for i64 srl
328 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
330 //! Emit the instruction sequence for i64 sra
331 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
333 //! Emit the necessary sequence for loading i64 constants:
334 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
336 //! Alternate instruction emit sequence for loading i64 constants
337 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
339 //! Returns true if the address N is an A-form (local store) address
340 bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
343 //! D-form address predicate
344 bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
347 /// Alternate D-form address using i7 offset predicate
348 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
351 /// D-form address selection workhorse
352 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
353 SDValue &Base, int minOffset, int maxOffset);
355 //! Address predicate if N can be expressed as an indexed [r+r] operation.
356 bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
359 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
360 /// inline asm expressions.
361 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
363 std::vector<SDValue> &OutOps) {
365 switch (ConstraintCode) {
366 default: return true;
368 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
369 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
370 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
372 case 'o': // offsetable
373 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
374 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
376 Op1 = getSmallIPtrImm(0);
379 case 'v': // not offsetable
381 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
383 SelectAddrIdxOnly(Op, Op, Op0, Op1);
388 OutOps.push_back(Op0);
389 OutOps.push_back(Op1);
393 /// InstructionSelect - This callback is invoked by
394 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
395 virtual void InstructionSelect();
397 virtual const char *getPassName() const {
398 return "Cell SPU DAG->DAG Pattern Instruction Selection";
401 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
402 /// this target when scheduling the DAG.
403 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
404 const TargetInstrInfo *II = TM.getInstrInfo();
405 assert(II && "No InstrInfo?");
406 return new SPUHazardRecognizer(*II);
409 // Include the pieces autogenerated from the target description.
410 #include "SPUGenDAGISel.inc"
414 /// InstructionSelect - This callback is invoked by
415 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
417 SPUDAGToDAGISel::InstructionSelect()
419 // Select target instructions for the DAG.
421 CurDAG->RemoveDeadNodes();
425 \arg Op The ISD instruction operand
426 \arg N The address to be tested
427 \arg Base The base address
428 \arg Index The base address index
431 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
433 // These match the addr256k operand type:
434 EVT OffsVT = MVT::i16;
435 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
437 switch (N.getOpcode()) {
439 case ISD::ConstantPool:
440 case ISD::GlobalAddress:
441 llvm_report_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
444 case ISD::TargetConstant:
445 case ISD::TargetGlobalAddress:
446 case ISD::TargetJumpTable:
447 llvm_report_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
448 "not wrapped as A-form address.");
451 case SPUISD::AFormAddr:
452 // Just load from memory if there's only a single use of the location,
453 // otherwise, this will get handled below with D-form offset addresses
455 SDValue Op0 = N.getOperand(0);
456 switch (Op0.getOpcode()) {
457 case ISD::TargetConstantPool:
458 case ISD::TargetJumpTable:
463 case ISD::TargetGlobalAddress: {
464 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
465 GlobalValue *GV = GSDN->getGlobal();
466 if (GV->getAlignment() == 16) {
481 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
483 const int minDForm2Offset = -(1 << 7);
484 const int maxDForm2Offset = (1 << 7) - 1;
485 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
490 \arg Op The ISD instruction (ignored)
491 \arg N The address to be tested
492 \arg Base Base address register/pointer
493 \arg Index Base address index
495 Examine the input address by a base register plus a signed 10-bit
496 displacement, [r+I10] (D-form address).
498 \return true if \a N is a D-form address with \a Base and \a Index set
499 to non-empty SDValue instances.
502 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
504 return DFormAddressPredicate(Op, N, Base, Index,
505 SPUFrameInfo::minFrameOffset(),
506 SPUFrameInfo::maxFrameOffset());
510 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
511 SDValue &Index, int minOffset,
513 unsigned Opc = N.getOpcode();
514 EVT PtrTy = SPUtli.getPointerTy();
516 if (Opc == ISD::FrameIndex) {
517 // Stack frame index must be less than 512 (divided by 16):
518 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
519 int FI = int(FIN->getIndex());
520 DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
522 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
523 Base = CurDAG->getTargetConstant(0, PtrTy);
524 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
527 } else if (Opc == ISD::ADD) {
528 // Generated by getelementptr
529 const SDValue Op0 = N.getOperand(0);
530 const SDValue Op1 = N.getOperand(1);
532 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
533 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
534 Base = CurDAG->getTargetConstant(0, PtrTy);
537 } else if (Op1.getOpcode() == ISD::Constant
538 || Op1.getOpcode() == ISD::TargetConstant) {
539 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
540 int32_t offset = int32_t(CN->getSExtValue());
542 if (Op0.getOpcode() == ISD::FrameIndex) {
543 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
544 int FI = int(FIN->getIndex());
545 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
546 << " frame index = " << FI << "\n");
548 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
549 Base = CurDAG->getTargetConstant(offset, PtrTy);
550 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
553 } else if (offset > minOffset && offset < maxOffset) {
554 Base = CurDAG->getTargetConstant(offset, PtrTy);
558 } else if (Op0.getOpcode() == ISD::Constant
559 || Op0.getOpcode() == ISD::TargetConstant) {
560 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
561 int32_t offset = int32_t(CN->getSExtValue());
563 if (Op1.getOpcode() == ISD::FrameIndex) {
564 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
565 int FI = int(FIN->getIndex());
566 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
567 << " frame index = " << FI << "\n");
569 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
570 Base = CurDAG->getTargetConstant(offset, PtrTy);
571 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
574 } else if (offset > minOffset && offset < maxOffset) {
575 Base = CurDAG->getTargetConstant(offset, PtrTy);
580 } else if (Opc == SPUISD::IndirectAddr) {
581 // Indirect with constant offset -> D-Form address
582 const SDValue Op0 = N.getOperand(0);
583 const SDValue Op1 = N.getOperand(1);
585 if (Op0.getOpcode() == SPUISD::Hi
586 && Op1.getOpcode() == SPUISD::Lo) {
587 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
588 Base = CurDAG->getTargetConstant(0, PtrTy);
591 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
595 if (isa<ConstantSDNode>(Op1)) {
596 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
597 offset = int32_t(CN->getSExtValue());
599 } else if (isa<ConstantSDNode>(Op0)) {
600 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
601 offset = int32_t(CN->getSExtValue());
605 if (offset >= minOffset && offset <= maxOffset) {
606 Base = CurDAG->getTargetConstant(offset, PtrTy);
611 } else if (Opc == SPUISD::AFormAddr) {
612 Base = CurDAG->getTargetConstant(0, N.getValueType());
615 } else if (Opc == SPUISD::LDRESULT) {
616 Base = CurDAG->getTargetConstant(0, N.getValueType());
619 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
620 unsigned OpOpc = Op->getOpcode();
622 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
623 // Direct load/store without getelementptr
626 // Get the register from CopyFromReg
627 if (Opc == ISD::CopyFromReg)
628 Addr = N.getOperand(1);
630 Addr = N; // Register
632 Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
634 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
635 if (Offs.getOpcode() == ISD::UNDEF)
636 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
643 /* If otherwise unadorned, default to D-form address with 0 offset: */
644 if (Opc == ISD::CopyFromReg) {
645 Index = N.getOperand(1);
650 Base = CurDAG->getTargetConstant(0, Index.getValueType());
659 \arg Op The ISD instruction operand
660 \arg N The address operand
661 \arg Base The base pointer operand
662 \arg Index The offset/index operand
664 If the address \a N can be expressed as an A-form or D-form address, returns
665 false. Otherwise, creates two operands, Base and Index that will become the
666 (r)(r) X-form address.
669 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
671 if (!SelectAFormAddr(Op, N, Base, Index)
672 && !SelectDFormAddr(Op, N, Base, Index)) {
673 // If the address is neither A-form or D-form, punt and use an X-form
675 Base = N.getOperand(1);
676 Index = N.getOperand(0);
683 //! Convert the operand from a target-independent to a target-specific node
687 SPUDAGToDAGISel::Select(SDNode *N) {
688 unsigned Opc = N->getOpcode();
691 EVT OpVT = N->getValueType(0);
693 DebugLoc dl = N->getDebugLoc();
695 if (N->isMachineOpcode()) {
696 return NULL; // Already selected.
699 if (Opc == ISD::FrameIndex) {
700 int FI = cast<FrameIndexSDNode>(N)->getIndex();
701 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
702 SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
711 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
712 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
713 N->getValueType(0), TFI, Imm0),
717 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
718 // Catch the i64 constants that end up here. Note: The backend doesn't
719 // attempt to legalize the constant (it's useless because DAGCombiner
720 // will insert 64-bit constants and we can't stop it).
721 return SelectI64Constant(N, OpVT, N->getDebugLoc());
722 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
723 && OpVT == MVT::i64) {
724 SDValue Op0 = N->getOperand(0);
725 EVT Op0VT = Op0.getValueType();
726 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
727 Op0VT, (128 / Op0VT.getSizeInBits()));
728 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
729 OpVT, (128 / OpVT.getSizeInBits()));
732 switch (Op0VT.getSimpleVT().SimpleTy) {
734 llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
737 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
738 CurDAG->getConstant(0x80808080, MVT::i32),
739 CurDAG->getConstant(0x00010203, MVT::i32),
740 CurDAG->getConstant(0x80808080, MVT::i32),
741 CurDAG->getConstant(0x08090a0b, MVT::i32));
745 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
746 CurDAG->getConstant(0x80808080, MVT::i32),
747 CurDAG->getConstant(0x80800203, MVT::i32),
748 CurDAG->getConstant(0x80808080, MVT::i32),
749 CurDAG->getConstant(0x80800a0b, MVT::i32));
753 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
754 CurDAG->getConstant(0x80808080, MVT::i32),
755 CurDAG->getConstant(0x80808003, MVT::i32),
756 CurDAG->getConstant(0x80808080, MVT::i32),
757 CurDAG->getConstant(0x8080800b, MVT::i32));
761 SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
762 SDNode *PromoteScalar =
763 SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
764 Op0VecVT, Op0).getNode());
766 SDValue zextShuffle =
767 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
768 SDValue(PromoteScalar, 0),
769 SDValue(PromoteScalar, 0),
770 SDValue(shufMaskLoad, 0));
772 // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
773 // re-use it in the VEC2PREFSLOT selection without needing to explicitly
774 // call SelectCode (it's already done for us.)
775 SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle).getNode());
776 return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
777 zextShuffle).getNode());
778 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
780 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
782 return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
783 N->getOperand(0), N->getOperand(1),
784 SDValue(CGLoad, 0)).getNode());
785 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
787 emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
789 return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
790 N->getOperand(0), N->getOperand(1),
791 SDValue(CGLoad, 0)).getNode());
792 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
794 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
796 return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
797 N->getOperand(0), N->getOperand(1),
798 SDValue(CGLoad, 0)).getNode());
799 } else if (Opc == ISD::TRUNCATE) {
800 SDValue Op0 = N->getOperand(0);
801 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
803 && Op0.getValueType() == MVT::i64) {
804 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
806 // Take advantage of the fact that the upper 32 bits are in the
807 // i32 preferred slot and avoid shuffle gymnastics:
808 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
810 unsigned shift_amt = unsigned(CN->getZExtValue());
812 if (shift_amt >= 32) {
814 CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT,
819 // Take care of the additional shift, if present:
820 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
821 unsigned Opc = SPU::ROTMAIr32_i32;
823 if (Op0.getOpcode() == ISD::SRL)
826 hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
834 } else if (Opc == ISD::SHL) {
835 if (OpVT == MVT::i64) {
836 return SelectSHLi64(N, OpVT);
838 } else if (Opc == ISD::SRL) {
839 if (OpVT == MVT::i64) {
840 return SelectSRLi64(N, OpVT);
842 } else if (Opc == ISD::SRA) {
843 if (OpVT == MVT::i64) {
844 return SelectSRAi64(N, OpVT);
846 } else if (Opc == ISD::FNEG
847 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
848 DebugLoc dl = N->getDebugLoc();
849 // Check if the pattern is a special form of DFNMS:
850 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
851 SDValue Op0 = N->getOperand(0);
852 if (Op0.getOpcode() == ISD::FSUB) {
853 SDValue Op00 = Op0.getOperand(0);
854 if (Op00.getOpcode() == ISD::FMUL) {
855 unsigned Opc = SPU::DFNMSf64;
856 if (OpVT == MVT::v2f64)
857 Opc = SPU::DFNMSv2f64;
859 return CurDAG->getMachineNode(Opc, dl, OpVT,
866 SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
867 SDNode *signMask = 0;
868 unsigned Opc = SPU::XORfneg64;
870 if (OpVT == MVT::f64) {
871 signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
872 } else if (OpVT == MVT::v2f64) {
873 Opc = SPU::XORfnegvec;
874 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
876 negConst, negConst).getNode());
879 return CurDAG->getMachineNode(Opc, dl, OpVT,
880 N->getOperand(0), SDValue(signMask, 0));
881 } else if (Opc == ISD::FABS) {
882 if (OpVT == MVT::f64) {
883 SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
884 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
885 N->getOperand(0), SDValue(signMask, 0));
886 } else if (OpVT == MVT::v2f64) {
887 SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
888 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
890 SDNode *signMask = emitBuildVector(absVec.getNode());
891 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
892 N->getOperand(0), SDValue(signMask, 0));
894 } else if (Opc == SPUISD::LDRESULT) {
895 // Custom select instructions for LDRESULT
896 EVT VT = N->getValueType(0);
897 SDValue Arg = N->getOperand(0);
898 SDValue Chain = N->getOperand(1);
900 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
902 if (vtm->ldresult_ins == 0) {
904 raw_string_ostream Msg(msg);
905 Msg << "LDRESULT for unsupported type: "
906 << VT.getEVTString();
907 llvm_report_error(Msg.str());
910 Opc = vtm->ldresult_ins;
911 if (vtm->ldresult_imm) {
912 SDValue Zero = CurDAG->getTargetConstant(0, VT);
914 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
916 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
920 } else if (Opc == SPUISD::IndirectAddr) {
921 // Look at the operands: SelectCode() will catch the cases that aren't
922 // specifically handled here.
924 // SPUInstrInfo catches the following patterns:
925 // (SPUindirect (SPUhi ...), (SPUlo ...))
926 // (SPUindirect $sp, imm)
927 EVT VT = N->getValueType(0);
928 SDValue Op0 = N->getOperand(0);
929 SDValue Op1 = N->getOperand(1);
932 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
933 || (Op0.getOpcode() == ISD::Register
934 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
935 && RN->getReg() != SPU::R1))) {
937 if (Op1.getOpcode() == ISD::Constant) {
938 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
939 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
940 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
950 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
952 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
954 return SelectCode(N);
958 * Emit the instruction sequence for i64 left shifts. The basic algorithm
959 * is to fill the bottom two word slots with zeros so that zeros are shifted
960 * in as the entire quadword is shifted left.
962 * \note This code could also be used to implement v2i64 shl.
964 * @param Op The shl operand
965 * @param OpVT Op's machine value value type (doesn't need to be passed, but
966 * makes life easier.)
967 * @return The SDNode with the entire instruction sequence
970 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
971 SDValue Op0 = N->getOperand(0);
972 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
973 OpVT, (128 / OpVT.getSizeInBits()));
974 SDValue ShiftAmt = N->getOperand(1);
975 EVT ShiftAmtVT = ShiftAmt.getValueType();
976 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
978 DebugLoc dl = N->getDebugLoc();
980 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
981 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
982 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
983 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
984 CurDAG->getTargetConstant(0, OpVT));
985 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
986 SDValue(ZeroFill, 0),
988 SDValue(SelMask, 0));
990 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
991 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
992 unsigned bits = unsigned(CN->getZExtValue()) & 7;
996 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
998 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1003 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
1004 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1005 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1009 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1011 CurDAG->getTargetConstant(3, ShiftAmtVT));
1013 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1015 CurDAG->getTargetConstant(7, ShiftAmtVT));
1017 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
1018 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1020 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
1021 SDValue(Shift, 0), SDValue(Bits, 0));
1024 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1028 * Emit the instruction sequence for i64 logical right shifts.
1030 * @param Op The shl operand
1031 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1032 * makes life easier.)
1033 * @return The SDNode with the entire instruction sequence
1036 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
1037 SDValue Op0 = N->getOperand(0);
1038 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1039 OpVT, (128 / OpVT.getSizeInBits()));
1040 SDValue ShiftAmt = N->getOperand(1);
1041 EVT ShiftAmtVT = ShiftAmt.getValueType();
1042 SDNode *VecOp0, *Shift = 0;
1043 DebugLoc dl = N->getDebugLoc();
1045 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1047 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1048 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1049 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1053 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1055 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1060 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1061 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1062 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1066 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1068 CurDAG->getTargetConstant(3, ShiftAmtVT));
1070 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1072 CurDAG->getTargetConstant(7, ShiftAmtVT));
1074 // Ensure that the shift amounts are negated!
1075 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1077 CurDAG->getTargetConstant(0, ShiftAmtVT));
1079 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1081 CurDAG->getTargetConstant(0, ShiftAmtVT));
1084 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1085 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1087 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1088 SDValue(Shift, 0), SDValue(Bits, 0));
1091 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1095 * Emit the instruction sequence for i64 arithmetic right shifts.
1097 * @param Op The shl operand
1098 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1099 * makes life easier.)
1100 * @return The SDNode with the entire instruction sequence
1103 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1104 // Promote Op0 to vector
1105 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1106 OpVT, (128 / OpVT.getSizeInBits()));
1107 SDValue ShiftAmt = N->getOperand(1);
1108 EVT ShiftAmtVT = ShiftAmt.getValueType();
1109 DebugLoc dl = N->getDebugLoc();
1112 CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0));
1114 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1116 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1117 SDValue(VecOp0, 0), SignRotAmt);
1118 SDNode *UpperHalfSign =
1119 CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1121 SDNode *UpperHalfSignMask =
1122 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1123 SDNode *UpperLowerMask =
1124 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1125 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1126 SDNode *UpperLowerSelect =
1127 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1128 SDValue(UpperHalfSignMask, 0),
1130 SDValue(UpperLowerMask, 0));
1134 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1135 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1136 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1141 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1142 SDValue(UpperLowerSelect, 0),
1143 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1149 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1150 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1151 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1155 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1156 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1159 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1160 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1162 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1163 SDValue(Shift, 0), SDValue(NegShift, 0));
1166 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1170 Do the necessary magic necessary to load a i64 constant
1172 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1174 ConstantSDNode *CN = cast<ConstantSDNode>(N);
1175 return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1178 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1180 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1182 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1184 // Here's where it gets interesting, because we have to parse out the
1185 // subtree handed back in i64vec:
1187 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1188 // The degenerate case where the upper and lower bits in the splat are
1190 SDValue Op0 = i64vec.getOperand(0);
1192 ReplaceUses(i64vec, Op0);
1193 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1194 SDValue(emitBuildVector(Op0.getNode()), 0));
1195 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1196 SDValue lhs = i64vec.getOperand(0);
1197 SDValue rhs = i64vec.getOperand(1);
1198 SDValue shufmask = i64vec.getOperand(2);
1200 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1201 ReplaceUses(lhs, lhs.getOperand(0));
1202 lhs = lhs.getOperand(0);
1205 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1207 : emitBuildVector(lhs.getNode()));
1209 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1210 ReplaceUses(rhs, rhs.getOperand(0));
1211 rhs = rhs.getOperand(0);
1214 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1216 : emitBuildVector(rhs.getNode()));
1218 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1219 ReplaceUses(shufmask, shufmask.getOperand(0));
1220 shufmask = shufmask.getOperand(0);
1223 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1224 ? shufmask.getNode()
1225 : emitBuildVector(shufmask.getNode()));
1228 Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1229 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1230 SDValue(shufMaskNode, 0)).getNode());
1232 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1233 SDValue(shufNode, 0));
1234 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1235 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1236 SDValue(emitBuildVector(i64vec.getNode()), 0));
1238 llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1243 /// createSPUISelDag - This pass converts a legalized DAG into a
1244 /// SPU-specific DAG, ready for instruction scheduling.
1246 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1247 return new SPUDAGToDAGISel(TM);