1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/raw_ostream.h"
43 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
45 isI64IntS10Immediate(ConstantSDNode *CN)
47 return isS10Constant(CN->getSExtValue());
50 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
52 isI32IntS10Immediate(ConstantSDNode *CN)
54 return isS10Constant(CN->getSExtValue());
57 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
59 isI32IntU10Immediate(ConstantSDNode *CN)
61 return isU10Constant(CN->getSExtValue());
64 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
66 isI16IntS10Immediate(ConstantSDNode *CN)
68 return isS10Constant(CN->getSExtValue());
71 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(SDNode *N)
75 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
76 return (CN != 0 && isI16IntS10Immediate(CN));
79 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
81 isI16IntU10Immediate(ConstantSDNode *CN)
83 return isU10Constant((short) CN->getZExtValue());
86 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
88 isI16IntU10Immediate(SDNode *N)
90 return (N->getOpcode() == ISD::Constant
91 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
94 //! ConstantSDNode predicate for signed 16-bit values
96 \arg CN The constant SelectionDAG node holding the value
97 \arg Imm The returned 16-bit value, if returning true
99 This predicate tests the value in \a CN to see whether it can be
100 represented as a 16-bit, sign-extended quantity. Returns true if
104 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
106 EVT vt = CN->getValueType(0);
107 Imm = (short) CN->getZExtValue();
108 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
110 } else if (vt == MVT::i32) {
111 int32_t i_val = (int32_t) CN->getZExtValue();
112 short s_val = (short) i_val;
113 return i_val == s_val;
115 int64_t i_val = (int64_t) CN->getZExtValue();
116 short s_val = (short) i_val;
117 return i_val == s_val;
123 //! SDNode predicate for signed 16-bit values.
125 isIntS16Immediate(SDNode *N, short &Imm)
127 return (N->getOpcode() == ISD::Constant
128 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
131 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
133 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
135 EVT vt = FPN->getValueType(0);
136 if (vt == MVT::f32) {
137 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
138 int sval = (int) ((val << 16) >> 16);
147 isHighLow(const SDValue &Op)
149 return (Op.getOpcode() == SPUISD::IndirectAddr
150 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
151 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
152 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
153 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
156 //===------------------------------------------------------------------===//
157 //! EVT to "useful stuff" mapping structure:
159 struct valtype_map_s {
161 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
162 bool ldresult_imm; /// LDRESULT instruction requires immediate?
163 unsigned lrinst; /// LR instruction
166 const valtype_map_s valtype_map[] = {
167 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
168 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
169 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
170 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
171 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
172 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
173 // vector types... (sigh!)
174 { MVT::v16i8, 0, false, SPU::LRv16i8 },
175 { MVT::v8i16, 0, false, SPU::LRv8i16 },
176 { MVT::v4i32, 0, false, SPU::LRv4i32 },
177 { MVT::v2i64, 0, false, SPU::LRv2i64 },
178 { MVT::v4f32, 0, false, SPU::LRv4f32 },
179 { MVT::v2f64, 0, false, SPU::LRv2f64 }
182 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
184 const valtype_map_s *getValueTypeMapEntry(EVT VT)
186 const valtype_map_s *retval = 0;
187 for (size_t i = 0; i < n_valtype_map; ++i) {
188 if (valtype_map[i].VT == VT) {
189 retval = valtype_map + i;
198 raw_string_ostream Msg(msg);
199 Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
200 << VT.getEVTString();
201 llvm_report_error(Msg.str());
208 //! Generate the carry-generate shuffle mask.
209 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
210 SmallVector<SDValue, 16 > ShufBytes;
212 // Create the shuffle mask for "rotating" the borrow up one register slot
213 // once the borrow is generated.
214 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
215 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
216 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
217 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
219 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
220 &ShufBytes[0], ShufBytes.size());
223 //! Generate the borrow-generate shuffle mask
224 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
225 SmallVector<SDValue, 16 > ShufBytes;
227 // Create the shuffle mask for "rotating" the borrow up one register slot
228 // once the borrow is generated.
229 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
230 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
231 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
232 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
234 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
235 &ShufBytes[0], ShufBytes.size());
238 //===------------------------------------------------------------------===//
239 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
240 /// instructions for SelectionDAG operations.
242 class SPUDAGToDAGISel :
243 public SelectionDAGISel
245 SPUTargetMachine &TM;
246 SPUTargetLowering &SPUtli;
247 unsigned GlobalBaseReg;
250 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
251 SelectionDAGISel(tm),
253 SPUtli(*tm.getTargetLowering())
256 virtual bool runOnMachineFunction(MachineFunction &MF) {
257 // Make sure we re-emit a set of the global base reg if necessary
259 SelectionDAGISel::runOnMachineFunction(MF);
263 /// getI32Imm - Return a target constant with the specified value, of type
265 inline SDValue getI32Imm(uint32_t Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i32);
269 /// getI64Imm - Return a target constant with the specified value, of type
271 inline SDValue getI64Imm(uint64_t Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i64);
275 /// getSmallIPtrImm - Return a target constant of pointer type.
276 inline SDValue getSmallIPtrImm(unsigned Imm) {
277 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
280 SDNode *emitBuildVector(SDNode *bvNode) {
281 EVT vecVT = bvNode->getValueType(0);
282 EVT eltVT = vecVT.getVectorElementType();
283 DebugLoc dl = bvNode->getDebugLoc();
285 // Check to see if this vector can be represented as a CellSPU immediate
286 // constant by invoking all of the instruction selection predicates:
287 if (((vecVT == MVT::v8i16) &&
288 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
289 ((vecVT == MVT::v4i32) &&
290 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
291 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
292 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
293 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
294 ((vecVT == MVT::v2i64) &&
295 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
296 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
297 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
298 HandleSDNode Dummy(SDValue(bvNode, 0));
299 if (SDNode *N = Select(bvNode))
301 return Dummy.getValue().getNode();
304 // No, need to emit a constant pool spill:
305 std::vector<Constant*> CV;
307 for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
308 ConstantSDNode *V = dyn_cast<ConstantSDNode > (bvNode->getOperand(i));
309 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
312 Constant *CP = ConstantVector::get(CV);
313 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
314 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
315 SDValue CGPoolOffset =
316 SPU::LowerConstantPool(CPIdx, *CurDAG,
317 SPUtli.getSPUTargetMachine());
319 HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
320 CurDAG->getEntryNode(), CGPoolOffset,
321 PseudoSourceValue::getConstantPool(),0,
322 false, false, Alignment));
323 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
324 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
326 return Dummy.getValue().getNode();
329 /// Select - Convert the specified operand from a target-independent to a
330 /// target-specific node if it hasn't already been changed.
331 SDNode *Select(SDNode *N);
333 //! Emit the instruction sequence for i64 shl
334 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
336 //! Emit the instruction sequence for i64 srl
337 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
339 //! Emit the instruction sequence for i64 sra
340 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
342 //! Emit the necessary sequence for loading i64 constants:
343 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
345 //! Alternate instruction emit sequence for loading i64 constants
346 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
348 //! Returns true if the address N is an A-form (local store) address
349 bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
352 //! D-form address predicate
353 bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
356 /// Alternate D-form address using i7 offset predicate
357 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
360 /// D-form address selection workhorse
361 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
362 SDValue &Base, int minOffset, int maxOffset);
364 //! Address predicate if N can be expressed as an indexed [r+r] operation.
365 bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
368 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
369 /// inline asm expressions.
370 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
372 std::vector<SDValue> &OutOps) {
374 switch (ConstraintCode) {
375 default: return true;
377 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
378 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
379 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
381 case 'o': // offsetable
382 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
383 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
385 Op1 = getSmallIPtrImm(0);
388 case 'v': // not offsetable
390 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
392 SelectAddrIdxOnly(Op, Op, Op0, Op1);
397 OutOps.push_back(Op0);
398 OutOps.push_back(Op1);
402 virtual const char *getPassName() const {
403 return "Cell SPU DAG->DAG Pattern Instruction Selection";
406 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
407 /// this target when scheduling the DAG.
408 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
409 const TargetInstrInfo *II = TM.getInstrInfo();
410 assert(II && "No InstrInfo?");
411 return new SPUHazardRecognizer(*II);
414 // Include the pieces autogenerated from the target description.
415 #include "SPUGenDAGISel.inc"
420 \arg Op The ISD instruction operand
421 \arg N The address to be tested
422 \arg Base The base address
423 \arg Index The base address index
426 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
428 // These match the addr256k operand type:
429 EVT OffsVT = MVT::i16;
430 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
432 switch (N.getOpcode()) {
434 case ISD::ConstantPool:
435 case ISD::GlobalAddress:
436 llvm_report_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
439 case ISD::TargetConstant:
440 case ISD::TargetGlobalAddress:
441 case ISD::TargetJumpTable:
442 llvm_report_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
443 "not wrapped as A-form address.");
446 case SPUISD::AFormAddr:
447 // Just load from memory if there's only a single use of the location,
448 // otherwise, this will get handled below with D-form offset addresses
450 SDValue Op0 = N.getOperand(0);
451 switch (Op0.getOpcode()) {
452 case ISD::TargetConstantPool:
453 case ISD::TargetJumpTable:
458 case ISD::TargetGlobalAddress: {
459 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
460 GlobalValue *GV = GSDN->getGlobal();
461 if (GV->getAlignment() == 16) {
476 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
478 const int minDForm2Offset = -(1 << 7);
479 const int maxDForm2Offset = (1 << 7) - 1;
480 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
485 \arg Op The ISD instruction (ignored)
486 \arg N The address to be tested
487 \arg Base Base address register/pointer
488 \arg Index Base address index
490 Examine the input address by a base register plus a signed 10-bit
491 displacement, [r+I10] (D-form address).
493 \return true if \a N is a D-form address with \a Base and \a Index set
494 to non-empty SDValue instances.
497 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
499 return DFormAddressPredicate(Op, N, Base, Index,
500 SPUFrameInfo::minFrameOffset(),
501 SPUFrameInfo::maxFrameOffset());
505 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
506 SDValue &Index, int minOffset,
508 unsigned Opc = N.getOpcode();
509 EVT PtrTy = SPUtli.getPointerTy();
511 if (Opc == ISD::FrameIndex) {
512 // Stack frame index must be less than 512 (divided by 16):
513 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
514 int FI = int(FIN->getIndex());
515 DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
517 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
518 Base = CurDAG->getTargetConstant(0, PtrTy);
519 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
522 } else if (Opc == ISD::ADD) {
523 // Generated by getelementptr
524 const SDValue Op0 = N.getOperand(0);
525 const SDValue Op1 = N.getOperand(1);
527 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
528 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
529 Base = CurDAG->getTargetConstant(0, PtrTy);
532 } else if (Op1.getOpcode() == ISD::Constant
533 || Op1.getOpcode() == ISD::TargetConstant) {
534 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
535 int32_t offset = int32_t(CN->getSExtValue());
537 if (Op0.getOpcode() == ISD::FrameIndex) {
538 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
539 int FI = int(FIN->getIndex());
540 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
541 << " frame index = " << FI << "\n");
543 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
544 Base = CurDAG->getTargetConstant(offset, PtrTy);
545 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
548 } else if (offset > minOffset && offset < maxOffset) {
549 Base = CurDAG->getTargetConstant(offset, PtrTy);
553 } else if (Op0.getOpcode() == ISD::Constant
554 || Op0.getOpcode() == ISD::TargetConstant) {
555 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
556 int32_t offset = int32_t(CN->getSExtValue());
558 if (Op1.getOpcode() == ISD::FrameIndex) {
559 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
560 int FI = int(FIN->getIndex());
561 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
562 << " frame index = " << FI << "\n");
564 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
565 Base = CurDAG->getTargetConstant(offset, PtrTy);
566 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
569 } else if (offset > minOffset && offset < maxOffset) {
570 Base = CurDAG->getTargetConstant(offset, PtrTy);
575 } else if (Opc == SPUISD::IndirectAddr) {
576 // Indirect with constant offset -> D-Form address
577 const SDValue Op0 = N.getOperand(0);
578 const SDValue Op1 = N.getOperand(1);
580 if (Op0.getOpcode() == SPUISD::Hi
581 && Op1.getOpcode() == SPUISD::Lo) {
582 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
583 Base = CurDAG->getTargetConstant(0, PtrTy);
586 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
590 if (isa<ConstantSDNode>(Op1)) {
591 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
592 offset = int32_t(CN->getSExtValue());
594 } else if (isa<ConstantSDNode>(Op0)) {
595 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
596 offset = int32_t(CN->getSExtValue());
600 if (offset >= minOffset && offset <= maxOffset) {
601 Base = CurDAG->getTargetConstant(offset, PtrTy);
606 } else if (Opc == SPUISD::AFormAddr) {
607 Base = CurDAG->getTargetConstant(0, N.getValueType());
610 } else if (Opc == SPUISD::LDRESULT) {
611 Base = CurDAG->getTargetConstant(0, N.getValueType());
614 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
615 unsigned OpOpc = Op->getOpcode();
617 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
618 // Direct load/store without getelementptr
621 // Get the register from CopyFromReg
622 if (Opc == ISD::CopyFromReg)
623 Addr = N.getOperand(1);
625 Addr = N; // Register
627 Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
629 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
630 if (Offs.getOpcode() == ISD::UNDEF)
631 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
638 /* If otherwise unadorned, default to D-form address with 0 offset: */
639 if (Opc == ISD::CopyFromReg) {
640 Index = N.getOperand(1);
645 Base = CurDAG->getTargetConstant(0, Index.getValueType());
654 \arg Op The ISD instruction operand
655 \arg N The address operand
656 \arg Base The base pointer operand
657 \arg Index The offset/index operand
659 If the address \a N can be expressed as an A-form or D-form address, returns
660 false. Otherwise, creates two operands, Base and Index that will become the
661 (r)(r) X-form address.
664 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
666 if (!SelectAFormAddr(Op, N, Base, Index)
667 && !SelectDFormAddr(Op, N, Base, Index)) {
668 // If the address is neither A-form or D-form, punt and use an X-form
670 Base = N.getOperand(1);
671 Index = N.getOperand(0);
678 //! Convert the operand from a target-independent to a target-specific node
682 SPUDAGToDAGISel::Select(SDNode *N) {
683 unsigned Opc = N->getOpcode();
686 EVT OpVT = N->getValueType(0);
688 DebugLoc dl = N->getDebugLoc();
690 if (N->isMachineOpcode())
691 return NULL; // Already selected.
693 if (Opc == ISD::FrameIndex) {
694 int FI = cast<FrameIndexSDNode>(N)->getIndex();
695 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
696 SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
705 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
706 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
707 N->getValueType(0), TFI, Imm0),
711 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
712 // Catch the i64 constants that end up here. Note: The backend doesn't
713 // attempt to legalize the constant (it's useless because DAGCombiner
714 // will insert 64-bit constants and we can't stop it).
715 return SelectI64Constant(N, OpVT, N->getDebugLoc());
716 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
717 && OpVT == MVT::i64) {
718 SDValue Op0 = N->getOperand(0);
719 EVT Op0VT = Op0.getValueType();
720 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
721 Op0VT, (128 / Op0VT.getSizeInBits()));
722 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
723 OpVT, (128 / OpVT.getSizeInBits()));
726 switch (Op0VT.getSimpleVT().SimpleTy) {
728 llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
731 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
732 CurDAG->getConstant(0x80808080, MVT::i32),
733 CurDAG->getConstant(0x00010203, MVT::i32),
734 CurDAG->getConstant(0x80808080, MVT::i32),
735 CurDAG->getConstant(0x08090a0b, MVT::i32));
739 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
740 CurDAG->getConstant(0x80808080, MVT::i32),
741 CurDAG->getConstant(0x80800203, MVT::i32),
742 CurDAG->getConstant(0x80808080, MVT::i32),
743 CurDAG->getConstant(0x80800a0b, MVT::i32));
747 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
748 CurDAG->getConstant(0x80808080, MVT::i32),
749 CurDAG->getConstant(0x80808003, MVT::i32),
750 CurDAG->getConstant(0x80808080, MVT::i32),
751 CurDAG->getConstant(0x8080800b, MVT::i32));
755 SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
757 HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
761 if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
762 PromScalar = SDValue(N, 0);
764 PromScalar = PromoteScalar.getValue();
766 SDValue zextShuffle =
767 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
768 PromScalar, PromScalar,
769 SDValue(shufMaskLoad, 0));
771 HandleSDNode Dummy2(zextShuffle);
772 if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
773 zextShuffle = SDValue(N, 0);
775 zextShuffle = Dummy2.getValue();
776 HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
779 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
780 SelectCode(Dummy.getValue().getNode());
781 return Dummy.getValue().getNode();
782 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
784 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
786 HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
787 N->getOperand(0), N->getOperand(1),
788 SDValue(CGLoad, 0)));
790 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
791 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
793 return Dummy.getValue().getNode();
794 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
796 emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
798 HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
799 N->getOperand(0), N->getOperand(1),
800 SDValue(CGLoad, 0)));
802 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
803 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
805 return Dummy.getValue().getNode();
806 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
808 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
810 HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
811 N->getOperand(0), N->getOperand(1),
812 SDValue(CGLoad, 0)));
813 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
814 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
816 return Dummy.getValue().getNode();
817 } else if (Opc == ISD::TRUNCATE) {
818 SDValue Op0 = N->getOperand(0);
819 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
821 && Op0.getValueType() == MVT::i64) {
822 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
824 // Take advantage of the fact that the upper 32 bits are in the
825 // i32 preferred slot and avoid shuffle gymnastics:
826 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
828 unsigned shift_amt = unsigned(CN->getZExtValue());
830 if (shift_amt >= 32) {
832 CurDAG->getMachineNode(SPU::ORr32_r64, dl, OpVT,
837 // Take care of the additional shift, if present:
838 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
839 unsigned Opc = SPU::ROTMAIr32_i32;
841 if (Op0.getOpcode() == ISD::SRL)
844 hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
852 } else if (Opc == ISD::SHL) {
853 if (OpVT == MVT::i64)
854 return SelectSHLi64(N, OpVT);
855 } else if (Opc == ISD::SRL) {
856 if (OpVT == MVT::i64)
857 return SelectSRLi64(N, OpVT);
858 } else if (Opc == ISD::SRA) {
859 if (OpVT == MVT::i64)
860 return SelectSRAi64(N, OpVT);
861 } else if (Opc == ISD::FNEG
862 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
863 DebugLoc dl = N->getDebugLoc();
864 // Check if the pattern is a special form of DFNMS:
865 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
866 SDValue Op0 = N->getOperand(0);
867 if (Op0.getOpcode() == ISD::FSUB) {
868 SDValue Op00 = Op0.getOperand(0);
869 if (Op00.getOpcode() == ISD::FMUL) {
870 unsigned Opc = SPU::DFNMSf64;
871 if (OpVT == MVT::v2f64)
872 Opc = SPU::DFNMSv2f64;
874 return CurDAG->getMachineNode(Opc, dl, OpVT,
881 SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
882 SDNode *signMask = 0;
883 unsigned Opc = SPU::XORfneg64;
885 if (OpVT == MVT::f64) {
886 signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
887 } else if (OpVT == MVT::v2f64) {
888 Opc = SPU::XORfnegvec;
889 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
891 negConst, negConst).getNode());
894 return CurDAG->getMachineNode(Opc, dl, OpVT,
895 N->getOperand(0), SDValue(signMask, 0));
896 } else if (Opc == ISD::FABS) {
897 if (OpVT == MVT::f64) {
898 SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
899 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
900 N->getOperand(0), SDValue(signMask, 0));
901 } else if (OpVT == MVT::v2f64) {
902 SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
903 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
905 SDNode *signMask = emitBuildVector(absVec.getNode());
906 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
907 N->getOperand(0), SDValue(signMask, 0));
909 } else if (Opc == SPUISD::LDRESULT) {
910 // Custom select instructions for LDRESULT
911 EVT VT = N->getValueType(0);
912 SDValue Arg = N->getOperand(0);
913 SDValue Chain = N->getOperand(1);
915 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
917 if (vtm->ldresult_ins == 0) {
919 raw_string_ostream Msg(msg);
920 Msg << "LDRESULT for unsupported type: "
921 << VT.getEVTString();
922 llvm_report_error(Msg.str());
925 Opc = vtm->ldresult_ins;
926 if (vtm->ldresult_imm) {
927 SDValue Zero = CurDAG->getTargetConstant(0, VT);
929 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
931 Result = CurDAG->getMachineNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
935 } else if (Opc == SPUISD::IndirectAddr) {
936 // Look at the operands: SelectCode() will catch the cases that aren't
937 // specifically handled here.
939 // SPUInstrInfo catches the following patterns:
940 // (SPUindirect (SPUhi ...), (SPUlo ...))
941 // (SPUindirect $sp, imm)
942 EVT VT = N->getValueType(0);
943 SDValue Op0 = N->getOperand(0);
944 SDValue Op1 = N->getOperand(1);
947 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
948 || (Op0.getOpcode() == ISD::Register
949 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
950 && RN->getReg() != SPU::R1))) {
952 if (Op1.getOpcode() == ISD::Constant) {
953 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
954 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
955 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
965 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
967 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
969 return SelectCode(N);
973 * Emit the instruction sequence for i64 left shifts. The basic algorithm
974 * is to fill the bottom two word slots with zeros so that zeros are shifted
975 * in as the entire quadword is shifted left.
977 * \note This code could also be used to implement v2i64 shl.
979 * @param Op The shl operand
980 * @param OpVT Op's machine value value type (doesn't need to be passed, but
981 * makes life easier.)
982 * @return The SDNode with the entire instruction sequence
985 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
986 SDValue Op0 = N->getOperand(0);
987 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
988 OpVT, (128 / OpVT.getSizeInBits()));
989 SDValue ShiftAmt = N->getOperand(1);
990 EVT ShiftAmtVT = ShiftAmt.getValueType();
991 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
993 DebugLoc dl = N->getDebugLoc();
995 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
996 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
997 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
998 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
999 CurDAG->getTargetConstant(0, OpVT));
1000 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1001 SDValue(ZeroFill, 0),
1003 SDValue(SelMask, 0));
1005 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1006 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1007 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1011 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
1013 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1018 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
1019 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1020 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1024 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1026 CurDAG->getTargetConstant(3, ShiftAmtVT));
1028 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1030 CurDAG->getTargetConstant(7, ShiftAmtVT));
1032 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
1033 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1035 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
1036 SDValue(Shift, 0), SDValue(Bits, 0));
1039 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1043 * Emit the instruction sequence for i64 logical right shifts.
1045 * @param Op The shl operand
1046 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1047 * makes life easier.)
1048 * @return The SDNode with the entire instruction sequence
1051 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
1052 SDValue Op0 = N->getOperand(0);
1053 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1054 OpVT, (128 / OpVT.getSizeInBits()));
1055 SDValue ShiftAmt = N->getOperand(1);
1056 EVT ShiftAmtVT = ShiftAmt.getValueType();
1057 SDNode *VecOp0, *Shift = 0;
1058 DebugLoc dl = N->getDebugLoc();
1060 VecOp0 = CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1062 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1063 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1064 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1068 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1070 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1075 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1076 SDValue((Shift != 0 ? Shift : VecOp0), 0),
1077 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1081 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1083 CurDAG->getTargetConstant(3, ShiftAmtVT));
1085 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1087 CurDAG->getTargetConstant(7, ShiftAmtVT));
1089 // Ensure that the shift amounts are negated!
1090 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1092 CurDAG->getTargetConstant(0, ShiftAmtVT));
1094 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1096 CurDAG->getTargetConstant(0, ShiftAmtVT));
1099 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1100 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1102 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1103 SDValue(Shift, 0), SDValue(Bits, 0));
1106 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1110 * Emit the instruction sequence for i64 arithmetic right shifts.
1112 * @param Op The shl operand
1113 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1114 * makes life easier.)
1115 * @return The SDNode with the entire instruction sequence
1118 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1119 // Promote Op0 to vector
1120 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1121 OpVT, (128 / OpVT.getSizeInBits()));
1122 SDValue ShiftAmt = N->getOperand(1);
1123 EVT ShiftAmtVT = ShiftAmt.getValueType();
1124 DebugLoc dl = N->getDebugLoc();
1127 CurDAG->getMachineNode(SPU::ORv2i64_i64, dl, VecVT, N->getOperand(0));
1129 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1131 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1132 SDValue(VecOp0, 0), SignRotAmt);
1133 SDNode *UpperHalfSign =
1134 CurDAG->getMachineNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1136 SDNode *UpperHalfSignMask =
1137 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1138 SDNode *UpperLowerMask =
1139 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1140 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1141 SDNode *UpperLowerSelect =
1142 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1143 SDValue(UpperHalfSignMask, 0),
1145 SDValue(UpperLowerMask, 0));
1149 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1150 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1151 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1156 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1157 SDValue(UpperLowerSelect, 0),
1158 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1164 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1165 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1166 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1170 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1171 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1174 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1175 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1177 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1178 SDValue(Shift, 0), SDValue(NegShift, 0));
1181 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1185 Do the necessary magic necessary to load a i64 constant
1187 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1189 ConstantSDNode *CN = cast<ConstantSDNode>(N);
1190 return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1193 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1195 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1197 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1199 // Here's where it gets interesting, because we have to parse out the
1200 // subtree handed back in i64vec:
1202 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1203 // The degenerate case where the upper and lower bits in the splat are
1205 SDValue Op0 = i64vec.getOperand(0);
1207 ReplaceUses(i64vec, Op0);
1208 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1209 SDValue(emitBuildVector(Op0.getNode()), 0));
1210 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1211 SDValue lhs = i64vec.getOperand(0);
1212 SDValue rhs = i64vec.getOperand(1);
1213 SDValue shufmask = i64vec.getOperand(2);
1215 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1216 ReplaceUses(lhs, lhs.getOperand(0));
1217 lhs = lhs.getOperand(0);
1220 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1222 : emitBuildVector(lhs.getNode()));
1224 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1225 ReplaceUses(rhs, rhs.getOperand(0));
1226 rhs = rhs.getOperand(0);
1229 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1231 : emitBuildVector(rhs.getNode()));
1233 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1234 ReplaceUses(shufmask, shufmask.getOperand(0));
1235 shufmask = shufmask.getOperand(0);
1238 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1239 ? shufmask.getNode()
1240 : emitBuildVector(shufmask.getNode()));
1243 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1244 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1245 SDValue(shufMaskNode, 0));
1246 HandleSDNode Dummy(shufNode);
1247 SDNode *SN = SelectCode(Dummy.getValue().getNode());
1248 if (SN == 0) SN = Dummy.getValue().getNode();
1250 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(SN, 0));
1251 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1252 return CurDAG->getMachineNode(SPU::ORi64_v2i64, dl, OpVT,
1253 SDValue(emitBuildVector(i64vec.getNode()), 0));
1255 llvm_report_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1260 /// createSPUISelDag - This pass converts a legalized DAG into a
1261 /// SPU-specific DAG, ready for instruction scheduling.
1263 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1264 return new SPUDAGToDAGISel(TM);