1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "SPUFrameInfo.h"
19 #include "SPURegisterNames.h"
20 #include "SPUTargetMachine.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Constants.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/raw_ostream.h"
42 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
44 isI32IntS10Immediate(ConstantSDNode *CN)
46 return isInt<10>(CN->getSExtValue());
49 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
51 isI32IntU10Immediate(ConstantSDNode *CN)
53 return isUInt<10>(CN->getSExtValue());
56 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
58 isI16IntS10Immediate(ConstantSDNode *CN)
60 return isInt<10>(CN->getSExtValue());
63 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
65 isI16IntU10Immediate(ConstantSDNode *CN)
67 return isUInt<10>((short) CN->getZExtValue());
70 //! ConstantSDNode predicate for signed 16-bit values
72 \arg CN The constant SelectionDAG node holding the value
73 \arg Imm The returned 16-bit value, if returning true
75 This predicate tests the value in \a CN to see whether it can be
76 represented as a 16-bit, sign-extended quantity. Returns true if
80 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
82 EVT vt = CN->getValueType(0);
83 Imm = (short) CN->getZExtValue();
84 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
86 } else if (vt == MVT::i32) {
87 int32_t i_val = (int32_t) CN->getZExtValue();
88 short s_val = (short) i_val;
89 return i_val == s_val;
91 int64_t i_val = (int64_t) CN->getZExtValue();
92 short s_val = (short) i_val;
93 return i_val == s_val;
99 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
101 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
103 EVT vt = FPN->getValueType(0);
104 if (vt == MVT::f32) {
105 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
106 int sval = (int) ((val << 16) >> 16);
114 //! Generate the carry-generate shuffle mask.
115 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
116 SmallVector<SDValue, 16 > ShufBytes;
118 // Create the shuffle mask for "rotating" the borrow up one register slot
119 // once the borrow is generated.
120 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
121 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
122 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
123 ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
125 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
126 &ShufBytes[0], ShufBytes.size());
129 //! Generate the borrow-generate shuffle mask
130 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
131 SmallVector<SDValue, 16 > ShufBytes;
133 // Create the shuffle mask for "rotating" the borrow up one register slot
134 // once the borrow is generated.
135 ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
136 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
137 ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
138 ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
140 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
141 &ShufBytes[0], ShufBytes.size());
144 //===------------------------------------------------------------------===//
145 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
146 /// instructions for SelectionDAG operations.
148 class SPUDAGToDAGISel :
149 public SelectionDAGISel
151 const SPUTargetMachine &TM;
152 const SPUTargetLowering &SPUtli;
153 unsigned GlobalBaseReg;
156 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
157 SelectionDAGISel(tm),
159 SPUtli(*tm.getTargetLowering())
162 virtual bool runOnMachineFunction(MachineFunction &MF) {
163 // Make sure we re-emit a set of the global base reg if necessary
165 SelectionDAGISel::runOnMachineFunction(MF);
169 /// getI32Imm - Return a target constant with the specified value, of type
171 inline SDValue getI32Imm(uint32_t Imm) {
172 return CurDAG->getTargetConstant(Imm, MVT::i32);
175 /// getSmallIPtrImm - Return a target constant of pointer type.
176 inline SDValue getSmallIPtrImm(unsigned Imm) {
177 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
180 SDNode *emitBuildVector(SDNode *bvNode) {
181 EVT vecVT = bvNode->getValueType(0);
182 DebugLoc dl = bvNode->getDebugLoc();
184 // Check to see if this vector can be represented as a CellSPU immediate
185 // constant by invoking all of the instruction selection predicates:
186 if (((vecVT == MVT::v8i16) &&
187 (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
188 ((vecVT == MVT::v4i32) &&
189 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
191 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
192 (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
193 ((vecVT == MVT::v2i64) &&
194 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
195 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
196 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
197 HandleSDNode Dummy(SDValue(bvNode, 0));
198 if (SDNode *N = Select(bvNode))
200 return Dummy.getValue().getNode();
203 // No, need to emit a constant pool spill:
204 std::vector<Constant*> CV;
206 for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
207 ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
208 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
211 const Constant *CP = ConstantVector::get(CV);
212 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
213 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
214 SDValue CGPoolOffset =
215 SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
217 HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
218 CurDAG->getEntryNode(), CGPoolOffset,
219 MachinePointerInfo::getConstantPool(),
220 false, false, Alignment));
221 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
222 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
224 return Dummy.getValue().getNode();
227 /// Select - Convert the specified operand from a target-independent to a
228 /// target-specific node if it hasn't already been changed.
229 SDNode *Select(SDNode *N);
231 //! Emit the instruction sequence for i64 shl
232 SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
234 //! Emit the instruction sequence for i64 srl
235 SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
237 //! Emit the instruction sequence for i64 sra
238 SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
240 //! Emit the necessary sequence for loading i64 constants:
241 SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
243 //! Alternate instruction emit sequence for loading i64 constants
244 SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
246 //! Returns true if the address N is an A-form (local store) address
247 bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
250 //! D-form address predicate
251 bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
254 /// Alternate D-form address using i7 offset predicate
255 bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
258 /// D-form address selection workhorse
259 bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
260 SDValue &Base, int minOffset, int maxOffset);
262 //! Address predicate if N can be expressed as an indexed [r+r] operation.
263 bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
266 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
267 /// inline asm expressions.
268 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
270 std::vector<SDValue> &OutOps) {
272 switch (ConstraintCode) {
273 default: return true;
275 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
276 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
277 SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
279 case 'o': // offsetable
280 if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
281 && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
283 Op1 = getSmallIPtrImm(0);
286 case 'v': // not offsetable
288 llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
290 SelectAddrIdxOnly(Op, Op, Op0, Op1);
295 OutOps.push_back(Op0);
296 OutOps.push_back(Op1);
300 virtual const char *getPassName() const {
301 return "Cell SPU DAG->DAG Pattern Instruction Selection";
304 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
305 /// this target when scheduling the DAG.
306 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
307 const TargetInstrInfo *II = TM.getInstrInfo();
308 assert(II && "No InstrInfo?");
309 return new SPUHazardRecognizer(*II);
313 SDValue getRC( MVT );
315 // Include the pieces autogenerated from the target description.
316 #include "SPUGenDAGISel.inc"
321 \arg Op The ISD instruction operand
322 \arg N The address to be tested
323 \arg Base The base address
324 \arg Index The base address index
327 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
329 // These match the addr256k operand type:
330 EVT OffsVT = MVT::i16;
331 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
333 switch (N.getOpcode()) {
335 case ISD::ConstantPool:
336 case ISD::GlobalAddress:
337 report_fatal_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
340 case ISD::TargetConstant:
341 case ISD::TargetGlobalAddress:
342 case ISD::TargetJumpTable:
343 report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
344 "not wrapped as A-form address.");
347 case SPUISD::AFormAddr:
348 // Just load from memory if there's only a single use of the location,
349 // otherwise, this will get handled below with D-form offset addresses
351 SDValue Op0 = N.getOperand(0);
352 switch (Op0.getOpcode()) {
353 case ISD::TargetConstantPool:
354 case ISD::TargetJumpTable:
359 case ISD::TargetGlobalAddress: {
360 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
361 const GlobalValue *GV = GSDN->getGlobal();
362 if (GV->getAlignment() == 16) {
377 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
379 const int minDForm2Offset = -(1 << 7);
380 const int maxDForm2Offset = (1 << 7) - 1;
381 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
386 \arg Op The ISD instruction (ignored)
387 \arg N The address to be tested
388 \arg Base Base address register/pointer
389 \arg Index Base address index
391 Examine the input address by a base register plus a signed 10-bit
392 displacement, [r+I10] (D-form address).
394 \return true if \a N is a D-form address with \a Base and \a Index set
395 to non-empty SDValue instances.
398 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
400 return DFormAddressPredicate(Op, N, Base, Index,
401 SPUFrameInfo::minFrameOffset(),
402 SPUFrameInfo::maxFrameOffset());
406 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
407 SDValue &Index, int minOffset,
409 unsigned Opc = N.getOpcode();
410 EVT PtrTy = SPUtli.getPointerTy();
412 if (Opc == ISD::FrameIndex) {
413 // Stack frame index must be less than 512 (divided by 16):
414 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
415 int FI = int(FIN->getIndex());
416 DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
418 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
419 Base = CurDAG->getTargetConstant(0, PtrTy);
420 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
423 } else if (Opc == ISD::ADD) {
424 // Generated by getelementptr
425 const SDValue Op0 = N.getOperand(0);
426 const SDValue Op1 = N.getOperand(1);
428 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
429 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
430 Base = CurDAG->getTargetConstant(0, PtrTy);
433 } else if (Op1.getOpcode() == ISD::Constant
434 || Op1.getOpcode() == ISD::TargetConstant) {
435 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
436 int32_t offset = int32_t(CN->getSExtValue());
438 if (Op0.getOpcode() == ISD::FrameIndex) {
439 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
440 int FI = int(FIN->getIndex());
441 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
442 << " frame index = " << FI << "\n");
444 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
445 Base = CurDAG->getTargetConstant(offset, PtrTy);
446 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
449 } else if (offset > minOffset && offset < maxOffset) {
450 Base = CurDAG->getTargetConstant(offset, PtrTy);
454 } else if (Op0.getOpcode() == ISD::Constant
455 || Op0.getOpcode() == ISD::TargetConstant) {
456 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
457 int32_t offset = int32_t(CN->getSExtValue());
459 if (Op1.getOpcode() == ISD::FrameIndex) {
460 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
461 int FI = int(FIN->getIndex());
462 DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
463 << " frame index = " << FI << "\n");
465 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
466 Base = CurDAG->getTargetConstant(offset, PtrTy);
467 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
470 } else if (offset > minOffset && offset < maxOffset) {
471 Base = CurDAG->getTargetConstant(offset, PtrTy);
476 } else if (Opc == SPUISD::IndirectAddr) {
477 // Indirect with constant offset -> D-Form address
478 const SDValue Op0 = N.getOperand(0);
479 const SDValue Op1 = N.getOperand(1);
481 if (Op0.getOpcode() == SPUISD::Hi
482 && Op1.getOpcode() == SPUISD::Lo) {
483 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
484 Base = CurDAG->getTargetConstant(0, PtrTy);
487 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
491 if (isa<ConstantSDNode>(Op1)) {
492 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
493 offset = int32_t(CN->getSExtValue());
495 } else if (isa<ConstantSDNode>(Op0)) {
496 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
497 offset = int32_t(CN->getSExtValue());
501 if (offset >= minOffset && offset <= maxOffset) {
502 Base = CurDAG->getTargetConstant(offset, PtrTy);
507 } else if (Opc == SPUISD::AFormAddr) {
508 Base = CurDAG->getTargetConstant(0, N.getValueType());
511 } else if (Opc == SPUISD::LDRESULT) {
512 Base = CurDAG->getTargetConstant(0, N.getValueType());
515 } else if (Opc == ISD::Register
516 ||Opc == ISD::CopyFromReg
518 ||Opc == ISD::Constant) {
519 unsigned OpOpc = Op->getOpcode();
521 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
522 // Direct load/store without getelementptr
525 Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
527 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
528 if (Offs.getOpcode() == ISD::UNDEF)
529 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
536 /* If otherwise unadorned, default to D-form address with 0 offset: */
537 if (Opc == ISD::CopyFromReg) {
538 Index = N.getOperand(1);
543 Base = CurDAG->getTargetConstant(0, Index.getValueType());
552 \arg Op The ISD instruction operand
553 \arg N The address operand
554 \arg Base The base pointer operand
555 \arg Index The offset/index operand
557 If the address \a N can be expressed as an A-form or D-form address, returns
558 false. Otherwise, creates two operands, Base and Index that will become the
559 (r)(r) X-form address.
562 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
564 if (!SelectAFormAddr(Op, N, Base, Index)
565 && !SelectDFormAddr(Op, N, Base, Index)) {
566 // If the address is neither A-form or D-form, punt and use an X-form
568 Base = N.getOperand(1);
569 Index = N.getOperand(0);
577 Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue
578 to be used as the last parameter of a
579 CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call
580 \arg VT the value type for which we want a register class
582 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
583 switch( VT.SimpleTy ) {
585 return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
588 return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
591 return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
594 assert( false && "add a new case here" );
599 //! Convert the operand from a target-independent to a target-specific node
603 SPUDAGToDAGISel::Select(SDNode *N) {
604 unsigned Opc = N->getOpcode();
607 EVT OpVT = N->getValueType(0);
609 DebugLoc dl = N->getDebugLoc();
611 if (N->isMachineOpcode())
612 return NULL; // Already selected.
614 if (Opc == ISD::FrameIndex) {
615 int FI = cast<FrameIndexSDNode>(N)->getIndex();
616 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
617 SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
626 Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
627 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
628 N->getValueType(0), TFI, Imm0),
632 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
633 // Catch the i64 constants that end up here. Note: The backend doesn't
634 // attempt to legalize the constant (it's useless because DAGCombiner
635 // will insert 64-bit constants and we can't stop it).
636 return SelectI64Constant(N, OpVT, N->getDebugLoc());
637 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
638 && OpVT == MVT::i64) {
639 SDValue Op0 = N->getOperand(0);
640 EVT Op0VT = Op0.getValueType();
641 EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
642 Op0VT, (128 / Op0VT.getSizeInBits()));
643 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
644 OpVT, (128 / OpVT.getSizeInBits()));
647 switch (Op0VT.getSimpleVT().SimpleTy) {
649 report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
652 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
653 CurDAG->getConstant(0x80808080, MVT::i32),
654 CurDAG->getConstant(0x00010203, MVT::i32),
655 CurDAG->getConstant(0x80808080, MVT::i32),
656 CurDAG->getConstant(0x08090a0b, MVT::i32));
660 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
661 CurDAG->getConstant(0x80808080, MVT::i32),
662 CurDAG->getConstant(0x80800203, MVT::i32),
663 CurDAG->getConstant(0x80808080, MVT::i32),
664 CurDAG->getConstant(0x80800a0b, MVT::i32));
668 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
669 CurDAG->getConstant(0x80808080, MVT::i32),
670 CurDAG->getConstant(0x80808003, MVT::i32),
671 CurDAG->getConstant(0x80808080, MVT::i32),
672 CurDAG->getConstant(0x8080800b, MVT::i32));
676 SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
678 HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
682 if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
683 PromScalar = SDValue(N, 0);
685 PromScalar = PromoteScalar.getValue();
687 SDValue zextShuffle =
688 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
689 PromScalar, PromScalar,
690 SDValue(shufMaskLoad, 0));
692 HandleSDNode Dummy2(zextShuffle);
693 if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
694 zextShuffle = SDValue(N, 0);
696 zextShuffle = Dummy2.getValue();
697 HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
700 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
701 SelectCode(Dummy.getValue().getNode());
702 return Dummy.getValue().getNode();
703 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
705 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
707 HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
708 N->getOperand(0), N->getOperand(1),
709 SDValue(CGLoad, 0)));
711 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
712 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
714 return Dummy.getValue().getNode();
715 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
717 emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
719 HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
720 N->getOperand(0), N->getOperand(1),
721 SDValue(CGLoad, 0)));
723 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
724 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
726 return Dummy.getValue().getNode();
727 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
729 emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
731 HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
732 N->getOperand(0), N->getOperand(1),
733 SDValue(CGLoad, 0)));
734 CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
735 if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
737 return Dummy.getValue().getNode();
738 } else if (Opc == ISD::TRUNCATE) {
739 SDValue Op0 = N->getOperand(0);
740 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
742 && Op0.getValueType() == MVT::i64) {
743 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
745 // Take advantage of the fact that the upper 32 bits are in the
746 // i32 preferred slot and avoid shuffle gymnastics:
747 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
749 unsigned shift_amt = unsigned(CN->getZExtValue());
751 if (shift_amt >= 32) {
753 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
754 Op0.getOperand(0), getRC(MVT::i32));
758 // Take care of the additional shift, if present:
759 SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
760 unsigned Opc = SPU::ROTMAIr32_i32;
762 if (Op0.getOpcode() == ISD::SRL)
765 hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
773 } else if (Opc == ISD::SHL) {
774 if (OpVT == MVT::i64)
775 return SelectSHLi64(N, OpVT);
776 } else if (Opc == ISD::SRL) {
777 if (OpVT == MVT::i64)
778 return SelectSRLi64(N, OpVT);
779 } else if (Opc == ISD::SRA) {
780 if (OpVT == MVT::i64)
781 return SelectSRAi64(N, OpVT);
782 } else if (Opc == ISD::FNEG
783 && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
784 DebugLoc dl = N->getDebugLoc();
785 // Check if the pattern is a special form of DFNMS:
786 // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
787 SDValue Op0 = N->getOperand(0);
788 if (Op0.getOpcode() == ISD::FSUB) {
789 SDValue Op00 = Op0.getOperand(0);
790 if (Op00.getOpcode() == ISD::FMUL) {
791 unsigned Opc = SPU::DFNMSf64;
792 if (OpVT == MVT::v2f64)
793 Opc = SPU::DFNMSv2f64;
795 return CurDAG->getMachineNode(Opc, dl, OpVT,
802 SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
803 SDNode *signMask = 0;
804 unsigned Opc = SPU::XORfneg64;
806 if (OpVT == MVT::f64) {
807 signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
808 } else if (OpVT == MVT::v2f64) {
809 Opc = SPU::XORfnegvec;
810 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
812 negConst, negConst).getNode());
815 return CurDAG->getMachineNode(Opc, dl, OpVT,
816 N->getOperand(0), SDValue(signMask, 0));
817 } else if (Opc == ISD::FABS) {
818 if (OpVT == MVT::f64) {
819 SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
820 return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
821 N->getOperand(0), SDValue(signMask, 0));
822 } else if (OpVT == MVT::v2f64) {
823 SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
824 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
826 SDNode *signMask = emitBuildVector(absVec.getNode());
827 return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
828 N->getOperand(0), SDValue(signMask, 0));
830 } else if (Opc == SPUISD::LDRESULT) {
831 // Custom select instructions for LDRESULT
832 EVT VT = N->getValueType(0);
833 SDValue Arg = N->getOperand(0);
834 SDValue Chain = N->getOperand(1);
837 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
839 getRC( VT.getSimpleVT()), Chain);
842 } else if (Opc == SPUISD::IndirectAddr) {
843 // Look at the operands: SelectCode() will catch the cases that aren't
844 // specifically handled here.
846 // SPUInstrInfo catches the following patterns:
847 // (SPUindirect (SPUhi ...), (SPUlo ...))
848 // (SPUindirect $sp, imm)
849 EVT VT = N->getValueType(0);
850 SDValue Op0 = N->getOperand(0);
851 SDValue Op1 = N->getOperand(1);
854 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
855 || (Op0.getOpcode() == ISD::Register
856 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
857 && RN->getReg() != SPU::R1))) {
860 if (Op1.getOpcode() == ISD::Constant) {
861 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
862 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
863 if (isInt<10>(CN->getSExtValue())) {
867 Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
880 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
882 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
884 return SelectCode(N);
888 * Emit the instruction sequence for i64 left shifts. The basic algorithm
889 * is to fill the bottom two word slots with zeros so that zeros are shifted
890 * in as the entire quadword is shifted left.
892 * \note This code could also be used to implement v2i64 shl.
894 * @param Op The shl operand
895 * @param OpVT Op's machine value value type (doesn't need to be passed, but
896 * makes life easier.)
897 * @return The SDNode with the entire instruction sequence
900 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
901 SDValue Op0 = N->getOperand(0);
902 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
903 OpVT, (128 / OpVT.getSizeInBits()));
904 SDValue ShiftAmt = N->getOperand(1);
905 EVT ShiftAmtVT = ShiftAmt.getValueType();
906 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
908 DebugLoc dl = N->getDebugLoc();
910 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
911 Op0, getRC(MVT::v2i64) );
912 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
913 SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
914 ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
915 CurDAG->getTargetConstant(0, OpVT));
916 VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
917 SDValue(ZeroFill, 0),
919 SDValue(SelMask, 0));
921 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
922 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
923 unsigned bits = unsigned(CN->getZExtValue()) & 7;
927 CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
929 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
934 CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
935 SDValue((Shift != 0 ? Shift : VecOp0), 0),
936 CurDAG->getTargetConstant(bits, ShiftAmtVT));
940 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
942 CurDAG->getTargetConstant(3, ShiftAmtVT));
944 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
946 CurDAG->getTargetConstant(7, ShiftAmtVT));
948 CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
949 SDValue(VecOp0, 0), SDValue(Bytes, 0));
951 CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
952 SDValue(Shift, 0), SDValue(Bits, 0));
955 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
956 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
960 * Emit the instruction sequence for i64 logical right shifts.
962 * @param Op The shl operand
963 * @param OpVT Op's machine value value type (doesn't need to be passed, but
964 * makes life easier.)
965 * @return The SDNode with the entire instruction sequence
968 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
969 SDValue Op0 = N->getOperand(0);
970 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
971 OpVT, (128 / OpVT.getSizeInBits()));
972 SDValue ShiftAmt = N->getOperand(1);
973 EVT ShiftAmtVT = ShiftAmt.getValueType();
974 SDNode *VecOp0, *Shift = 0;
975 DebugLoc dl = N->getDebugLoc();
977 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
978 Op0, getRC(MVT::v2i64) );
980 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
981 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
982 unsigned bits = unsigned(CN->getZExtValue()) & 7;
986 CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
988 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
993 CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
994 SDValue((Shift != 0 ? Shift : VecOp0), 0),
995 CurDAG->getTargetConstant(bits, ShiftAmtVT));
999 CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1001 CurDAG->getTargetConstant(3, ShiftAmtVT));
1003 CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1005 CurDAG->getTargetConstant(7, ShiftAmtVT));
1007 // Ensure that the shift amounts are negated!
1008 Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1010 CurDAG->getTargetConstant(0, ShiftAmtVT));
1012 Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1014 CurDAG->getTargetConstant(0, ShiftAmtVT));
1017 CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1018 SDValue(VecOp0, 0), SDValue(Bytes, 0));
1020 CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1021 SDValue(Shift, 0), SDValue(Bits, 0));
1024 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1025 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1029 * Emit the instruction sequence for i64 arithmetic right shifts.
1031 * @param Op The shl operand
1032 * @param OpVT Op's machine value value type (doesn't need to be passed, but
1033 * makes life easier.)
1034 * @return The SDNode with the entire instruction sequence
1037 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1038 // Promote Op0 to vector
1039 EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1040 OpVT, (128 / OpVT.getSizeInBits()));
1041 SDValue ShiftAmt = N->getOperand(1);
1042 EVT ShiftAmtVT = ShiftAmt.getValueType();
1043 DebugLoc dl = N->getDebugLoc();
1046 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1047 VecVT, N->getOperand(0), getRC(MVT::v2i64));
1049 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1051 CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1052 SDValue(VecOp0, 0), SignRotAmt);
1053 SDNode *UpperHalfSign =
1054 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1055 MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32));
1057 SDNode *UpperHalfSignMask =
1058 CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1059 SDNode *UpperLowerMask =
1060 CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1061 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1062 SDNode *UpperLowerSelect =
1063 CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1064 SDValue(UpperHalfSignMask, 0),
1066 SDValue(UpperLowerMask, 0));
1070 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1071 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1072 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1077 CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1078 SDValue(UpperLowerSelect, 0),
1079 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1085 CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1086 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1087 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1091 CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1092 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1095 CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1096 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1098 CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1099 SDValue(Shift, 0), SDValue(NegShift, 0));
1102 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1103 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1107 Do the necessary magic necessary to load a i64 constant
1109 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1111 ConstantSDNode *CN = cast<ConstantSDNode>(N);
1112 return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1115 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1117 EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1119 SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1121 // Here's where it gets interesting, because we have to parse out the
1122 // subtree handed back in i64vec:
1124 if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1125 // The degenerate case where the upper and lower bits in the splat are
1127 SDValue Op0 = i64vec.getOperand(0);
1129 ReplaceUses(i64vec, Op0);
1130 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1131 SDValue(emitBuildVector(Op0.getNode()), 0),
1133 } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1134 SDValue lhs = i64vec.getOperand(0);
1135 SDValue rhs = i64vec.getOperand(1);
1136 SDValue shufmask = i64vec.getOperand(2);
1138 if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1139 ReplaceUses(lhs, lhs.getOperand(0));
1140 lhs = lhs.getOperand(0);
1143 SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1145 : emitBuildVector(lhs.getNode()));
1147 if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1148 ReplaceUses(rhs, rhs.getOperand(0));
1149 rhs = rhs.getOperand(0);
1152 SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1154 : emitBuildVector(rhs.getNode()));
1156 if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1157 ReplaceUses(shufmask, shufmask.getOperand(0));
1158 shufmask = shufmask.getOperand(0);
1161 SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1162 ? shufmask.getNode()
1163 : emitBuildVector(shufmask.getNode()));
1166 CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1167 SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1168 SDValue(shufMaskNode, 0));
1169 HandleSDNode Dummy(shufNode);
1170 SDNode *SN = SelectCode(Dummy.getValue().getNode());
1171 if (SN == 0) SN = Dummy.getValue().getNode();
1173 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1174 OpVT, SDValue(SN, 0), getRC(MVT::i64));
1175 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1176 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1177 SDValue(emitBuildVector(i64vec.getNode()), 0),
1180 report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1185 /// createSPUISelDag - This pass converts a legalized DAG into a
1186 /// SPU-specific DAG, ready for instruction scheduling.
1188 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1189 return new SPUDAGToDAGISel(TM);