1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "SPUTargetMachine.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Constants.h"
31 #include "llvm/GlobalValue.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSExtValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSExtValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant(CN->getSExtValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant(CN->getSExtValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getZExtValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT vt = CN->getValueType(0);
114 Imm = (short) CN->getZExtValue();
115 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getZExtValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getZExtValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDValue &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 bool ldresult_imm; /// LDRESULT instruction requires immediate?
170 unsigned lrinst; /// LR instruction
173 const valtype_map_s valtype_map[] = {
174 { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
175 { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
176 { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
177 { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
178 { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
179 { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
180 // vector types... (sigh!)
181 { MVT::v16i8, 0, false, SPU::LRv16i8 },
182 { MVT::v8i16, 0, false, SPU::LRv8i16 },
183 { MVT::v4i32, 0, false, SPU::LRv4i32 },
184 { MVT::v2i64, 0, false, SPU::LRv2i64 },
185 { MVT::v4f32, 0, false, SPU::LRv4f32 },
186 { MVT::v2f64, 0, false, SPU::LRv2f64 }
189 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
191 const valtype_map_s *getValueTypeMapEntry(MVT VT)
193 const valtype_map_s *retval = 0;
194 for (size_t i = 0; i < n_valtype_map; ++i) {
195 if (valtype_map[i].VT == VT) {
196 retval = valtype_map + i;
204 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
217 //===--------------------------------------------------------------------===//
218 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
219 /// instructions for SelectionDAG operations.
221 class SPUDAGToDAGISel :
222 public SelectionDAGISel
224 SPUTargetMachine &TM;
225 SPUTargetLowering &SPUtli;
226 unsigned GlobalBaseReg;
229 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
230 SelectionDAGISel(*tm.getTargetLowering()),
232 SPUtli(*tm.getTargetLowering())
235 virtual bool runOnFunction(Function &Fn) {
236 // Make sure we re-emit a set of the global base reg if necessary
238 SelectionDAGISel::runOnFunction(Fn);
242 /// getI32Imm - Return a target constant with the specified value, of type
244 inline SDValue getI32Imm(uint32_t Imm) {
245 return CurDAG->getTargetConstant(Imm, MVT::i32);
248 /// getI64Imm - Return a target constant with the specified value, of type
250 inline SDValue getI64Imm(uint64_t Imm) {
251 return CurDAG->getTargetConstant(Imm, MVT::i64);
254 /// getSmallIPtrImm - Return a target constant of pointer type.
255 inline SDValue getSmallIPtrImm(unsigned Imm) {
256 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
259 SDNode *emitBuildVector(SDValue build_vec) {
260 std::vector<Constant*> CV;
262 for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
263 ConstantSDNode *V = dyn_cast<ConstantSDNode>(build_vec.getOperand(i));
264 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
267 Constant *CP = ConstantVector::get(CV);
268 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
269 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
270 SDValue CGPoolOffset =
271 SPU::LowerConstantPool(CPIdx, *CurDAG,
272 SPUtli.getSPUTargetMachine());
273 return SelectCode(CurDAG->getLoad(build_vec.getValueType(),
274 CurDAG->getEntryNode(), CGPoolOffset,
275 PseudoSourceValue::getConstantPool(), 0,
279 /// Select - Convert the specified operand from a target-independent to a
280 /// target-specific node if it hasn't already been changed.
281 SDNode *Select(SDValue Op);
283 //! Emit the instruction sequence for i64 shl
284 SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
286 //! Emit the instruction sequence for i64 srl
287 SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
289 //! Emit the instruction sequence for i64 sra
290 SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
292 //! Returns true if the address N is an A-form (local store) address
293 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
296 //! D-form address predicate
297 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
300 /// Alternate D-form address using i7 offset predicate
301 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
304 /// D-form address selection workhorse
305 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
306 SDValue &Base, int minOffset, int maxOffset);
308 //! Address predicate if N can be expressed as an indexed [r+r] operation.
309 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
312 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
313 /// inline asm expressions.
314 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
316 std::vector<SDValue> &OutOps) {
318 switch (ConstraintCode) {
319 default: return true;
321 if (!SelectDFormAddr(Op, Op, Op0, Op1)
322 && !SelectAFormAddr(Op, Op, Op0, Op1))
323 SelectXFormAddr(Op, Op, Op0, Op1);
325 case 'o': // offsetable
326 if (!SelectDFormAddr(Op, Op, Op0, Op1)
327 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
329 Op1 = getSmallIPtrImm(0);
332 case 'v': // not offsetable
334 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
336 SelectAddrIdxOnly(Op, Op, Op0, Op1);
341 OutOps.push_back(Op0);
342 OutOps.push_back(Op1);
346 /// InstructionSelect - This callback is invoked by
347 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
348 virtual void InstructionSelect();
350 virtual const char *getPassName() const {
351 return "Cell SPU DAG->DAG Pattern Instruction Selection";
354 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
355 /// this target when scheduling the DAG.
356 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
357 const TargetInstrInfo *II = TM.getInstrInfo();
358 assert(II && "No InstrInfo?");
359 return new SPUHazardRecognizer(*II);
362 // Include the pieces autogenerated from the target description.
363 #include "SPUGenDAGISel.inc"
368 /// InstructionSelect - This callback is invoked by
369 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
371 SPUDAGToDAGISel::InstructionSelect()
375 // Select target instructions for the DAG.
377 CurDAG->RemoveDeadNodes();
381 \arg Op The ISD instructio operand
382 \arg N The address to be tested
383 \arg Base The base address
384 \arg Index The base address index
387 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
389 // These match the addr256k operand type:
390 MVT OffsVT = MVT::i16;
391 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
393 switch (N.getOpcode()) {
395 case ISD::ConstantPool:
396 case ISD::GlobalAddress:
397 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
401 case ISD::TargetConstant:
402 case ISD::TargetGlobalAddress:
403 case ISD::TargetJumpTable:
404 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
405 << "A-form address.\n";
409 case SPUISD::AFormAddr:
410 // Just load from memory if there's only a single use of the location,
411 // otherwise, this will get handled below with D-form offset addresses
413 SDValue Op0 = N.getOperand(0);
414 switch (Op0.getOpcode()) {
415 case ISD::TargetConstantPool:
416 case ISD::TargetJumpTable:
421 case ISD::TargetGlobalAddress: {
422 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
423 GlobalValue *GV = GSDN->getGlobal();
424 if (GV->getAlignment() == 16) {
439 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
441 const int minDForm2Offset = -(1 << 7);
442 const int maxDForm2Offset = (1 << 7) - 1;
443 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
448 \arg Op The ISD instruction (ignored)
449 \arg N The address to be tested
450 \arg Base Base address register/pointer
451 \arg Index Base address index
453 Examine the input address by a base register plus a signed 10-bit
454 displacement, [r+I10] (D-form address).
456 \return true if \a N is a D-form address with \a Base and \a Index set
457 to non-empty SDValue instances.
460 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
462 return DFormAddressPredicate(Op, N, Base, Index,
463 SPUFrameInfo::minFrameOffset(),
464 SPUFrameInfo::maxFrameOffset());
468 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
469 SDValue &Index, int minOffset,
471 unsigned Opc = N.getOpcode();
472 MVT PtrTy = SPUtli.getPointerTy();
474 if (Opc == ISD::FrameIndex) {
475 // Stack frame index must be less than 512 (divided by 16):
476 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
477 int FI = int(FIN->getIndex());
478 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
480 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
481 Base = CurDAG->getTargetConstant(0, PtrTy);
482 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
485 } else if (Opc == ISD::ADD) {
486 // Generated by getelementptr
487 const SDValue Op0 = N.getOperand(0);
488 const SDValue Op1 = N.getOperand(1);
490 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
491 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
492 Base = CurDAG->getTargetConstant(0, PtrTy);
495 } else if (Op1.getOpcode() == ISD::Constant
496 || Op1.getOpcode() == ISD::TargetConstant) {
497 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
498 int32_t offset = int32_t(CN->getSExtValue());
500 if (Op0.getOpcode() == ISD::FrameIndex) {
501 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
502 int FI = int(FIN->getIndex());
503 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
504 << " frame index = " << FI << "\n");
506 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
507 Base = CurDAG->getTargetConstant(offset, PtrTy);
508 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
511 } else if (offset > minOffset && offset < maxOffset) {
512 Base = CurDAG->getTargetConstant(offset, PtrTy);
516 } else if (Op0.getOpcode() == ISD::Constant
517 || Op0.getOpcode() == ISD::TargetConstant) {
518 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
519 int32_t offset = int32_t(CN->getSExtValue());
521 if (Op1.getOpcode() == ISD::FrameIndex) {
522 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
523 int FI = int(FIN->getIndex());
524 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
525 << " frame index = " << FI << "\n");
527 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
528 Base = CurDAG->getTargetConstant(offset, PtrTy);
529 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
532 } else if (offset > minOffset && offset < maxOffset) {
533 Base = CurDAG->getTargetConstant(offset, PtrTy);
538 } else if (Opc == SPUISD::IndirectAddr) {
539 // Indirect with constant offset -> D-Form address
540 const SDValue Op0 = N.getOperand(0);
541 const SDValue Op1 = N.getOperand(1);
543 if (Op0.getOpcode() == SPUISD::Hi
544 && Op1.getOpcode() == SPUISD::Lo) {
545 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
546 Base = CurDAG->getTargetConstant(0, PtrTy);
549 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
553 if (isa<ConstantSDNode>(Op1)) {
554 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
555 offset = int32_t(CN->getSExtValue());
557 } else if (isa<ConstantSDNode>(Op0)) {
558 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
559 offset = int32_t(CN->getSExtValue());
563 if (offset >= minOffset && offset <= maxOffset) {
564 Base = CurDAG->getTargetConstant(offset, PtrTy);
569 } else if (Opc == SPUISD::AFormAddr) {
570 Base = CurDAG->getTargetConstant(0, N.getValueType());
573 } else if (Opc == SPUISD::LDRESULT) {
574 Base = CurDAG->getTargetConstant(0, N.getValueType());
577 } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
578 unsigned OpOpc = Op.getOpcode();
580 if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
581 // Direct load/store without getelementptr
584 // Get the register from CopyFromReg
585 if (Opc == ISD::CopyFromReg)
586 Addr = N.getOperand(1);
588 Addr = N; // Register
590 Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
592 if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
593 if (Offs.getOpcode() == ISD::UNDEF)
594 Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
601 /* If otherwise unadorned, default to D-form address with 0 offset: */
602 if (Opc == ISD::CopyFromReg) {
603 Index = N.getOperand(1);
608 Base = CurDAG->getTargetConstant(0, Index.getValueType());
617 \arg Op The ISD instruction operand
618 \arg N The address operand
619 \arg Base The base pointer operand
620 \arg Index The offset/index operand
622 If the address \a N can be expressed as an A-form or D-form address, returns
623 false. Otherwise, creates two operands, Base and Index that will become the
624 (r)(r) X-form address.
627 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
629 if (!SelectAFormAddr(Op, N, Base, Index)
630 && !SelectDFormAddr(Op, N, Base, Index)) {
631 // If the address is neither A-form or D-form, punt and use an X-form
633 Base = N.getOperand(1);
634 Index = N.getOperand(0);
641 //! Convert the operand from a target-independent to a target-specific node
645 SPUDAGToDAGISel::Select(SDValue Op) {
646 SDNode *N = Op.getNode();
647 unsigned Opc = N->getOpcode();
650 MVT OpVT = Op.getValueType();
653 if (N->isMachineOpcode()) {
654 return NULL; // Already selected.
655 } else if (Opc == ISD::FrameIndex) {
656 int FI = cast<FrameIndexSDNode>(N)->getIndex();
657 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
658 SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
667 Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
668 Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, Op.getValueType(),
672 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
673 && OpVT == MVT::i64) {
674 SDValue Op0 = Op.getOperand(0);
675 MVT Op0VT = Op0.getValueType();
676 MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
677 MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
680 switch (Op0VT.getSimpleVT()) {
682 cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
687 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
688 CurDAG->getConstant(0x80808080, MVT::i32),
689 CurDAG->getConstant(0x00010203, MVT::i32),
690 CurDAG->getConstant(0x80808080, MVT::i32),
691 CurDAG->getConstant(0x08090a0b, MVT::i32));
695 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
696 CurDAG->getConstant(0x80808080, MVT::i32),
697 CurDAG->getConstant(0x80800203, MVT::i32),
698 CurDAG->getConstant(0x80808080, MVT::i32),
699 CurDAG->getConstant(0x80800a0b, MVT::i32));
703 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
704 CurDAG->getConstant(0x80808080, MVT::i32),
705 CurDAG->getConstant(0x80808003, MVT::i32),
706 CurDAG->getConstant(0x80808080, MVT::i32),
707 CurDAG->getConstant(0x8080800b, MVT::i32));
711 SDNode *shufMaskLoad = emitBuildVector(shufMask);
712 SDNode *PromoteScalar =
713 SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, Op0VecVT, Op0));
715 SDValue zextShuffle =
716 CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
717 SDValue(PromoteScalar, 0),
718 SDValue(PromoteScalar, 0),
719 SDValue(shufMaskLoad, 0));
721 // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
722 // re-use it in the VEC2PREFSLOT selection without needing to explicitly
723 // call SelectCode (it's already done for us.)
724 SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, OpVecVT, zextShuffle));
725 return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, OpVT,
727 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
729 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
731 return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
732 Op.getOperand(0), Op.getOperand(1),
733 SDValue(CGLoad, 0)));
734 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
736 emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
738 return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
739 Op.getOperand(0), Op.getOperand(1),
740 SDValue(CGLoad, 0)));
741 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
743 emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
745 return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
746 Op.getOperand(0), Op.getOperand(1),
747 SDValue(CGLoad, 0)));
748 } else if (Opc == ISD::SHL) {
749 if (OpVT == MVT::i64) {
750 return SelectSHLi64(Op, OpVT);
752 } else if (Opc == ISD::SRL) {
753 if (OpVT == MVT::i64) {
754 return SelectSRLi64(Op, OpVT);
756 } else if (Opc == ISD::SRA) {
757 if (OpVT == MVT::i64) {
758 return SelectSRAi64(Op, OpVT);
760 } else if (Opc == SPUISD::LDRESULT) {
761 // Custom select instructions for LDRESULT
762 MVT VT = N->getValueType(0);
763 SDValue Arg = N->getOperand(0);
764 SDValue Chain = N->getOperand(1);
766 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
768 if (vtm->ldresult_ins == 0) {
769 cerr << "LDRESULT for unsupported type: "
775 Opc = vtm->ldresult_ins;
776 if (vtm->ldresult_imm) {
777 SDValue Zero = CurDAG->getTargetConstant(0, VT);
779 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
781 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
785 } else if (Opc == SPUISD::IndirectAddr) {
786 // Look at the operands: SelectCode() will catch the cases that aren't
787 // specifically handled here.
789 // SPUInstrInfo catches the following patterns:
790 // (SPUindirect (SPUhi ...), (SPUlo ...))
791 // (SPUindirect $sp, imm)
792 MVT VT = Op.getValueType();
793 SDValue Op0 = N->getOperand(0);
794 SDValue Op1 = N->getOperand(1);
797 if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
798 || (Op0.getOpcode() == ISD::Register
799 && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
800 && RN->getReg() != SPU::R1))) {
802 if (Op1.getOpcode() == ISD::Constant) {
803 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
804 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
805 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
815 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
817 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
819 return SelectCode(Op);
823 * Emit the instruction sequence for i64 left shifts. The basic algorithm
824 * is to fill the bottom two word slots with zeros so that zeros are shifted
825 * in as the entire quadword is shifted left.
827 * \note This code could also be used to implement v2i64 shl.
829 * @param Op The shl operand
830 * @param OpVT Op's machine value value type (doesn't need to be passed, but
831 * makes life easier.)
832 * @return The SDNode with the entire instruction sequence
835 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
836 SDValue Op0 = Op.getOperand(0);
837 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
838 SDValue ShiftAmt = Op.getOperand(1);
839 MVT ShiftAmtVT = ShiftAmt.getValueType();
840 SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
843 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
844 SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
845 SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT, SelMaskVal);
846 ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, VecVT,
847 CurDAG->getTargetConstant(0, OpVT));
848 VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
849 SDValue(ZeroFill, 0),
851 SDValue(SelMask, 0));
853 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
854 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
855 unsigned bits = unsigned(CN->getZExtValue()) & 7;
859 CurDAG->getTargetNode(SPU::SHLQBYIv2i64, VecVT,
861 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
866 CurDAG->getTargetNode(SPU::SHLQBIIv2i64, VecVT,
867 SDValue((Shift != 0 ? Shift : VecOp0), 0),
868 CurDAG->getTargetConstant(bits, ShiftAmtVT));
872 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
874 CurDAG->getTargetConstant(3, ShiftAmtVT));
876 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
878 CurDAG->getTargetConstant(7, ShiftAmtVT));
880 CurDAG->getTargetNode(SPU::SHLQBYv2i64, VecVT,
881 SDValue(VecOp0, 0), SDValue(Bytes, 0));
883 CurDAG->getTargetNode(SPU::SHLQBIv2i64, VecVT,
884 SDValue(Shift, 0), SDValue(Bits, 0));
887 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
891 * Emit the instruction sequence for i64 logical right shifts.
893 * @param Op The shl operand
894 * @param OpVT Op's machine value value type (doesn't need to be passed, but
895 * makes life easier.)
896 * @return The SDNode with the entire instruction sequence
899 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
900 SDValue Op0 = Op.getOperand(0);
901 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
902 SDValue ShiftAmt = Op.getOperand(1);
903 MVT ShiftAmtVT = ShiftAmt.getValueType();
904 SDNode *VecOp0, *Shift = 0;
906 VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op0);
908 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
909 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
910 unsigned bits = unsigned(CN->getZExtValue()) & 7;
914 CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, VecVT,
916 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
921 CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, VecVT,
922 SDValue((Shift != 0 ? Shift : VecOp0), 0),
923 CurDAG->getTargetConstant(bits, ShiftAmtVT));
927 CurDAG->getTargetNode(SPU::ROTMIr32, ShiftAmtVT,
929 CurDAG->getTargetConstant(3, ShiftAmtVT));
931 CurDAG->getTargetNode(SPU::ANDIr32, ShiftAmtVT,
933 CurDAG->getTargetConstant(7, ShiftAmtVT));
935 // Ensure that the shift amounts are negated!
936 Bytes = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
938 CurDAG->getTargetConstant(0, ShiftAmtVT));
940 Bits = CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
942 CurDAG->getTargetConstant(0, ShiftAmtVT));
945 CurDAG->getTargetNode(SPU::ROTQMBYv2i64, VecVT,
946 SDValue(VecOp0, 0), SDValue(Bytes, 0));
948 CurDAG->getTargetNode(SPU::ROTQMBIv2i64, VecVT,
949 SDValue(Shift, 0), SDValue(Bits, 0));
952 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
956 * Emit the instruction sequence for i64 arithmetic right shifts.
958 * @param Op The shl operand
959 * @param OpVT Op's machine value value type (doesn't need to be passed, but
960 * makes life easier.)
961 * @return The SDNode with the entire instruction sequence
964 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
965 // Promote Op0 to vector
966 MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
967 SDValue ShiftAmt = Op.getOperand(1);
968 MVT ShiftAmtVT = ShiftAmt.getValueType();
971 CurDAG->getTargetNode(SPU::ORv2i64_i64, VecVT, Op.getOperand(0));
973 SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
975 CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, MVT::v2i64,
976 SDValue(VecOp0, 0), SignRotAmt);
977 SDNode *UpperHalfSign =
978 CurDAG->getTargetNode(SPU::ORi32_v4i32, MVT::i32, SDValue(SignRot, 0));
980 SDNode *UpperHalfSignMask =
981 CurDAG->getTargetNode(SPU::FSM64r32, VecVT, SDValue(UpperHalfSign, 0));
982 SDNode *UpperLowerMask =
983 CurDAG->getTargetNode(SPU::FSMBIv2i64, VecVT,
984 CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
985 SDNode *UpperLowerSelect =
986 CurDAG->getTargetNode(SPU::SELBv2i64, VecVT,
987 SDValue(UpperHalfSignMask, 0),
989 SDValue(UpperLowerMask, 0));
993 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
994 unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
995 unsigned bits = unsigned(CN->getZExtValue()) & 7;
1000 CurDAG->getTargetNode(SPU::ROTQBYIv2i64, VecVT,
1001 SDValue(UpperLowerSelect, 0),
1002 CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1008 CurDAG->getTargetNode(SPU::ROTQBIIv2i64, VecVT,
1009 SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1010 CurDAG->getTargetConstant(bits, ShiftAmtVT));
1014 CurDAG->getTargetNode(SPU::SFIr32, ShiftAmtVT,
1015 ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1018 CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, VecVT,
1019 SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1021 CurDAG->getTargetNode(SPU::ROTQBIv2i64, VecVT,
1022 SDValue(Shift, 0), SDValue(NegShift, 0));
1025 return CurDAG->getTargetNode(SPU::ORi64_v2i64, OpVT, SDValue(Shift, 0));
1028 /// createSPUISelDag - This pass converts a legalized DAG into a
1029 /// SPU-specific DAG, ready for instruction scheduling.
1031 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1032 return new SPUDAGToDAGISel(TM);