1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getValue());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant((int) CN->getValue());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant((int) CN->getValue());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant((short) CN->getValue());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT::ValueType vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt >= MVT::i1 && vt <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT::ValueType vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDOperand &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT::ValueType to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 bool ldresult_imm; /// LDRESULT instruction requires immediate?
170 int prefslot_byte; /// Byte offset of the "preferred" slot
173 const valtype_map_s valtype_map[] = {
174 { MVT::i1, 0, false, 3 },
175 { MVT::i8, SPU::ORBIr8, true, 3 },
176 { MVT::i16, SPU::ORHIr16, true, 2 },
177 { MVT::i32, SPU::ORIr32, true, 0 },
178 { MVT::i64, SPU::ORr64, false, 0 },
179 { MVT::f32, SPU::ORf32, false, 0 },
180 { MVT::f64, SPU::ORf64, false, 0 },
181 // vector types... (sigh!)
182 { MVT::v16i8, 0, false, 0 },
183 { MVT::v8i16, 0, false, 0 },
184 { MVT::v4i32, 0, false, 0 },
185 { MVT::v2i64, 0, false, 0 },
186 { MVT::v4f32, 0, false, 0 },
187 { MVT::v2f64, 0, false, 0 }
190 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
192 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
194 const valtype_map_s *retval = 0;
195 for (size_t i = 0; i < n_valtype_map; ++i) {
196 if (valtype_map[i].VT == VT) {
197 retval = valtype_map + i;
205 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
206 << MVT::getValueTypeString(VT)
216 //===--------------------------------------------------------------------===//
217 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
218 /// instructions for SelectionDAG operations.
220 class SPUDAGToDAGISel :
221 public SelectionDAGISel
223 SPUTargetMachine &TM;
224 SPUTargetLowering &SPUtli;
225 unsigned GlobalBaseReg;
228 SPUDAGToDAGISel(SPUTargetMachine &tm) :
229 SelectionDAGISel(*tm.getTargetLowering()),
231 SPUtli(*tm.getTargetLowering())
234 virtual bool runOnFunction(Function &Fn) {
235 // Make sure we re-emit a set of the global base reg if necessary
237 SelectionDAGISel::runOnFunction(Fn);
241 /// getI32Imm - Return a target constant with the specified value, of type
243 inline SDOperand getI32Imm(uint32_t Imm) {
244 return CurDAG->getTargetConstant(Imm, MVT::i32);
247 /// getI64Imm - Return a target constant with the specified value, of type
249 inline SDOperand getI64Imm(uint64_t Imm) {
250 return CurDAG->getTargetConstant(Imm, MVT::i64);
253 /// getSmallIPtrImm - Return a target constant of pointer type.
254 inline SDOperand getSmallIPtrImm(unsigned Imm) {
255 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
258 /// Select - Convert the specified operand from a target-independent to a
259 /// target-specific node if it hasn't already been changed.
260 SDNode *Select(SDOperand Op);
262 //! Returns true if the address N is an A-form (local store) address
263 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
266 //! D-form address predicate
267 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
270 /// Alternate D-form address using i7 offset predicate
271 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
274 /// D-form address selection workhorse
275 bool DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Disp,
276 SDOperand &Base, int minOffset, int maxOffset);
278 //! Address predicate if N can be expressed as an indexed [r+r] operation.
279 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
282 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
283 /// inline asm expressions.
284 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
286 std::vector<SDOperand> &OutOps,
289 switch (ConstraintCode) {
290 default: return true;
292 if (!SelectDFormAddr(Op, Op, Op0, Op1)
293 && !SelectAFormAddr(Op, Op, Op0, Op1))
294 SelectXFormAddr(Op, Op, Op0, Op1);
296 case 'o': // offsetable
297 if (!SelectDFormAddr(Op, Op, Op0, Op1)
298 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
300 AddToISelQueue(Op0); // r+0.
301 Op1 = getSmallIPtrImm(0);
304 case 'v': // not offsetable
306 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
308 SelectAddrIdxOnly(Op, Op, Op0, Op1);
313 OutOps.push_back(Op0);
314 OutOps.push_back(Op1);
318 /// InstructionSelectBasicBlock - This callback is invoked by
319 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
320 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
322 virtual const char *getPassName() const {
323 return "Cell SPU DAG->DAG Pattern Instruction Selection";
326 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
327 /// this target when scheduling the DAG.
328 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
329 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
330 assert(II && "No InstrInfo?");
331 return new SPUHazardRecognizer(*II);
334 // Include the pieces autogenerated from the target description.
335 #include "SPUGenDAGISel.inc"
338 /// InstructionSelectBasicBlock - This callback is invoked by
339 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
341 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
345 // Select target instructions for the DAG.
346 DAG.setRoot(SelectRoot(DAG.getRoot()));
347 DAG.RemoveDeadNodes();
349 // Emit machine code to BB.
350 ScheduleAndEmitDAG(DAG);
354 \arg Op The ISD instructio operand
355 \arg N The address to be tested
356 \arg Base The base address
357 \arg Index The base address index
360 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
362 // These match the addr256k operand type:
363 MVT::ValueType OffsVT = MVT::i16;
364 SDOperand Zero = CurDAG->getTargetConstant(0, OffsVT);
366 switch (N.getOpcode()) {
368 case ISD::ConstantPool:
369 case ISD::GlobalAddress:
370 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
374 case ISD::TargetConstant:
375 case ISD::TargetGlobalAddress:
376 case ISD::TargetJumpTable:
377 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
378 << "A-form address.\n";
382 case SPUISD::AFormAddr:
383 // Just load from memory if there's only a single use of the location,
384 // otherwise, this will get handled below with D-form offset addresses
386 SDOperand Op0 = N.getOperand(0);
387 switch (Op0.getOpcode()) {
388 case ISD::TargetConstantPool:
389 case ISD::TargetJumpTable:
394 case ISD::TargetGlobalAddress: {
395 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
396 GlobalValue *GV = GSDN->getGlobal();
397 if (GV->getAlignment() == 16) {
412 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
414 return DFormAddressPredicate(Op, N, Disp, Base, -(1 << 7), (1 << 7) - 1);
418 \arg Op The ISD instruction (ignored)
419 \arg N The address to be tested
420 \arg Base Base address register/pointer
421 \arg Index Base address index
423 Examine the input address by a base register plus a signed 10-bit
424 displacement, [r+I10] (D-form address).
426 \return true if \a N is a D-form address with \a Base and \a Index set
427 to non-empty SDOperand instances.
430 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
432 return DFormAddressPredicate(Op, N, Base, Index,
433 SPUFrameInfo::minFrameOffset(),
434 SPUFrameInfo::maxFrameOffset());
438 SPUDAGToDAGISel::DFormAddressPredicate(SDOperand Op, SDOperand N, SDOperand &Base,
439 SDOperand &Index, int minOffset,
441 unsigned Opc = N.getOpcode();
442 unsigned PtrTy = SPUtli.getPointerTy();
444 if (Opc == ISD::FrameIndex) {
445 // Stack frame index must be less than 512 (divided by 16):
446 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
447 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
448 << FI->getIndex() << "\n");
449 if (FI->getIndex() < maxOffset) {
450 Base = CurDAG->getTargetConstant(0, PtrTy);
451 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
454 } else if (Opc == ISD::ADD) {
455 // Generated by getelementptr
456 const SDOperand Op0 = N.getOperand(0);
457 const SDOperand Op1 = N.getOperand(1);
459 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
460 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
461 Base = CurDAG->getTargetConstant(0, PtrTy);
464 } else if (Op1.getOpcode() == ISD::Constant
465 || Op1.getOpcode() == ISD::TargetConstant) {
466 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
467 int32_t offset = int32_t(CN->getSignExtended());
469 if (Op0.getOpcode() == ISD::FrameIndex) {
470 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
471 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
472 << " frame index = " << FI->getIndex() << "\n");
474 if (FI->getIndex() < maxOffset) {
475 Base = CurDAG->getTargetConstant(offset, PtrTy);
476 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
479 } else if (offset > minOffset && offset < maxOffset) {
480 Base = CurDAG->getTargetConstant(offset, PtrTy);
484 } else if (Op0.getOpcode() == ISD::Constant
485 || Op0.getOpcode() == ISD::TargetConstant) {
486 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
487 int32_t offset = int32_t(CN->getSignExtended());
489 if (Op1.getOpcode() == ISD::FrameIndex) {
490 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op1);
491 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
492 << " frame index = " << FI->getIndex() << "\n");
494 if (FI->getIndex() < maxOffset) {
495 Base = CurDAG->getTargetConstant(offset, PtrTy);
496 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
499 } else if (offset > minOffset && offset < maxOffset) {
500 Base = CurDAG->getTargetConstant(offset, PtrTy);
505 } else if (Opc == SPUISD::IndirectAddr) {
506 // Indirect with constant offset -> D-Form address
507 const SDOperand Op0 = N.getOperand(0);
508 const SDOperand Op1 = N.getOperand(1);
510 if (Op0.getOpcode() == SPUISD::Hi
511 && Op1.getOpcode() == SPUISD::Lo) {
512 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
513 Base = CurDAG->getTargetConstant(0, PtrTy);
516 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
520 if (isa<ConstantSDNode>(Op1)) {
521 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
522 offset = int32_t(CN->getSignExtended());
524 } else if (isa<ConstantSDNode>(Op0)) {
525 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
526 offset = int32_t(CN->getSignExtended());
530 if (offset >= minOffset && offset <= maxOffset) {
531 Base = CurDAG->getTargetConstant(offset, PtrTy);
536 } else if (Opc == SPUISD::AFormAddr) {
537 Base = CurDAG->getTargetConstant(0, N.getValueType());
540 } else if (Opc == SPUISD::LDRESULT) {
541 Base = CurDAG->getTargetConstant(0, N.getValueType());
549 \arg Op The ISD instruction operand
550 \arg N The address operand
551 \arg Base The base pointer operand
552 \arg Index The offset/index operand
554 If the address \a N can be expressed as a [r + s10imm] address, returns false.
555 Otherwise, creates two operands, Base and Index that will become the [r+r]
559 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
561 if (SelectAFormAddr(Op, N, Base, Index)
562 || SelectDFormAddr(Op, N, Base, Index))
565 // All else fails, punt and use an X-form address:
566 Base = N.getOperand(0);
567 Index = N.getOperand(1);
571 //! Convert the operand from a target-independent to a target-specific node
575 SPUDAGToDAGISel::Select(SDOperand Op) {
577 unsigned Opc = N->getOpcode();
580 MVT::ValueType OpVT = Op.getValueType();
583 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
584 return NULL; // Already selected.
585 } else if (Opc == ISD::FrameIndex) {
586 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
587 int FI = cast<FrameIndexSDNode>(N)->getIndex();
588 MVT::ValueType PtrVT = SPUtli.getPointerTy();
589 SDOperand Zero = CurDAG->getTargetConstant(0, PtrVT);
590 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, PtrVT);
592 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 <FI>, 0\n");
597 } else if (Opc == ISD::ZERO_EXTEND) {
598 // (zero_extend:i16 (and:i8 <arg>, <const>))
599 const SDOperand &Op1 = N->getOperand(0);
601 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
602 if (Op1.getOpcode() == ISD::AND) {
603 // Fold this into a single ANDHI. This is often seen in expansions of i1
604 // to i8, then i8 to i16 in logical/branching operations.
605 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
606 "<arg>, <const>))\n");
607 NewOpc = SPU::ANDHIi8i16;
608 Ops[0] = Op1.getOperand(0);
609 Ops[1] = Op1.getOperand(1);
613 } else if (Opc == SPUISD::LDRESULT) {
614 // Custom select instructions for LDRESULT
615 unsigned VT = N->getValueType(0);
616 SDOperand Arg = N->getOperand(0);
617 SDOperand Chain = N->getOperand(1);
619 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
621 if (vtm->ldresult_ins == 0) {
622 cerr << "LDRESULT for unsupported type: "
623 << MVT::getValueTypeString(VT)
629 Opc = vtm->ldresult_ins;
630 if (vtm->ldresult_imm) {
631 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
633 AddToISelQueue(Zero);
634 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
636 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
639 Chain = SDOperand(Result, 1);
640 AddToISelQueue(Chain);
643 } else if (Opc == SPUISD::IndirectAddr) {
644 SDOperand Op0 = Op.getOperand(0);
645 if (Op0.getOpcode() == SPUISD::LDRESULT) {
646 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
647 // (IndirectAddr (LDRESULT, imm))
648 SDOperand Op1 = Op.getOperand(1);
649 MVT::ValueType VT = Op.getValueType();
651 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
652 DEBUG(Op.getOperand(0).Val->dump(CurDAG));
653 DEBUG(cerr << "\nOp1 = ");
654 DEBUG(Op.getOperand(1).Val->dump(CurDAG));
657 if (Op1.getOpcode() == ISD::Constant) {
658 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
659 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
660 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
672 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
674 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
676 return SelectCode(Op);
679 /// createPPCISelDag - This pass converts a legalized DAG into a
680 /// SPU-specific DAG, ready for instruction scheduling.
682 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
683 return new SPUDAGToDAGISel(TM);