1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
13 //===----------------------------------------------------------------------===//
16 #include "SPUTargetMachine.h"
17 #include "SPUISelLowering.h"
18 #include "SPUHazardRecognizers.h"
19 #include "SPUFrameInfo.h"
20 #include "SPURegisterNames.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/Compiler.h"
40 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42 isI64IntS10Immediate(ConstantSDNode *CN)
44 return isS10Constant(CN->getSignExtended());
47 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
49 isI32IntS10Immediate(ConstantSDNode *CN)
51 return isS10Constant(CN->getSignExtended());
55 //! SDNode predicate for sign-extended, 10-bit immediate values
57 isI32IntS10Immediate(SDNode *N)
59 return (N->getOpcode() == ISD::Constant
60 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
64 //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
66 isI32IntU10Immediate(ConstantSDNode *CN)
68 return isU10Constant(CN->getSignExtended());
71 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
73 isI16IntS10Immediate(ConstantSDNode *CN)
75 return isS10Constant(CN->getSignExtended());
78 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
80 isI16IntS10Immediate(SDNode *N)
82 return (N->getOpcode() == ISD::Constant
83 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
86 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
88 isI16IntU10Immediate(ConstantSDNode *CN)
90 return isU10Constant((short) CN->getValue());
93 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
95 isI16IntU10Immediate(SDNode *N)
97 return (N->getOpcode() == ISD::Constant
98 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
101 //! ConstantSDNode predicate for signed 16-bit values
103 \arg CN The constant SelectionDAG node holding the value
104 \arg Imm The returned 16-bit value, if returning true
106 This predicate tests the value in \a CN to see whether it can be
107 represented as a 16-bit, sign-extended quantity. Returns true if
111 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
113 MVT vt = CN->getValueType(0);
114 Imm = (short) CN->getValue();
115 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
117 } else if (vt == MVT::i32) {
118 int32_t i_val = (int32_t) CN->getValue();
119 short s_val = (short) i_val;
120 return i_val == s_val;
122 int64_t i_val = (int64_t) CN->getValue();
123 short s_val = (short) i_val;
124 return i_val == s_val;
130 //! SDNode predicate for signed 16-bit values.
132 isIntS16Immediate(SDNode *N, short &Imm)
134 return (N->getOpcode() == ISD::Constant
135 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
138 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
140 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
142 MVT vt = FPN->getValueType(0);
143 if (vt == MVT::f32) {
144 int val = FloatToBits(FPN->getValueAPF().convertToFloat());
145 int sval = (int) ((val << 16) >> 16);
154 isHighLow(const SDValue &Op)
156 return (Op.getOpcode() == SPUISD::IndirectAddr
157 && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
158 && Op.getOperand(1).getOpcode() == SPUISD::Lo)
159 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
160 && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
163 //===------------------------------------------------------------------===//
164 //! MVT to "useful stuff" mapping structure:
166 struct valtype_map_s {
168 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
169 bool ldresult_imm; /// LDRESULT instruction requires immediate?
170 int prefslot_byte; /// Byte offset of the "preferred" slot
173 const valtype_map_s valtype_map[] = {
174 { MVT::i1, 0, false, 3 },
175 { MVT::i8, SPU::ORBIr8, true, 3 },
176 { MVT::i16, SPU::ORHIr16, true, 2 },
177 { MVT::i32, SPU::ORIr32, true, 0 },
178 { MVT::i64, SPU::ORr64, false, 0 },
179 { MVT::f32, SPU::ORf32, false, 0 },
180 { MVT::f64, SPU::ORf64, false, 0 },
181 // vector types... (sigh!)
182 { MVT::v16i8, 0, false, 0 },
183 { MVT::v8i16, 0, false, 0 },
184 { MVT::v4i32, 0, false, 0 },
185 { MVT::v2i64, 0, false, 0 },
186 { MVT::v4f32, 0, false, 0 },
187 { MVT::v2f64, 0, false, 0 }
190 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
192 const valtype_map_s *getValueTypeMapEntry(MVT VT)
194 const valtype_map_s *retval = 0;
195 for (size_t i = 0; i < n_valtype_map; ++i) {
196 if (valtype_map[i].VT == VT) {
197 retval = valtype_map + i;
205 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
218 //===--------------------------------------------------------------------===//
219 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
220 /// instructions for SelectionDAG operations.
222 class SPUDAGToDAGISel :
223 public SelectionDAGISel
225 SPUTargetMachine &TM;
226 SPUTargetLowering &SPUtli;
227 unsigned GlobalBaseReg;
230 explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
231 SelectionDAGISel(*tm.getTargetLowering()),
233 SPUtli(*tm.getTargetLowering())
236 virtual bool runOnFunction(Function &Fn) {
237 // Make sure we re-emit a set of the global base reg if necessary
239 SelectionDAGISel::runOnFunction(Fn);
243 /// getI32Imm - Return a target constant with the specified value, of type
245 inline SDValue getI32Imm(uint32_t Imm) {
246 return CurDAG->getTargetConstant(Imm, MVT::i32);
249 /// getI64Imm - Return a target constant with the specified value, of type
251 inline SDValue getI64Imm(uint64_t Imm) {
252 return CurDAG->getTargetConstant(Imm, MVT::i64);
255 /// getSmallIPtrImm - Return a target constant of pointer type.
256 inline SDValue getSmallIPtrImm(unsigned Imm) {
257 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
260 /// Select - Convert the specified operand from a target-independent to a
261 /// target-specific node if it hasn't already been changed.
262 SDNode *Select(SDValue Op);
264 //! Returns true if the address N is an A-form (local store) address
265 bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
268 //! D-form address predicate
269 bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
272 /// Alternate D-form address using i7 offset predicate
273 bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
276 /// D-form address selection workhorse
277 bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
278 SDValue &Base, int minOffset, int maxOffset);
280 //! Address predicate if N can be expressed as an indexed [r+r] operation.
281 bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
284 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
285 /// inline asm expressions.
286 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
288 std::vector<SDValue> &OutOps) {
290 switch (ConstraintCode) {
291 default: return true;
293 if (!SelectDFormAddr(Op, Op, Op0, Op1)
294 && !SelectAFormAddr(Op, Op, Op0, Op1))
295 SelectXFormAddr(Op, Op, Op0, Op1);
297 case 'o': // offsetable
298 if (!SelectDFormAddr(Op, Op, Op0, Op1)
299 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
301 AddToISelQueue(Op0); // r+0.
302 Op1 = getSmallIPtrImm(0);
305 case 'v': // not offsetable
307 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
309 SelectAddrIdxOnly(Op, Op, Op0, Op1);
314 OutOps.push_back(Op0);
315 OutOps.push_back(Op1);
319 /// InstructionSelect - This callback is invoked by
320 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
321 virtual void InstructionSelect();
323 virtual const char *getPassName() const {
324 return "Cell SPU DAG->DAG Pattern Instruction Selection";
327 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
328 /// this target when scheduling the DAG.
329 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
330 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
331 assert(II && "No InstrInfo?");
332 return new SPUHazardRecognizer(*II);
335 // Include the pieces autogenerated from the target description.
336 #include "SPUGenDAGISel.inc"
341 /// InstructionSelect - This callback is invoked by
342 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
344 SPUDAGToDAGISel::InstructionSelect()
348 // Select target instructions for the DAG.
350 CurDAG->RemoveDeadNodes();
354 \arg Op The ISD instructio operand
355 \arg N The address to be tested
356 \arg Base The base address
357 \arg Index The base address index
360 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
362 // These match the addr256k operand type:
363 MVT OffsVT = MVT::i16;
364 SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
366 switch (N.getOpcode()) {
368 case ISD::ConstantPool:
369 case ISD::GlobalAddress:
370 cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
374 case ISD::TargetConstant:
375 case ISD::TargetGlobalAddress:
376 case ISD::TargetJumpTable:
377 cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
378 << "A-form address.\n";
382 case SPUISD::AFormAddr:
383 // Just load from memory if there's only a single use of the location,
384 // otherwise, this will get handled below with D-form offset addresses
386 SDValue Op0 = N.getOperand(0);
387 switch (Op0.getOpcode()) {
388 case ISD::TargetConstantPool:
389 case ISD::TargetJumpTable:
394 case ISD::TargetGlobalAddress: {
395 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
396 GlobalValue *GV = GSDN->getGlobal();
397 if (GV->getAlignment() == 16) {
412 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
414 const int minDForm2Offset = -(1 << 7);
415 const int maxDForm2Offset = (1 << 7) - 1;
416 return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
421 \arg Op The ISD instruction (ignored)
422 \arg N The address to be tested
423 \arg Base Base address register/pointer
424 \arg Index Base address index
426 Examine the input address by a base register plus a signed 10-bit
427 displacement, [r+I10] (D-form address).
429 \return true if \a N is a D-form address with \a Base and \a Index set
430 to non-empty SDValue instances.
433 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
435 return DFormAddressPredicate(Op, N, Base, Index,
436 SPUFrameInfo::minFrameOffset(),
437 SPUFrameInfo::maxFrameOffset());
441 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
442 SDValue &Index, int minOffset,
444 unsigned Opc = N.getOpcode();
445 MVT PtrTy = SPUtli.getPointerTy();
447 if (Opc == ISD::FrameIndex) {
448 // Stack frame index must be less than 512 (divided by 16):
449 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
450 int FI = int(FIN->getIndex());
451 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
453 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
454 Base = CurDAG->getTargetConstant(0, PtrTy);
455 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
458 } else if (Opc == ISD::ADD) {
459 // Generated by getelementptr
460 const SDValue Op0 = N.getOperand(0);
461 const SDValue Op1 = N.getOperand(1);
463 if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
464 || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
465 Base = CurDAG->getTargetConstant(0, PtrTy);
468 } else if (Op1.getOpcode() == ISD::Constant
469 || Op1.getOpcode() == ISD::TargetConstant) {
470 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
471 int32_t offset = int32_t(CN->getSignExtended());
473 if (Op0.getOpcode() == ISD::FrameIndex) {
474 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
475 int FI = int(FIN->getIndex());
476 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
477 << " frame index = " << FI << "\n");
479 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
480 Base = CurDAG->getTargetConstant(offset, PtrTy);
481 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
484 } else if (offset > minOffset && offset < maxOffset) {
485 Base = CurDAG->getTargetConstant(offset, PtrTy);
489 } else if (Op0.getOpcode() == ISD::Constant
490 || Op0.getOpcode() == ISD::TargetConstant) {
491 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
492 int32_t offset = int32_t(CN->getSignExtended());
494 if (Op1.getOpcode() == ISD::FrameIndex) {
495 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
496 int FI = int(FIN->getIndex());
497 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
498 << " frame index = " << FI << "\n");
500 if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
501 Base = CurDAG->getTargetConstant(offset, PtrTy);
502 Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
505 } else if (offset > minOffset && offset < maxOffset) {
506 Base = CurDAG->getTargetConstant(offset, PtrTy);
511 } else if (Opc == SPUISD::IndirectAddr) {
512 // Indirect with constant offset -> D-Form address
513 const SDValue Op0 = N.getOperand(0);
514 const SDValue Op1 = N.getOperand(1);
516 if (Op0.getOpcode() == SPUISD::Hi
517 && Op1.getOpcode() == SPUISD::Lo) {
518 // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
519 Base = CurDAG->getTargetConstant(0, PtrTy);
522 } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
526 if (isa<ConstantSDNode>(Op1)) {
527 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
528 offset = int32_t(CN->getSignExtended());
530 } else if (isa<ConstantSDNode>(Op0)) {
531 ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
532 offset = int32_t(CN->getSignExtended());
536 if (offset >= minOffset && offset <= maxOffset) {
537 Base = CurDAG->getTargetConstant(offset, PtrTy);
542 } else if (Opc == SPUISD::AFormAddr) {
543 Base = CurDAG->getTargetConstant(0, N.getValueType());
546 } else if (Opc == SPUISD::LDRESULT) {
547 Base = CurDAG->getTargetConstant(0, N.getValueType());
555 \arg Op The ISD instruction operand
556 \arg N The address operand
557 \arg Base The base pointer operand
558 \arg Index The offset/index operand
560 If the address \a N can be expressed as a [r + s10imm] address, returns false.
561 Otherwise, creates two operands, Base and Index that will become the [r+r]
565 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
567 if (SelectAFormAddr(Op, N, Base, Index)
568 || SelectDFormAddr(Op, N, Base, Index))
571 // All else fails, punt and use an X-form address:
572 Base = N.getOperand(0);
573 Index = N.getOperand(1);
577 //! Convert the operand from a target-independent to a target-specific node
581 SPUDAGToDAGISel::Select(SDValue Op) {
582 SDNode *N = Op.getNode();
583 unsigned Opc = N->getOpcode();
586 MVT OpVT = Op.getValueType();
589 if (N->isMachineOpcode()) {
590 return NULL; // Already selected.
591 } else if (Opc == ISD::FrameIndex) {
592 // Selects to (add $sp, FI * stackSlotSize)
594 SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
595 MVT PtrVT = SPUtli.getPointerTy();
597 // Adjust stack slot to actual offset in frame:
598 if (isS10Constant(FI)) {
599 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
603 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
604 Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
607 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
611 Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
612 Ops[1] = CurDAG->getConstant(FI, PtrVT);
615 AddToISelQueue(Ops[1]);
617 } else if (Opc == ISD::ZERO_EXTEND) {
618 // (zero_extend:i16 (and:i8 <arg>, <const>))
619 const SDValue &Op1 = N->getOperand(0);
621 if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
622 if (Op1.getOpcode() == ISD::AND) {
623 // Fold this into a single ANDHI. This is often seen in expansions of i1
624 // to i8, then i8 to i16 in logical/branching operations.
625 DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
626 "<arg>, <const>))\n");
627 NewOpc = SPU::ANDHIi8i16;
628 Ops[0] = Op1.getOperand(0);
629 Ops[1] = Op1.getOperand(1);
633 } else if (Opc == SPUISD::LDRESULT) {
634 // Custom select instructions for LDRESULT
635 MVT VT = N->getValueType(0);
636 SDValue Arg = N->getOperand(0);
637 SDValue Chain = N->getOperand(1);
639 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
641 if (vtm->ldresult_ins == 0) {
642 cerr << "LDRESULT for unsupported type: "
649 Opc = vtm->ldresult_ins;
650 if (vtm->ldresult_imm) {
651 SDValue Zero = CurDAG->getTargetConstant(0, VT);
653 AddToISelQueue(Zero);
654 Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
656 Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
659 Chain = SDValue(Result, 1);
660 AddToISelQueue(Chain);
663 } else if (Opc == SPUISD::IndirectAddr) {
664 SDValue Op0 = Op.getOperand(0);
665 if (Op0.getOpcode() == SPUISD::LDRESULT) {
666 /* || Op0.getOpcode() == SPUISD::AFormAddr) */
667 // (IndirectAddr (LDRESULT, imm))
668 SDValue Op1 = Op.getOperand(1);
669 MVT VT = Op.getValueType();
671 DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
672 DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
673 DEBUG(cerr << "\nOp1 = ");
674 DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
677 if (Op1.getOpcode() == ISD::Constant) {
678 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
679 Op1 = CurDAG->getTargetConstant(CN->getValue(), VT);
680 NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
692 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
694 return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
696 return SelectCode(Op);
699 /// createPPCISelDag - This pass converts a legalized DAG into a
700 /// SPU-specific DAG, ready for instruction scheduling.
702 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
703 return new SPUDAGToDAGISel(TM);