1 //===-- SPUISelDAGToDAG.cpp - CellSPU -pattern matching inst selector -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file defines a pattern matching instruction selector for the Cell SPU,
12 // converting from a legalized dag to a SPU-target dag.
14 //===----------------------------------------------------------------------===//
17 #include "SPUTargetMachine.h"
18 #include "SPUISelLowering.h"
19 #include "SPUHazardRecognizers.h"
20 #include "SPUFrameInfo.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Constants.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/Compiler.h"
42 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
44 isI64IntS10Immediate(ConstantSDNode *CN)
46 return isS10Constant(CN->getValue());
49 //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
51 isI32IntS10Immediate(ConstantSDNode *CN)
53 return isS10Constant((int) CN->getValue());
57 //! SDNode predicate for sign-extended, 10-bit immediate values
59 isI32IntS10Immediate(SDNode *N)
61 return (N->getOpcode() == ISD::Constant
62 && isI32IntS10Immediate(cast<ConstantSDNode>(N)));
66 //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
68 isI16IntS10Immediate(ConstantSDNode *CN)
70 return isS10Constant((short) CN->getValue());
73 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
75 isI16IntS10Immediate(SDNode *N)
77 return (N->getOpcode() == ISD::Constant
78 && isI16IntS10Immediate(cast<ConstantSDNode>(N)));
81 //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
83 isI16IntU10Immediate(ConstantSDNode *CN)
85 return isU10Constant((short) CN->getValue());
88 //! SDNode predicate for i16 sign-extended, 10-bit immediate values
90 isI16IntU10Immediate(SDNode *N)
92 return (N->getOpcode() == ISD::Constant
93 && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
96 //! ConstantSDNode predicate for signed 16-bit values
98 \arg CN The constant SelectionDAG node holding the value
99 \arg Imm The returned 16-bit value, if returning true
101 This predicate tests the value in \a CN to see whether it can be
102 represented as a 16-bit, sign-extended quantity. Returns true if
106 isIntS16Immediate(ConstantSDNode *CN, short &Imm)
108 MVT::ValueType vt = CN->getValueType(0);
109 Imm = (short) CN->getValue();
110 if (vt >= MVT::i1 && vt <= MVT::i16) {
112 } else if (vt == MVT::i32) {
113 int32_t i_val = (int32_t) CN->getValue();
114 short s_val = (short) i_val;
115 return i_val == s_val;
117 int64_t i_val = (int64_t) CN->getValue();
118 short s_val = (short) i_val;
119 return i_val == s_val;
125 //! SDNode predicate for signed 16-bit values.
127 isIntS16Immediate(SDNode *N, short &Imm)
129 return (N->getOpcode() == ISD::Constant
130 && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
133 //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
135 isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
137 MVT::ValueType vt = FPN->getValueType(0);
138 if (vt == MVT::f32) {
139 const APFloat &apf = FPN->getValueAPF();
140 float fval = apf.convertToFloat();
141 int val = *((int *) &fval);
142 int sval = (int) ((val << 16) >> 16);
150 //===------------------------------------------------------------------===//
151 //! MVT::ValueType to useful stuff structure:
153 struct valtype_map_s {
155 unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
156 int prefslot_byte; /// Byte offset of the "preferred" slot
157 unsigned brcc_eq_ins; /// br_cc equal instruction
158 unsigned brcc_neq_ins; /// br_cc not equal instruction
161 const valtype_map_s valtype_map[] = {
162 { MVT::i1, 0, 3, 0, 0 },
163 { MVT::i8, 0, 3, 0, 0 },
164 { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
165 { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
166 { MVT::i64, SPU::ORIr64, 0, 0, 0 },
167 { MVT::f32, SPU::ORIf32, 0, 0, 0 },
168 { MVT::f64, SPU::ORIf64, 0, 0, 0 }
171 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
173 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
175 const valtype_map_s *retval = 0;
176 for (size_t i = 0; i < n_valtype_map; ++i) {
177 if (valtype_map[i].VT == VT) {
178 retval = valtype_map + i;
186 cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
187 << MVT::getValueTypeString(VT)
197 //===--------------------------------------------------------------------===//
198 /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
199 /// instructions for SelectionDAG operations.
201 class SPUDAGToDAGISel :
202 public SelectionDAGISel
204 SPUTargetMachine &TM;
205 SPUTargetLowering &SPUtli;
206 unsigned GlobalBaseReg;
209 SPUDAGToDAGISel(SPUTargetMachine &tm) :
210 SelectionDAGISel(*tm.getTargetLowering()),
212 SPUtli(*tm.getTargetLowering())
215 virtual bool runOnFunction(Function &Fn) {
216 // Make sure we re-emit a set of the global base reg if necessary
218 SelectionDAGISel::runOnFunction(Fn);
222 /// getI32Imm - Return a target constant with the specified value, of type
224 inline SDOperand getI32Imm(uint32_t Imm) {
225 return CurDAG->getTargetConstant(Imm, MVT::i32);
228 /// getI64Imm - Return a target constant with the specified value, of type
230 inline SDOperand getI64Imm(uint64_t Imm) {
231 return CurDAG->getTargetConstant(Imm, MVT::i64);
234 /// getSmallIPtrImm - Return a target constant of pointer type.
235 inline SDOperand getSmallIPtrImm(unsigned Imm) {
236 return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
239 /// Select - Convert the specified operand from a target-independent to a
240 /// target-specific node if it hasn't already been changed.
241 SDNode *Select(SDOperand Op);
243 /// Return true if the address N is a RI7 format address [r+imm]
244 bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
247 //! Returns true if the address N is an A-form (local store) address
248 bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
251 //! D-form address predicate
252 bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
255 //! Address predicate if N can be expressed as an indexed [r+r] operation.
256 bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
259 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
260 /// inline asm expressions.
261 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
263 std::vector<SDOperand> &OutOps,
266 switch (ConstraintCode) {
267 default: return true;
269 if (!SelectDFormAddr(Op, Op, Op0, Op1)
270 && !SelectAFormAddr(Op, Op, Op0, Op1))
271 SelectXFormAddr(Op, Op, Op0, Op1);
273 case 'o': // offsetable
274 if (!SelectDFormAddr(Op, Op, Op0, Op1)
275 && !SelectAFormAddr(Op, Op, Op0, Op1)) {
277 AddToISelQueue(Op0); // r+0.
278 Op1 = getSmallIPtrImm(0);
281 case 'v': // not offsetable
283 assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
285 SelectAddrIdxOnly(Op, Op, Op0, Op1);
290 OutOps.push_back(Op0);
291 OutOps.push_back(Op1);
295 /// InstructionSelectBasicBlock - This callback is invoked by
296 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
297 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
299 virtual const char *getPassName() const {
300 return "Cell SPU DAG->DAG Pattern Instruction Selection";
303 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
304 /// this target when scheduling the DAG.
305 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
306 const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
307 assert(II && "No InstrInfo?");
308 return new SPUHazardRecognizer(*II);
311 // Include the pieces autogenerated from the target description.
312 #include "SPUGenDAGISel.inc"
315 /// InstructionSelectBasicBlock - This callback is invoked by
316 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
318 SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
322 // Select target instructions for the DAG.
323 DAG.setRoot(SelectRoot(DAG.getRoot()));
324 DAG.RemoveDeadNodes();
326 // Emit machine code to BB.
327 ScheduleAndEmitDAG(DAG);
331 SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
333 unsigned Opc = N.getOpcode();
334 unsigned VT = N.getValueType();
335 MVT::ValueType PtrVT = SPUtli.getPointerTy();
336 ConstantSDNode *CN = 0;
339 if (Opc == ISD::ADD) {
340 SDOperand Op0 = N.getOperand(0);
341 SDOperand Op1 = N.getOperand(1);
342 if (Op1.getOpcode() == ISD::Constant ||
343 Op1.getOpcode() == ISD::TargetConstant) {
344 CN = cast<ConstantSDNode>(Op1);
345 Imm = int(CN->getValue());
347 Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
352 } else if (Opc == ISD::GlobalAddress
353 || Opc == ISD::TargetGlobalAddress
354 || Opc == ISD::Register) {
355 // Plain old local store address:
356 Disp = CurDAG->getTargetConstant(0, VT);
359 } else if (Opc == SPUISD::DFormAddr) {
360 // D-Form address: This is pretty straightforward, naturally...
361 CN = cast<ConstantSDNode>(N.getOperand(1));
362 assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
363 Imm = unsigned(CN->getValue());
365 Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
366 Base = N.getOperand(0);
375 \arg Op The ISD instructio operand
376 \arg N The address to be tested
377 \arg Base The base address
378 \arg Index The base address index
381 SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
383 // These match the addr256k operand type:
384 MVT::ValueType PtrVT = SPUtli.getPointerTy();
385 MVT::ValueType OffsVT = MVT::i16;
387 switch (N.getOpcode()) {
389 case ISD::TargetConstant: {
390 // Loading from a constant address.
391 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
392 int Imm = (int)CN->getValue();
393 if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
394 Base = CurDAG->getTargetConstant(Imm, PtrVT);
395 // Note that this operand will be ignored by the assembly printer...
396 Index = CurDAG->getTargetConstant(0, OffsVT);
400 case ISD::ConstantPool:
401 case ISD::TargetConstantPool: {
402 // The constant pool address is N. Base is a dummy that will be ignored by
403 // the assembly printer.
405 Index = CurDAG->getTargetConstant(0, OffsVT);
409 case ISD::GlobalAddress:
410 case ISD::TargetGlobalAddress: {
411 // The global address is N. Base is a dummy that is ignored by the
414 Index = CurDAG->getTargetConstant(0, OffsVT);
423 \arg Op The ISD instruction (ignored)
424 \arg N The address to be tested
425 \arg Base Base address register/pointer
426 \arg Index Base address index
428 Examine the input address by a base register plus a signed 10-bit
429 displacement, [r+I10] (D-form address).
431 \return true if \a N is a D-form address with \a Base and \a Index set
432 to non-empty SDOperand instances.
435 SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
437 unsigned Opc = N.getOpcode();
438 unsigned PtrTy = SPUtli.getPointerTy();
440 if (Opc == ISD::Register) {
442 Index = CurDAG->getTargetConstant(0, PtrTy);
444 } else if (Opc == ISD::FrameIndex) {
445 // Stack frame index must be less than 512 (divided by 16):
446 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
447 DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
448 << FI->getIndex() << "\n");
449 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
450 Base = CurDAG->getTargetConstant(0, PtrTy);
451 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
454 } else if (Opc == ISD::ADD) {
455 // Generated by getelementptr
456 const SDOperand Op0 = N.getOperand(0); // Frame index/base
457 const SDOperand Op1 = N.getOperand(1); // Offset within base
458 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
464 int32_t offset = (int32_t) CN->getSignExtended();
465 unsigned Opc0 = Op0.getOpcode();
467 if ((offset & 0xf) != 0) {
468 cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n";
473 if (Opc0 == ISD::FrameIndex) {
474 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
475 DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
476 << " frame index = " << FI->getIndex() << "\n");
478 if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
479 Base = CurDAG->getTargetConstant(offset, PtrTy);
480 Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
483 } else if (offset > SPUFrameInfo::minFrameOffset()
484 && offset < SPUFrameInfo::maxFrameOffset()) {
485 Base = CurDAG->getTargetConstant(offset, PtrTy);
486 if (Opc0 == ISD::GlobalAddress) {
487 // Convert global address to target global address
488 GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
489 Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
492 // Otherwise, just take operand 0
497 } else if (Opc == SPUISD::DFormAddr) {
498 // D-Form address: This is pretty straightforward, naturally...
499 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
500 assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
501 Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
502 Index = N.getOperand(0);
510 \arg Op The ISD instruction operand
511 \arg N The address operand
512 \arg Base The base pointer operand
513 \arg Index The offset/index operand
515 If the address \a N can be expressed as a [r + s10imm] address, returns false.
516 Otherwise, creates two operands, Base and Index that will become the [r+r]
520 SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
522 if (SelectAFormAddr(Op, N, Base, Index)
523 || SelectDFormAddr(Op, N, Base, Index))
526 unsigned Opc = N.getOpcode();
528 if (Opc == ISD::ADD) {
529 SDOperand N1 = N.getOperand(0);
530 SDOperand N2 = N.getOperand(1);
531 unsigned N1Opc = N1.getOpcode();
532 unsigned N2Opc = N2.getOpcode();
534 if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo)
535 || (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) {
536 Base = N.getOperand(0);
537 Index = N.getOperand(1);
540 cerr << "SelectXFormAddr: Unhandled ADD operands:\n";
548 } else if (N.getNumOperands() == 2) {
549 SDOperand N1 = N.getOperand(0);
550 SDOperand N2 = N.getOperand(1);
551 unsigned N1Opc = N1.getOpcode();
552 unsigned N2Opc = N2.getOpcode();
554 if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
555 && (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
556 Base = N.getOperand(0);
557 Index = N.getOperand(1);
561 cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
568 cerr << "SelectXFormAddr: Unhandled operand type:\n";
578 //! Convert the operand from a target-independent to a target-specific node
582 SPUDAGToDAGISel::Select(SDOperand Op) {
584 unsigned Opc = N->getOpcode();
586 if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
587 return NULL; // Already selected.
588 } else if (Opc == ISD::FrameIndex) {
589 // Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
590 int FI = cast<FrameIndexSDNode>(N)->getIndex();
591 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
593 DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
594 return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
595 CurDAG->getTargetConstant(0, MVT::i32));
596 } else if (Opc == SPUISD::LDRESULT) {
597 // Custom select instructions for LDRESULT
598 unsigned VT = N->getValueType(0);
599 SDOperand Arg = N->getOperand(0);
600 SDOperand Chain = N->getOperand(1);
601 SDOperand Zero = CurDAG->getTargetConstant(0, VT);
603 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
605 if (vtm->ldresult_ins == 0) {
606 cerr << "LDRESULT for unsupported type: "
607 << MVT::getValueTypeString(VT)
611 Opc = vtm->ldresult_ins;
614 AddToISelQueue(Zero);
615 AddToISelQueue(Chain);
616 Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
617 Chain = SDOperand(Result, 1);
621 return SelectCode(Op);
624 /// createPPCISelDag - This pass converts a legalized DAG into a
625 /// SPU-specific DAG, ready for instruction scheduling.
627 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
628 return new SPUDAGToDAGISel(TM);