1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SPUTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUISelLowering.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUFrameInfo.h"
18 #include "llvm/ADT/VectorExtras.h"
19 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetOptions.h"
37 // Used in getTargetNodeName() below
39 std::map<unsigned, const char *> node_names;
41 //! MVT::ValueType mapping to useful data for Cell SPU
42 struct valtype_map_s {
43 const MVT::ValueType valtype;
44 const int prefslot_byte;
47 const valtype_map_s valtype_map[] = {
58 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
60 const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT) {
61 const valtype_map_s *retval = 0;
63 for (size_t i = 0; i < n_valtype_map; ++i) {
64 if (valtype_map[i].valtype == VT) {
65 retval = valtype_map + i;
72 cerr << "getValueTypeMapEntry returns NULL for "
73 << MVT::getValueTypeString(VT)
82 //! Predicate that returns true if operand is a memory target
84 \arg Op Operand to test
85 \return true if the operand is a memory target (i.e., global
86 address, external symbol, constant pool) or an A-form
89 bool isMemoryOperand(const SDOperand &Op)
91 const unsigned Opc = Op.getOpcode();
92 return (Opc == ISD::GlobalAddress
93 || Opc == ISD::GlobalTLSAddress
94 || Opc == ISD::JumpTable
95 || Opc == ISD::ConstantPool
96 || Opc == ISD::ExternalSymbol
97 || Opc == ISD::TargetGlobalAddress
98 || Opc == ISD::TargetGlobalTLSAddress
99 || Opc == ISD::TargetJumpTable
100 || Opc == ISD::TargetConstantPool
101 || Opc == ISD::TargetExternalSymbol
102 || Opc == SPUISD::AFormAddr);
105 //! Predicate that returns true if the operand is an indirect target
106 bool isIndirectOperand(const SDOperand &Op)
108 const unsigned Opc = Op.getOpcode();
109 return (Opc == ISD::Register
110 || Opc == SPUISD::LDRESULT);
114 SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
115 : TargetLowering(TM),
118 // Fold away setcc operations if possible.
121 // Use _setjmp/_longjmp instead of setjmp/longjmp.
122 setUseUnderscoreSetJmp(true);
123 setUseUnderscoreLongJmp(true);
125 // Set up the SPU's register classes:
126 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
127 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
128 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
129 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
130 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
131 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
132 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
134 // SPU has no sign or zero extended loads for i1, i8, i16:
135 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
136 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
137 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
138 setTruncStoreAction(MVT::i8, MVT::i1, Custom);
139 setTruncStoreAction(MVT::i16, MVT::i1, Custom);
140 setTruncStoreAction(MVT::i32, MVT::i1, Custom);
141 setTruncStoreAction(MVT::i64, MVT::i1, Custom);
142 setTruncStoreAction(MVT::i128, MVT::i1, Custom);
144 setLoadXAction(ISD::EXTLOAD, MVT::i8, Custom);
145 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Custom);
146 setLoadXAction(ISD::ZEXTLOAD, MVT::i8, Custom);
147 setTruncStoreAction(MVT::i8 , MVT::i8, Custom);
148 setTruncStoreAction(MVT::i16 , MVT::i8, Custom);
149 setTruncStoreAction(MVT::i32 , MVT::i8, Custom);
150 setTruncStoreAction(MVT::i64 , MVT::i8, Custom);
151 setTruncStoreAction(MVT::i128, MVT::i8, Custom);
153 setLoadXAction(ISD::EXTLOAD, MVT::i16, Custom);
154 setLoadXAction(ISD::SEXTLOAD, MVT::i16, Custom);
155 setLoadXAction(ISD::ZEXTLOAD, MVT::i16, Custom);
157 // SPU constant load actions are custom lowered:
158 setOperationAction(ISD::Constant, MVT::i64, Custom);
159 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
160 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
162 // SPU's loads and stores have to be custom lowered:
163 for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
165 setOperationAction(ISD::LOAD, sctype, Custom);
166 setOperationAction(ISD::STORE, sctype, Custom);
169 // Custom lower BRCOND for i1, i8 to "promote" the result to
170 // i32 and i16, respectively.
171 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
173 // Expand the jumptable branches
174 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
175 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
176 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
178 // SPU has no intrinsics for these particular operations:
179 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
181 // PowerPC has no SREM/UREM instructions
182 setOperationAction(ISD::SREM, MVT::i32, Expand);
183 setOperationAction(ISD::UREM, MVT::i32, Expand);
184 setOperationAction(ISD::SREM, MVT::i64, Expand);
185 setOperationAction(ISD::UREM, MVT::i64, Expand);
187 // We don't support sin/cos/sqrt/fmod
188 setOperationAction(ISD::FSIN , MVT::f64, Expand);
189 setOperationAction(ISD::FCOS , MVT::f64, Expand);
190 setOperationAction(ISD::FREM , MVT::f64, Expand);
191 setOperationAction(ISD::FSIN , MVT::f32, Expand);
192 setOperationAction(ISD::FCOS , MVT::f32, Expand);
193 setOperationAction(ISD::FREM , MVT::f32, Expand);
195 // If we're enabling GP optimizations, use hardware square root
196 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
197 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
199 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
200 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
202 // SPU can do rotate right and left, so legalize it... but customize for i8
203 // because instructions don't exist.
204 setOperationAction(ISD::ROTR, MVT::i32, Legal);
205 setOperationAction(ISD::ROTR, MVT::i16, Legal);
206 setOperationAction(ISD::ROTR, MVT::i8, Custom);
207 setOperationAction(ISD::ROTL, MVT::i32, Legal);
208 setOperationAction(ISD::ROTL, MVT::i16, Legal);
209 setOperationAction(ISD::ROTL, MVT::i8, Custom);
210 // SPU has no native version of shift left/right for i8
211 setOperationAction(ISD::SHL, MVT::i8, Custom);
212 setOperationAction(ISD::SRL, MVT::i8, Custom);
213 setOperationAction(ISD::SRA, MVT::i8, Custom);
214 // And SPU needs custom lowering for shift left/right for i64
215 setOperationAction(ISD::SHL, MVT::i64, Custom);
216 setOperationAction(ISD::SRL, MVT::i64, Custom);
217 setOperationAction(ISD::SRA, MVT::i64, Custom);
219 // Custom lower i32 multiplications
220 setOperationAction(ISD::MUL, MVT::i32, Custom);
222 // Need to custom handle (some) common i8 math ops
223 setOperationAction(ISD::SUB, MVT::i8, Custom);
224 setOperationAction(ISD::MUL, MVT::i8, Custom);
226 // SPU does not have BSWAP. It does have i32 support CTLZ.
227 // CTPOP has to be custom lowered.
228 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
229 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
231 setOperationAction(ISD::CTPOP, MVT::i8, Custom);
232 setOperationAction(ISD::CTPOP, MVT::i16, Custom);
233 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
234 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
236 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
237 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
239 setOperationAction(ISD::CTLZ , MVT::i32, Legal);
241 // SPU has a version of select that implements (a&~c)|(b|c), just like
242 // select ought to work:
243 setOperationAction(ISD::SELECT, MVT::i1, Promote);
244 setOperationAction(ISD::SELECT, MVT::i8, Legal);
245 setOperationAction(ISD::SELECT, MVT::i16, Legal);
246 setOperationAction(ISD::SELECT, MVT::i32, Legal);
247 setOperationAction(ISD::SELECT, MVT::i64, Expand);
249 setOperationAction(ISD::SETCC, MVT::i1, Promote);
250 setOperationAction(ISD::SETCC, MVT::i8, Legal);
251 setOperationAction(ISD::SETCC, MVT::i16, Legal);
252 setOperationAction(ISD::SETCC, MVT::i32, Legal);
253 setOperationAction(ISD::SETCC, MVT::i64, Expand);
255 // Zero extension and sign extension for i64 have to be
257 setOperationAction(ISD::ZERO_EXTEND, MVT::i64, Custom);
258 setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
259 setOperationAction(ISD::ANY_EXTEND, MVT::i64, Custom);
261 // SPU has a legal FP -> signed INT instruction
262 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
264 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
265 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
267 // FDIV on SPU requires custom lowering
268 setOperationAction(ISD::FDIV, MVT::f32, Custom);
269 //setOperationAction(ISD::FDIV, MVT::f64, Custom);
271 // SPU has [U|S]INT_TO_FP
272 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
273 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
274 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
275 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
276 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
277 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
278 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
279 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
281 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
282 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
283 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
284 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
286 // We cannot sextinreg(i1). Expand to shifts.
287 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
289 // Support label based line numbers.
290 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
291 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
293 // We want to legalize GlobalAddress and ConstantPool nodes into the
294 // appropriate instructions to materialize the address.
295 for (unsigned sctype = (unsigned) MVT::i1; sctype < (unsigned) MVT::f128;
297 setOperationAction(ISD::GlobalAddress, sctype, Custom);
298 setOperationAction(ISD::ConstantPool, sctype, Custom);
299 setOperationAction(ISD::JumpTable, sctype, Custom);
302 // RET must be custom lowered, to meet ABI requirements
303 setOperationAction(ISD::RET, MVT::Other, Custom);
305 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
306 setOperationAction(ISD::VASTART , MVT::Other, Custom);
308 // Use the default implementation.
309 setOperationAction(ISD::VAARG , MVT::Other, Expand);
310 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
311 setOperationAction(ISD::VAEND , MVT::Other, Expand);
312 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
313 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
314 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
315 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
317 // Cell SPU has instructions for converting between i64 and fp.
318 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
319 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
321 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
322 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
324 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
325 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
327 // First set operation action for all vector types to expand. Then we
328 // will selectively turn on ones that can be effectively codegen'd.
329 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
330 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
331 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
332 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
333 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
334 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
336 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
337 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
338 // add/sub are legal for all supported vector VT's.
339 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
340 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
341 // mul has to be custom lowered.
342 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Custom);
344 setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
345 setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal);
346 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
347 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Legal);
348 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Legal);
349 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Legal);
351 // These operations need to be expanded:
352 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
353 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
354 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
355 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
356 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Custom);
358 // Custom lower build_vector, constant pool spills, insert and
359 // extract vector elements:
360 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
361 setOperationAction(ISD::ConstantPool, (MVT::ValueType)VT, Custom);
362 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Custom);
363 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
364 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
365 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
368 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
369 setOperationAction(ISD::AND, MVT::v16i8, Custom);
370 setOperationAction(ISD::OR, MVT::v16i8, Custom);
371 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
372 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
374 setShiftAmountType(MVT::i32);
375 setSetCCResultContents(ZeroOrOneSetCCResult);
377 setStackPointerRegisterToSaveRestore(SPU::R1);
379 // We have target-specific dag combine patterns for the following nodes:
380 setTargetDAGCombine(ISD::ADD);
381 setTargetDAGCombine(ISD::ZERO_EXTEND);
382 setTargetDAGCombine(ISD::SIGN_EXTEND);
383 setTargetDAGCombine(ISD::ANY_EXTEND);
385 computeRegisterProperties();
389 SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
391 if (node_names.empty()) {
392 node_names[(unsigned) SPUISD::RET_FLAG] = "SPUISD::RET_FLAG";
393 node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi";
394 node_names[(unsigned) SPUISD::Lo] = "SPUISD::Lo";
395 node_names[(unsigned) SPUISD::PCRelAddr] = "SPUISD::PCRelAddr";
396 node_names[(unsigned) SPUISD::AFormAddr] = "SPUISD::AFormAddr";
397 node_names[(unsigned) SPUISD::IndirectAddr] = "SPUISD::IndirectAddr";
398 node_names[(unsigned) SPUISD::LDRESULT] = "SPUISD::LDRESULT";
399 node_names[(unsigned) SPUISD::CALL] = "SPUISD::CALL";
400 node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB";
401 node_names[(unsigned) SPUISD::INSERT_MASK] = "SPUISD::INSERT_MASK";
402 node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
403 node_names[(unsigned) SPUISD::PROMOTE_SCALAR] = "SPUISD::PROMOTE_SCALAR";
404 node_names[(unsigned) SPUISD::EXTRACT_ELT0] = "SPUISD::EXTRACT_ELT0";
405 node_names[(unsigned) SPUISD::EXTRACT_ELT0_CHAINED] = "SPUISD::EXTRACT_ELT0_CHAINED";
406 node_names[(unsigned) SPUISD::EXTRACT_I1_ZEXT] = "SPUISD::EXTRACT_I1_ZEXT";
407 node_names[(unsigned) SPUISD::EXTRACT_I1_SEXT] = "SPUISD::EXTRACT_I1_SEXT";
408 node_names[(unsigned) SPUISD::EXTRACT_I8_ZEXT] = "SPUISD::EXTRACT_I8_ZEXT";
409 node_names[(unsigned) SPUISD::EXTRACT_I8_SEXT] = "SPUISD::EXTRACT_I8_SEXT";
410 node_names[(unsigned) SPUISD::MPY] = "SPUISD::MPY";
411 node_names[(unsigned) SPUISD::MPYU] = "SPUISD::MPYU";
412 node_names[(unsigned) SPUISD::MPYH] = "SPUISD::MPYH";
413 node_names[(unsigned) SPUISD::MPYHH] = "SPUISD::MPYHH";
414 node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS";
415 node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES";
416 node_names[(unsigned) SPUISD::VEC_SHL] = "SPUISD::VEC_SHL";
417 node_names[(unsigned) SPUISD::VEC_SRL] = "SPUISD::VEC_SRL";
418 node_names[(unsigned) SPUISD::VEC_SRA] = "SPUISD::VEC_SRA";
419 node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL";
420 node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR";
421 node_names[(unsigned) SPUISD::ROTQUAD_RZ_BYTES] =
422 "SPUISD::ROTQUAD_RZ_BYTES";
423 node_names[(unsigned) SPUISD::ROTQUAD_RZ_BITS] =
424 "SPUISD::ROTQUAD_RZ_BITS";
425 node_names[(unsigned) SPUISD::ROTBYTES_RIGHT_S] =
426 "SPUISD::ROTBYTES_RIGHT_S";
427 node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
428 node_names[(unsigned) SPUISD::ROTBYTES_LEFT_CHAINED] =
429 "SPUISD::ROTBYTES_LEFT_CHAINED";
430 node_names[(unsigned) SPUISD::FSMBI] = "SPUISD::FSMBI";
431 node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB";
432 node_names[(unsigned) SPUISD::FPInterp] = "SPUISD::FPInterp";
433 node_names[(unsigned) SPUISD::FPRecipEst] = "SPUISD::FPRecipEst";
434 node_names[(unsigned) SPUISD::SEXT32TO64] = "SPUISD::SEXT32TO64";
437 std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
439 return ((i != node_names.end()) ? i->second : 0);
443 SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
444 MVT::ValueType VT = Op.getValueType();
445 if (MVT::isInteger(VT))
451 //===----------------------------------------------------------------------===//
452 // Calling convention code:
453 //===----------------------------------------------------------------------===//
455 #include "SPUGenCallingConv.inc"
457 //===----------------------------------------------------------------------===//
458 // LowerOperation implementation
459 //===----------------------------------------------------------------------===//
461 /// Aligned load common code for CellSPU
463 \param[in] Op The SelectionDAG load or store operand
464 \param[in] DAG The selection DAG
465 \param[in] ST CellSPU subtarget information structure
466 \param[in,out] alignment Caller initializes this to the load or store node's
467 value from getAlignment(), may be updated while generating the aligned load
468 \param[in,out] alignOffs Aligned offset; set by AlignedLoad to the aligned
469 offset (divisible by 16, modulo 16 == 0)
470 \param[in,out] prefSlotOffs Preferred slot offset; set by AlignedLoad to the
471 offset of the preferred slot (modulo 16 != 0)
472 \param[in,out] VT Caller initializes this value type to the the load or store
473 node's loaded or stored value type; may be updated if an i1-extended load or
475 \param[out] was16aligned true if the base pointer had 16-byte alignment,
476 otherwise false. Can help to determine if the chunk needs to be rotated.
478 Both load and store lowering load a block of data aligned on a 16-byte
479 boundary. This is the common aligned load code shared between both.
482 AlignedLoad(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST,
484 unsigned &alignment, int &alignOffs, int &prefSlotOffs,
485 MVT::ValueType &VT, bool &was16aligned)
487 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
488 const valtype_map_s *vtm = getValueTypeMapEntry(VT);
489 SDOperand basePtr = LSN->getBasePtr();
490 SDOperand chain = LSN->getChain();
492 if (basePtr.getOpcode() == ISD::ADD) {
493 SDOperand Op1 = basePtr.Val->getOperand(1);
495 if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) {
496 const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
498 alignOffs = (int) CN->getValue();
499 prefSlotOffs = (int) (alignOffs & 0xf);
501 // Adjust the rotation amount to ensure that the final result ends up in
502 // the preferred slot:
503 prefSlotOffs -= vtm->prefslot_byte;
504 basePtr = basePtr.getOperand(0);
506 // Loading from memory, can we adjust alignment?
507 if (basePtr.getOpcode() == SPUISD::AFormAddr) {
508 SDOperand APtr = basePtr.getOperand(0);
509 if (APtr.getOpcode() == ISD::TargetGlobalAddress) {
510 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(APtr);
511 alignment = GSDN->getGlobal()->getAlignment();
516 prefSlotOffs = -vtm->prefslot_byte;
518 } else if (basePtr.getOpcode() == ISD::FrameIndex) {
519 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(basePtr);
520 alignOffs = int(FIN->getIndex() * SPUFrameInfo::stackSlotSize());
521 prefSlotOffs = (int) (alignOffs & 0xf);
522 prefSlotOffs -= vtm->prefslot_byte;
523 basePtr = DAG.getRegister(SPU::R1, VT);
526 prefSlotOffs = -vtm->prefslot_byte;
529 if (alignment == 16) {
530 // Realign the base pointer as a D-Form address:
531 if (!isMemoryOperand(basePtr) || (alignOffs & ~0xf) != 0) {
532 basePtr = DAG.getNode(ISD::ADD, PtrVT,
534 DAG.getConstant((alignOffs & ~0xf), PtrVT));
537 // Emit the vector load:
539 return DAG.getLoad(MVT::v16i8, chain, basePtr,
540 LSN->getSrcValue(), LSN->getSrcValueOffset(),
541 LSN->isVolatile(), 16);
544 // Unaligned load or we're using the "large memory" model, which means that
545 // we have to be very pessimistic:
546 if (isMemoryOperand(basePtr) || isIndirectOperand(basePtr)) {
547 basePtr = DAG.getNode(SPUISD::IndirectAddr, PtrVT, basePtr, DAG.getConstant(0, PtrVT));
551 basePtr = DAG.getNode(ISD::ADD, PtrVT, basePtr,
552 DAG.getConstant((alignOffs & ~0xf), PtrVT));
553 was16aligned = false;
554 return DAG.getLoad(MVT::v16i8, chain, basePtr,
555 LSN->getSrcValue(), LSN->getSrcValueOffset(),
556 LSN->isVolatile(), 16);
559 /// Custom lower loads for CellSPU
561 All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
562 within a 16-byte block, we have to rotate to extract the requested element.
565 LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
566 LoadSDNode *LN = cast<LoadSDNode>(Op);
567 SDOperand the_chain = LN->getChain();
568 MVT::ValueType VT = LN->getMemoryVT();
569 MVT::ValueType OpVT = Op.Val->getValueType(0);
570 ISD::LoadExtType ExtType = LN->getExtensionType();
571 unsigned alignment = LN->getAlignment();
574 switch (LN->getAddressingMode()) {
575 case ISD::UNINDEXED: {
579 AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned);
584 the_chain = result.getValue(1);
585 // Rotate the chunk if necessary
588 if (rotamt != 0 || !was16aligned) {
589 SDVTList vecvts = DAG.getVTList(MVT::v16i8, MVT::Other);
594 Ops[2] = DAG.getConstant(rotamt, MVT::i16);
596 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
597 LoadSDNode *LN1 = cast<LoadSDNode>(result);
598 Ops[2] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(),
599 DAG.getConstant(rotamt, PtrVT));
602 result = DAG.getNode(SPUISD::ROTBYTES_LEFT_CHAINED, vecvts, Ops, 3);
603 the_chain = result.getValue(1);
606 if (VT == OpVT || ExtType == ISD::EXTLOAD) {
608 MVT::ValueType vecVT = MVT::v16i8;
610 // Convert the loaded v16i8 vector to the appropriate vector type
611 // specified by the operand:
614 vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
616 vecVT = MVT::getVectorType(OpVT, (128 / MVT::getSizeInBits(OpVT)));
619 Ops[1] = DAG.getNode(ISD::BIT_CONVERT, vecVT, result);
620 scalarvts = DAG.getVTList((OpVT == VT ? VT : OpVT), MVT::Other);
621 result = DAG.getNode(SPUISD::EXTRACT_ELT0_CHAINED, scalarvts, Ops, 2);
622 the_chain = result.getValue(1);
624 // Handle the sign and zero-extending loads for i1 and i8:
627 if (ExtType == ISD::SEXTLOAD) {
628 NewOpC = (OpVT == MVT::i1
629 ? SPUISD::EXTRACT_I1_SEXT
630 : SPUISD::EXTRACT_I8_SEXT);
632 assert(ExtType == ISD::ZEXTLOAD);
633 NewOpC = (OpVT == MVT::i1
634 ? SPUISD::EXTRACT_I1_ZEXT
635 : SPUISD::EXTRACT_I8_ZEXT);
638 result = DAG.getNode(NewOpC, OpVT, result);
641 SDVTList retvts = DAG.getVTList(OpVT, MVT::Other);
642 SDOperand retops[2] = {
647 result = DAG.getNode(SPUISD::LDRESULT, retvts,
648 retops, sizeof(retops) / sizeof(retops[0]));
655 case ISD::LAST_INDEXED_MODE:
656 cerr << "LowerLOAD: Got a LoadSDNode with an addr mode other than "
658 cerr << (unsigned) LN->getAddressingMode() << "\n";
666 /// Custom lower stores for CellSPU
668 All CellSPU stores are aligned to 16-byte boundaries, so for elements
669 within a 16-byte block, we have to generate a shuffle to insert the
670 requested element into its place, then store the resulting block.
673 LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
674 StoreSDNode *SN = cast<StoreSDNode>(Op);
675 SDOperand Value = SN->getValue();
676 MVT::ValueType VT = Value.getValueType();
677 MVT::ValueType StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
678 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
679 unsigned alignment = SN->getAlignment();
681 switch (SN->getAddressingMode()) {
682 case ISD::UNINDEXED: {
683 int chunk_offset, slot_offset;
686 // The vector type we really want to load from the 16-byte chunk, except
687 // in the case of MVT::i1, which has to be v16i8.
688 unsigned vecVT, stVecVT = MVT::v16i8;
691 stVecVT = MVT::getVectorType(StVT, (128 / MVT::getSizeInBits(StVT)));
692 vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
694 SDOperand alignLoadVec =
695 AlignedLoad(Op, DAG, ST, SN, alignment,
696 chunk_offset, slot_offset, VT, was16aligned);
698 if (alignLoadVec.Val == 0)
701 LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
702 SDOperand basePtr = LN->getBasePtr();
703 SDOperand the_chain = alignLoadVec.getValue(1);
704 SDOperand theValue = SN->getValue();
708 && (theValue.getOpcode() == ISD::AssertZext
709 || theValue.getOpcode() == ISD::AssertSext)) {
710 // Drill down and get the value for zero- and sign-extended
712 theValue = theValue.getOperand(0);
717 SDOperand insertEltOffs = DAG.getConstant(chunk_offset, PtrVT);
718 SDOperand insertEltPtr;
719 SDOperand insertEltOp;
721 // If the base pointer is already a D-form address, then just create
722 // a new D-form address with a slot offset and the orignal base pointer.
723 // Otherwise generate a D-form address with the slot offset relative
724 // to the stack pointer, which is always aligned.
725 DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
726 DEBUG(basePtr.Val->dump(&DAG));
729 if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
730 (basePtr.getOpcode() == ISD::ADD
731 && basePtr.getOperand(0).getOpcode() == SPUISD::IndirectAddr)) {
732 insertEltPtr = basePtr;
734 insertEltPtr = DAG.getNode(ISD::ADD, PtrVT, basePtr, insertEltOffs);
737 insertEltOp = DAG.getNode(SPUISD::INSERT_MASK, stVecVT, insertEltPtr);
738 result = DAG.getNode(SPUISD::SHUFB, vecVT,
739 DAG.getNode(ISD::SCALAR_TO_VECTOR, vecVT, theValue),
741 DAG.getNode(ISD::BIT_CONVERT, vecVT, insertEltOp));
743 result = DAG.getStore(the_chain, result, basePtr,
744 LN->getSrcValue(), LN->getSrcValueOffset(),
745 LN->isVolatile(), LN->getAlignment());
754 case ISD::LAST_INDEXED_MODE:
755 cerr << "LowerLOAD: Got a LoadSDNode with an addr mode other than "
757 cerr << (unsigned) SN->getAddressingMode() << "\n";
765 /// Generate the address of a constant pool entry.
767 LowerConstantPool(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
768 MVT::ValueType PtrVT = Op.getValueType();
769 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
770 Constant *C = CP->getConstVal();
771 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
772 SDOperand Zero = DAG.getConstant(0, PtrVT);
773 const TargetMachine &TM = DAG.getTarget();
775 if (TM.getRelocationModel() == Reloc::Static) {
776 if (!ST->usingLargeMem()) {
777 // Just return the SDOperand with the constant pool address in it.
778 return DAG.getNode(SPUISD::AFormAddr, PtrVT, CPI, Zero);
780 SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, CPI, Zero);
781 SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, CPI, Zero);
782 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
787 "LowerConstantPool: Relocation model other than static not supported.");
792 LowerJumpTable(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
793 MVT::ValueType PtrVT = Op.getValueType();
794 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
795 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
796 SDOperand Zero = DAG.getConstant(0, PtrVT);
797 const TargetMachine &TM = DAG.getTarget();
799 if (TM.getRelocationModel() == Reloc::Static) {
800 if (!ST->usingLargeMem()) {
801 return DAG.getNode(SPUISD::AFormAddr, PtrVT, JTI, Zero);
803 SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, JTI, Zero);
804 SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, JTI, Zero);
805 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
810 "LowerJumpTable: Relocation model other than static not supported.");
815 LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
816 MVT::ValueType PtrVT = Op.getValueType();
817 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
818 GlobalValue *GV = GSDN->getGlobal();
819 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
820 const TargetMachine &TM = DAG.getTarget();
821 SDOperand Zero = DAG.getConstant(0, PtrVT);
823 if (TM.getRelocationModel() == Reloc::Static) {
824 if (!ST->usingLargeMem()) {
825 return DAG.getNode(SPUISD::AFormAddr, PtrVT, GA, Zero);
827 SDOperand Hi = DAG.getNode(SPUISD::Hi, PtrVT, GA, Zero);
828 SDOperand Lo = DAG.getNode(SPUISD::Lo, PtrVT, GA, Zero);
829 return DAG.getNode(SPUISD::IndirectAddr, PtrVT, Hi, Lo);
832 cerr << "LowerGlobalAddress: Relocation model other than static not "
841 //! Custom lower i64 integer constants
843 This code inserts all of the necessary juggling that needs to occur to load
844 a 64-bit constant into a register.
847 LowerConstant(SDOperand Op, SelectionDAG &DAG) {
848 unsigned VT = Op.getValueType();
849 ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
851 if (VT == MVT::i64) {
852 SDOperand T = DAG.getConstant(CN->getValue(), MVT::i64);
853 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
854 DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
856 cerr << "LowerConstant: unhandled constant type "
857 << MVT::getValueTypeString(VT)
866 //! Custom lower double precision floating point constants
868 LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
869 unsigned VT = Op.getValueType();
870 ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
873 "LowerConstantFP: Node is not ConstantFPSDNode");
875 if (VT == MVT::f64) {
876 uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
877 return DAG.getNode(ISD::BIT_CONVERT, VT,
878 LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
884 //! Lower MVT::i1, MVT::i8 brcond to a promoted type (MVT::i32, MVT::i16)
886 LowerBRCOND(SDOperand Op, SelectionDAG &DAG)
888 SDOperand Cond = Op.getOperand(1);
889 MVT::ValueType CondVT = Cond.getValueType();
890 MVT::ValueType CondNVT;
892 if (CondVT == MVT::i1 || CondVT == MVT::i8) {
893 CondNVT = (CondVT == MVT::i1 ? MVT::i32 : MVT::i16);
894 return DAG.getNode(ISD::BRCOND, Op.getValueType(),
896 DAG.getNode(ISD::ZERO_EXTEND, CondNVT, Op.getOperand(1)),
899 return SDOperand(); // Unchanged
903 LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
905 MachineFunction &MF = DAG.getMachineFunction();
906 MachineFrameInfo *MFI = MF.getFrameInfo();
907 MachineRegisterInfo &RegInfo = MF.getRegInfo();
908 SmallVector<SDOperand, 8> ArgValues;
909 SDOperand Root = Op.getOperand(0);
910 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
912 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
913 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
915 unsigned ArgOffset = SPUFrameInfo::minStackSize();
916 unsigned ArgRegIdx = 0;
917 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
919 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
921 // Add DAG nodes to load the arguments or copy them out of registers.
922 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
924 bool needsLoad = false;
925 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
926 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
930 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
931 << MVT::getValueTypeString(ObjectVT)
936 if (!isVarArg && ArgRegIdx < NumArgRegs) {
937 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R8CRegClass);
938 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
939 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i8);
946 if (!isVarArg && ArgRegIdx < NumArgRegs) {
947 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
948 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
949 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i16);
956 if (!isVarArg && ArgRegIdx < NumArgRegs) {
957 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
958 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
959 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
966 if (!isVarArg && ArgRegIdx < NumArgRegs) {
967 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64CRegClass);
968 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
969 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
976 if (!isVarArg && ArgRegIdx < NumArgRegs) {
977 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
978 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
979 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f32);
986 if (!isVarArg && ArgRegIdx < NumArgRegs) {
987 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64FPRegClass);
988 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
989 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1001 if (!isVarArg && ArgRegIdx < NumArgRegs) {
1002 unsigned VReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1003 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
1004 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1012 // We need to load the argument to a virtual register if we determined above
1013 // that we ran out of physical registers of the appropriate type
1015 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1016 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1017 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1018 ArgOffset += StackSlotSize;
1021 ArgValues.push_back(ArgVal);
1024 // If the function takes variable number of arguments, make a frame index for
1025 // the start of the first vararg value... for expansion of llvm.va_start.
1027 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1029 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1030 // If this function is vararg, store any remaining integer argument regs to
1031 // their spots on the stack so that they may be loaded by deferencing the
1032 // result of va_next.
1033 SmallVector<SDOperand, 8> MemOps;
1034 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
1035 unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass);
1036 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
1037 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1038 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1039 MemOps.push_back(Store);
1040 // Increment the address by four for the next argument to store
1041 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1042 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1044 if (!MemOps.empty())
1045 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1048 ArgValues.push_back(Root);
1050 // Return the new list of results.
1051 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1052 Op.Val->value_end());
1053 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1056 /// isLSAAddress - Return the immediate to use if the specified
1057 /// value is representable as a LSA address.
1058 static SDNode *isLSAAddress(SDOperand Op, SelectionDAG &DAG) {
1059 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1062 int Addr = C->getValue();
1063 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1064 (Addr << 14 >> 14) != Addr)
1065 return 0; // Top 14 bits have to be sext of immediate.
1067 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1072 LowerCALL(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
1073 SDOperand Chain = Op.getOperand(0);
1075 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1076 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1078 SDOperand Callee = Op.getOperand(4);
1079 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1080 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1081 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
1082 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
1084 // Handy pointer type
1085 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1087 // Accumulate how many bytes are to be pushed on the stack, including the
1088 // linkage area, and parameter passing area. According to the SPU ABI,
1089 // we minimally need space for [LR] and [SP]
1090 unsigned NumStackBytes = SPUFrameInfo::minStackSize();
1092 // Set up a copy of the stack pointer for use loading and storing any
1093 // arguments that may not fit in the registers available for argument
1095 SDOperand StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1097 // Figure out which arguments are going to go in registers, and which in
1099 unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
1100 unsigned ArgRegIdx = 0;
1102 // Keep track of registers passing arguments
1103 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1104 // And the arguments passed on the stack
1105 SmallVector<SDOperand, 8> MemOpChains;
1107 for (unsigned i = 0; i != NumOps; ++i) {
1108 SDOperand Arg = Op.getOperand(5+2*i);
1110 // PtrOff will be used to store the current argument to the stack if a
1111 // register cannot be found for it.
1112 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1113 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1115 switch (Arg.getValueType()) {
1116 default: assert(0 && "Unexpected ValueType for argument!");
1120 if (ArgRegIdx != NumArgRegs) {
1121 RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
1123 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1124 ArgOffset += StackSlotSize;
1129 if (ArgRegIdx != NumArgRegs) {
1130 RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
1132 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1133 ArgOffset += StackSlotSize;
1140 if (ArgRegIdx != NumArgRegs) {
1141 RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
1143 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1144 ArgOffset += StackSlotSize;
1150 // Update number of stack bytes actually used, insert a call sequence start
1151 NumStackBytes = (ArgOffset - SPUFrameInfo::minStackSize());
1152 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumStackBytes, PtrVT));
1154 if (!MemOpChains.empty()) {
1155 // Adjust the stack pointer for the stack arguments.
1156 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1157 &MemOpChains[0], MemOpChains.size());
1160 // Build a sequence of copy-to-reg nodes chained together with token chain
1161 // and flag operands which copy the outgoing args into the appropriate regs.
1163 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1164 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1166 InFlag = Chain.getValue(1);
1169 std::vector<MVT::ValueType> NodeTys;
1170 NodeTys.push_back(MVT::Other); // Returns a chain
1171 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1173 SmallVector<SDOperand, 8> Ops;
1174 unsigned CallOpc = SPUISD::CALL;
1176 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1177 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1178 // node so that legalize doesn't hack it.
1179 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1180 GlobalValue *GV = G->getGlobal();
1181 unsigned CalleeVT = Callee.getValueType();
1182 SDOperand Zero = DAG.getConstant(0, PtrVT);
1183 SDOperand GA = DAG.getTargetGlobalAddress(GV, CalleeVT);
1185 if (!ST->usingLargeMem()) {
1186 // Turn calls to targets that are defined (i.e., have bodies) into BRSL
1187 // style calls, otherwise, external symbols are BRASL calls. This assumes
1188 // that declared/defined symbols are in the same compilation unit and can
1189 // be reached through PC-relative jumps.
1192 // This may be an unsafe assumption for JIT and really large compilation
1194 if (GV->isDeclaration()) {
1195 Callee = DAG.getNode(SPUISD::AFormAddr, CalleeVT, GA, Zero);
1197 Callee = DAG.getNode(SPUISD::PCRelAddr, CalleeVT, GA, Zero);
1200 // "Large memory" mode: Turn all calls into indirect calls with a X-form
1202 Callee = DAG.getNode(SPUISD::IndirectAddr, PtrVT, GA, Zero);
1204 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1205 Callee = DAG.getExternalSymbol(S->getSymbol(), Callee.getValueType());
1206 else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
1207 // If this is an absolute destination address that appears to be a legal
1208 // local store address, use the munged value.
1209 Callee = SDOperand(Dest, 0);
1212 Ops.push_back(Chain);
1213 Ops.push_back(Callee);
1215 // Add argument registers to the end of the list so that they are known live
1217 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1218 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1219 RegsToPass[i].second.getValueType()));
1222 Ops.push_back(InFlag);
1223 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1224 InFlag = Chain.getValue(1);
1226 Chain = DAG.getCALLSEQ_END(Chain,
1227 DAG.getConstant(NumStackBytes, PtrVT),
1228 DAG.getConstant(0, PtrVT),
1230 if (Op.Val->getValueType(0) != MVT::Other)
1231 InFlag = Chain.getValue(1);
1233 SDOperand ResultVals[3];
1234 unsigned NumResults = 0;
1237 // If the call has results, copy the values out of the ret val registers.
1238 switch (Op.Val->getValueType(0)) {
1239 default: assert(0 && "Unexpected ret value!");
1240 case MVT::Other: break;
1242 if (Op.Val->getValueType(1) == MVT::i32) {
1243 Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1);
1244 ResultVals[0] = Chain.getValue(0);
1245 Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
1246 Chain.getValue(2)).getValue(1);
1247 ResultVals[1] = Chain.getValue(0);
1249 NodeTys.push_back(MVT::i32);
1251 Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32, InFlag).getValue(1);
1252 ResultVals[0] = Chain.getValue(0);
1255 NodeTys.push_back(MVT::i32);
1258 Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i64, InFlag).getValue(1);
1259 ResultVals[0] = Chain.getValue(0);
1261 NodeTys.push_back(MVT::i64);
1265 Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
1266 InFlag).getValue(1);
1267 ResultVals[0] = Chain.getValue(0);
1269 NodeTys.push_back(Op.Val->getValueType(0));
1276 Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
1277 InFlag).getValue(1);
1278 ResultVals[0] = Chain.getValue(0);
1280 NodeTys.push_back(Op.Val->getValueType(0));
1284 NodeTys.push_back(MVT::Other);
1286 // If the function returns void, just return the chain.
1287 if (NumResults == 0)
1290 // Otherwise, merge everything together with a MERGE_VALUES node.
1291 ResultVals[NumResults++] = Chain;
1292 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1293 ResultVals, NumResults);
1294 return Res.getValue(Op.ResNo);
1298 LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1299 SmallVector<CCValAssign, 16> RVLocs;
1300 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1301 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1302 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1303 CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
1305 // If this is the first return lowered for this function, add the regs to the
1306 // liveout set for the function.
1307 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1308 for (unsigned i = 0; i != RVLocs.size(); ++i)
1309 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1312 SDOperand Chain = Op.getOperand(0);
1315 // Copy the result values into the output registers.
1316 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1317 CCValAssign &VA = RVLocs[i];
1318 assert(VA.isRegLoc() && "Can only return in registers!");
1319 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1320 Flag = Chain.getValue(1);
1324 return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
1326 return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
1330 //===----------------------------------------------------------------------===//
1331 // Vector related lowering:
1332 //===----------------------------------------------------------------------===//
1334 static ConstantSDNode *
1335 getVecImm(SDNode *N) {
1336 SDOperand OpVal(0, 0);
1338 // Check to see if this buildvec has a single non-undef value in its elements.
1339 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1340 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1342 OpVal = N->getOperand(i);
1343 else if (OpVal != N->getOperand(i))
1347 if (OpVal.Val != 0) {
1348 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1353 return 0; // All UNDEF: use implicit def.; not Constant node
1356 /// get_vec_i18imm - Test if this vector is a vector filled with the same value
1357 /// and the value fits into an unsigned 18-bit constant, and if so, return the
1359 SDOperand SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
1360 MVT::ValueType ValueType) {
1361 if (ConstantSDNode *CN = getVecImm(N)) {
1362 uint64_t Value = CN->getValue();
1363 if (ValueType == MVT::i64) {
1364 uint64_t UValue = CN->getValue();
1365 uint32_t upper = uint32_t(UValue >> 32);
1366 uint32_t lower = uint32_t(UValue);
1369 Value = Value >> 32;
1371 if (Value <= 0x3ffff)
1372 return DAG.getConstant(Value, ValueType);
1378 /// get_vec_i16imm - Test if this vector is a vector filled with the same value
1379 /// and the value fits into a signed 16-bit constant, and if so, return the
1381 SDOperand SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
1382 MVT::ValueType ValueType) {
1383 if (ConstantSDNode *CN = getVecImm(N)) {
1384 int64_t Value = CN->getSignExtended();
1385 if (ValueType == MVT::i64) {
1386 uint64_t UValue = CN->getValue();
1387 uint32_t upper = uint32_t(UValue >> 32);
1388 uint32_t lower = uint32_t(UValue);
1391 Value = Value >> 32;
1393 if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
1394 return DAG.getConstant(Value, ValueType);
1401 /// get_vec_i10imm - Test if this vector is a vector filled with the same value
1402 /// and the value fits into a signed 10-bit constant, and if so, return the
1404 SDOperand SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
1405 MVT::ValueType ValueType) {
1406 if (ConstantSDNode *CN = getVecImm(N)) {
1407 int64_t Value = CN->getSignExtended();
1408 if (ValueType == MVT::i64) {
1409 uint64_t UValue = CN->getValue();
1410 uint32_t upper = uint32_t(UValue >> 32);
1411 uint32_t lower = uint32_t(UValue);
1414 Value = Value >> 32;
1416 if (isS10Constant(Value))
1417 return DAG.getConstant(Value, ValueType);
1423 /// get_vec_i8imm - Test if this vector is a vector filled with the same value
1424 /// and the value fits into a signed 8-bit constant, and if so, return the
1427 /// @note: The incoming vector is v16i8 because that's the only way we can load
1428 /// constant vectors. Thus, we test to see if the upper and lower bytes are the
1430 SDOperand SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
1431 MVT::ValueType ValueType) {
1432 if (ConstantSDNode *CN = getVecImm(N)) {
1433 int Value = (int) CN->getValue();
1434 if (ValueType == MVT::i16
1435 && Value <= 0xffff /* truncated from uint64_t */
1436 && ((short) Value >> 8) == ((short) Value & 0xff))
1437 return DAG.getConstant(Value & 0xff, ValueType);
1438 else if (ValueType == MVT::i8
1439 && (Value & 0xff) == Value)
1440 return DAG.getConstant(Value, ValueType);
1446 /// get_ILHUvec_imm - Test if this vector is a vector filled with the same value
1447 /// and the value fits into a signed 16-bit constant, and if so, return the
1449 SDOperand SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
1450 MVT::ValueType ValueType) {
1451 if (ConstantSDNode *CN = getVecImm(N)) {
1452 uint64_t Value = CN->getValue();
1453 if ((ValueType == MVT::i32
1454 && ((unsigned) Value & 0xffff0000) == (unsigned) Value)
1455 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1456 return DAG.getConstant(Value >> 16, ValueType);
1462 /// get_v4i32_imm - Catch-all for general 32-bit constant vectors
1463 SDOperand SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
1464 if (ConstantSDNode *CN = getVecImm(N)) {
1465 return DAG.getConstant((unsigned) CN->getValue(), MVT::i32);
1471 /// get_v4i32_imm - Catch-all for general 64-bit constant vectors
1472 SDOperand SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
1473 if (ConstantSDNode *CN = getVecImm(N)) {
1474 return DAG.getConstant((unsigned) CN->getValue(), MVT::i64);
1480 // If this is a vector of constants or undefs, get the bits. A bit in
1481 // UndefBits is set if the corresponding element of the vector is an
1482 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1483 // zero. Return true if this is not an array of constants, false if it is.
1485 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1486 uint64_t UndefBits[2]) {
1487 // Start with zero'd results.
1488 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1490 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1491 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1492 SDOperand OpVal = BV->getOperand(i);
1494 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1495 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1497 uint64_t EltBits = 0;
1498 if (OpVal.getOpcode() == ISD::UNDEF) {
1499 uint64_t EltUndefBits = ~0ULL >> (64-EltBitSize);
1500 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1502 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1503 EltBits = CN->getValue() & (~0ULL >> (64-EltBitSize));
1504 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1505 const APFloat &apf = CN->getValueAPF();
1506 EltBits = (CN->getValueType(0) == MVT::f32
1507 ? FloatToBits(apf.convertToFloat())
1508 : DoubleToBits(apf.convertToDouble()));
1510 // Nonconstant element.
1514 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1517 //printf("%llx %llx %llx %llx\n",
1518 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1522 /// If this is a splat (repetition) of a value across the whole vector, return
1523 /// the smallest size that splats it. For example, "0x01010101010101..." is a
1524 /// splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1525 /// SplatSize = 1 byte.
1526 static bool isConstantSplat(const uint64_t Bits128[2],
1527 const uint64_t Undef128[2],
1529 uint64_t &SplatBits, uint64_t &SplatUndef,
1531 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1532 // the same as the lower 64-bits, ignoring undefs.
1533 uint64_t Bits64 = Bits128[0] | Bits128[1];
1534 uint64_t Undef64 = Undef128[0] & Undef128[1];
1535 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1536 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1537 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1538 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1540 if ((Bits128[0] & ~Undef128[1]) == (Bits128[1] & ~Undef128[0])) {
1541 if (MinSplatBits < 64) {
1543 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1545 if ((Bits64 & (~Undef64 >> 32)) == ((Bits64 >> 32) & ~Undef64)) {
1546 if (MinSplatBits < 32) {
1548 // If the top 16-bits are different than the lower 16-bits, ignoring
1549 // undefs, we have an i32 splat.
1550 if ((Bits32 & (~Undef32 >> 16)) == ((Bits32 >> 16) & ~Undef32)) {
1551 if (MinSplatBits < 16) {
1552 // If the top 8-bits are different than the lower 8-bits, ignoring
1553 // undefs, we have an i16 splat.
1554 if ((Bits16 & (uint16_t(~Undef16) >> 8)) == ((Bits16 >> 8) & ~Undef16)) {
1555 // Otherwise, we have an 8-bit splat.
1556 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1557 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1563 SplatUndef = Undef16;
1570 SplatUndef = Undef32;
1576 SplatBits = Bits128[0];
1577 SplatUndef = Undef128[0];
1583 return false; // Can't be a splat if two pieces don't match.
1586 // If this is a case we can't handle, return null and let the default
1587 // expansion code take care of it. If we CAN select this case, and if it
1588 // selects to a single instruction, return Op. Otherwise, if we can codegen
1589 // this case more efficiently than a constant pool load, lower it to the
1590 // sequence of ops that should be used.
1591 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1592 MVT::ValueType VT = Op.getValueType();
1593 // If this is a vector of constants or undefs, get the bits. A bit in
1594 // UndefBits is set if the corresponding element of the vector is an
1595 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1597 uint64_t VectorBits[2];
1598 uint64_t UndefBits[2];
1599 uint64_t SplatBits, SplatUndef;
1601 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
1602 || !isConstantSplat(VectorBits, UndefBits,
1603 MVT::getSizeInBits(MVT::getVectorElementType(VT)),
1604 SplatBits, SplatUndef, SplatSize))
1605 return SDOperand(); // Not a constant vector, not a splat.
1610 uint32_t Value32 = SplatBits;
1611 assert(SplatSize == 4
1612 && "LowerBUILD_VECTOR: Unexpected floating point vector element.");
1613 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1614 SDOperand T = DAG.getConstant(Value32, MVT::i32);
1615 return DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32,
1616 DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, T, T, T, T));
1620 uint64_t f64val = SplatBits;
1621 assert(SplatSize == 8
1622 && "LowerBUILD_VECTOR: 64-bit float vector element: unexpected size.");
1623 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1624 SDOperand T = DAG.getConstant(f64val, MVT::i64);
1625 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64,
1626 DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i64, T, T));
1630 // 8-bit constants have to be expanded to 16-bits
1631 unsigned short Value16 = SplatBits | (SplatBits << 8);
1633 for (int i = 0; i < 8; ++i)
1634 Ops[i] = DAG.getConstant(Value16, MVT::i16);
1635 return DAG.getNode(ISD::BIT_CONVERT, VT,
1636 DAG.getNode(ISD::BUILD_VECTOR, MVT::v8i16, Ops, 8));
1639 unsigned short Value16;
1641 Value16 = (unsigned short) (SplatBits & 0xffff);
1643 Value16 = (unsigned short) (SplatBits | (SplatBits << 8));
1644 SDOperand T = DAG.getConstant(Value16, MVT::getVectorElementType(VT));
1646 for (int i = 0; i < 8; ++i) Ops[i] = T;
1647 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops, 8);
1650 unsigned int Value = SplatBits;
1651 SDOperand T = DAG.getConstant(Value, MVT::getVectorElementType(VT));
1652 return DAG.getNode(ISD::BUILD_VECTOR, VT, T, T, T, T);
1655 uint64_t val = SplatBits;
1656 uint32_t upper = uint32_t(val >> 32);
1657 uint32_t lower = uint32_t(val);
1659 if (upper == lower) {
1660 // Magic constant that can be matched by IL, ILA, et. al.
1661 SDOperand Val = DAG.getTargetConstant(val, MVT::i64);
1662 return DAG.getNode(ISD::BUILD_VECTOR, VT, Val, Val);
1666 SmallVector<SDOperand, 16> ShufBytes;
1668 bool upper_special, lower_special;
1670 // NOTE: This code creates common-case shuffle masks that can be easily
1671 // detected as common expressions. It is not attempting to create highly
1672 // specialized masks to replace any and all 0's, 0xff's and 0x80's.
1674 // Detect if the upper or lower half is a special shuffle mask pattern:
1675 upper_special = (upper == 0 || upper == 0xffffffff || upper == 0x80000000);
1676 lower_special = (lower == 0 || lower == 0xffffffff || lower == 0x80000000);
1678 // Create lower vector if not a special pattern
1679 if (!lower_special) {
1680 SDOperand LO32C = DAG.getConstant(lower, MVT::i32);
1681 LO32 = DAG.getNode(ISD::BIT_CONVERT, VT,
1682 DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
1683 LO32C, LO32C, LO32C, LO32C));
1686 // Create upper vector if not a special pattern
1687 if (!upper_special) {
1688 SDOperand HI32C = DAG.getConstant(upper, MVT::i32);
1689 HI32 = DAG.getNode(ISD::BIT_CONVERT, VT,
1690 DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
1691 HI32C, HI32C, HI32C, HI32C));
1694 // If either upper or lower are special, then the two input operands are
1695 // the same (basically, one of them is a "don't care")
1700 if (lower_special && upper_special) {
1701 // Unhappy situation... both upper and lower are special, so punt with
1702 // a target constant:
1703 SDOperand Zero = DAG.getConstant(0, MVT::i32);
1704 HI32 = LO32 = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Zero, Zero,
1708 for (int i = 0; i < 4; ++i) {
1709 for (int j = 0; j < 4; ++j) {
1711 bool process_upper, process_lower;
1714 process_upper = (upper_special && (i & 1) == 0);
1715 process_lower = (lower_special && (i & 1) == 1);
1717 if (process_upper || process_lower) {
1718 if ((process_upper && upper == 0)
1719 || (process_lower && lower == 0))
1721 else if ((process_upper && upper == 0xffffffff)
1722 || (process_lower && lower == 0xffffffff))
1724 else if ((process_upper && upper == 0x80000000)
1725 || (process_lower && lower == 0x80000000))
1726 val = (j == 0 ? 0xe0 : 0x80);
1728 val = i * 4 + j + ((i & 1) * 16);
1730 ShufBytes.push_back(DAG.getConstant(val, MVT::i8));
1734 return DAG.getNode(SPUISD::SHUFB, VT, HI32, LO32,
1735 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
1736 &ShufBytes[0], ShufBytes.size()));
1744 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1745 /// which the Cell can operate. The code inspects V3 to ascertain whether the
1746 /// permutation vector, V3, is monotonically increasing with one "exception"
1747 /// element, e.g., (0, 1, _, 3). If this is the case, then generate a
1748 /// INSERT_MASK synthetic instruction. Otherwise, spill V3 to the constant pool.
1749 /// In either case, the net result is going to eventually invoke SHUFB to
1750 /// permute/shuffle the bytes from V1 and V2.
1752 /// INSERT_MASK is eventually selected as one of the C*D instructions, generate
1753 /// control word for byte/halfword/word insertion. This takes care of a single
1754 /// element move from V2 into V1.
1756 /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
1757 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1758 SDOperand V1 = Op.getOperand(0);
1759 SDOperand V2 = Op.getOperand(1);
1760 SDOperand PermMask = Op.getOperand(2);
1762 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1764 // If we have a single element being moved from V1 to V2, this can be handled
1765 // using the C*[DX] compute mask instructions, but the vector elements have
1766 // to be monotonically increasing with one exception element.
1767 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
1768 unsigned EltsFromV2 = 0;
1770 unsigned V2EltIdx0 = 0;
1771 unsigned CurrElt = 0;
1772 bool monotonic = true;
1773 if (EltVT == MVT::i8)
1775 else if (EltVT == MVT::i16)
1777 else if (EltVT == MVT::i32)
1780 assert(0 && "Unhandled vector type in LowerVECTOR_SHUFFLE");
1782 for (unsigned i = 0, e = PermMask.getNumOperands();
1783 EltsFromV2 <= 1 && monotonic && i != e;
1786 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1789 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1791 if (SrcElt >= V2EltIdx0) {
1793 V2Elt = (V2EltIdx0 - SrcElt) << 2;
1794 } else if (CurrElt != SrcElt) {
1801 if (EltsFromV2 == 1 && monotonic) {
1802 // Compute mask and shuffle
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1805 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
1806 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1807 // Initialize temporary register to 0
1808 SDOperand InitTempReg =
1809 DAG.getCopyToReg(DAG.getEntryNode(), VReg, DAG.getConstant(0, PtrVT));
1810 // Copy register's contents as index in INSERT_MASK:
1811 SDOperand ShufMaskOp =
1812 DAG.getNode(SPUISD::INSERT_MASK, V1.getValueType(),
1813 DAG.getTargetConstant(V2Elt, MVT::i32),
1814 DAG.getCopyFromReg(InitTempReg, VReg, PtrVT));
1815 // Use shuffle mask in SHUFB synthetic instruction:
1816 return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V2, V1, ShufMaskOp);
1818 // Convert the SHUFFLE_VECTOR mask's input element units to the actual bytes.
1819 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1821 SmallVector<SDOperand, 16> ResultMask;
1822 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1824 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1827 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1829 for (unsigned j = 0; j < BytesPerElement; ++j) {
1830 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1835 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
1836 &ResultMask[0], ResultMask.size());
1837 return DAG.getNode(SPUISD::SHUFB, V1.getValueType(), V1, V2, VPermMask);
1841 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1842 SDOperand Op0 = Op.getOperand(0); // Op0 = the scalar
1844 if (Op0.Val->getOpcode() == ISD::Constant) {
1845 // For a constant, build the appropriate constant vector, which will
1846 // eventually simplify to a vector register load.
1848 ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
1849 SmallVector<SDOperand, 16> ConstVecValues;
1853 // Create a constant vector:
1854 switch (Op.getValueType()) {
1855 default: assert(0 && "Unexpected constant value type in "
1856 "LowerSCALAR_TO_VECTOR");
1857 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1858 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1859 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1860 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1861 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1862 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1865 SDOperand CValue = DAG.getConstant(CN->getValue(), VT);
1866 for (size_t j = 0; j < n_copies; ++j)
1867 ConstVecValues.push_back(CValue);
1869 return DAG.getNode(ISD::BUILD_VECTOR, Op.getValueType(),
1870 &ConstVecValues[0], ConstVecValues.size());
1872 // Otherwise, copy the value from one register to another:
1873 switch (Op0.getValueType()) {
1874 default: assert(0 && "Unexpected value type in LowerSCALAR_TO_VECTOR");
1881 return DAG.getNode(SPUISD::PROMOTE_SCALAR, Op.getValueType(), Op0, Op0);
1888 static SDOperand LowerVectorMUL(SDOperand Op, SelectionDAG &DAG) {
1889 switch (Op.getValueType()) {
1891 SDOperand rA = Op.getOperand(0);
1892 SDOperand rB = Op.getOperand(1);
1893 SDOperand HiProd1 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rA, rB);
1894 SDOperand HiProd2 = DAG.getNode(SPUISD::MPYH, MVT::v4i32, rB, rA);
1895 SDOperand LoProd = DAG.getNode(SPUISD::MPYU, MVT::v4i32, rA, rB);
1896 SDOperand Residual1 = DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd1);
1898 return DAG.getNode(ISD::ADD, MVT::v4i32, Residual1, HiProd2);
1902 // Multiply two v8i16 vectors (pipeline friendly version):
1903 // a) multiply lower halves, mask off upper 16-bit of 32-bit product
1904 // b) multiply upper halves, rotate left by 16 bits (inserts 16 lower zeroes)
1905 // c) Use SELB to select upper and lower halves from the intermediate results
1907 // NOTE: We really want to move the FSMBI to earlier to actually get the
1908 // dual-issue. This code does manage to do this, even if it's a little on
1911 MachineFunction &MF = DAG.getMachineFunction();
1912 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1913 SDOperand Chain = Op.getOperand(0);
1914 SDOperand rA = Op.getOperand(0);
1915 SDOperand rB = Op.getOperand(1);
1916 unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1917 unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1920 DAG.getCopyToReg(Chain, FSMBIreg,
1921 DAG.getNode(SPUISD::FSMBI, MVT::v8i16,
1922 DAG.getConstant(0xcccc, MVT::i16)));
1925 DAG.getCopyToReg(FSMBOp, HiProdReg,
1926 DAG.getNode(SPUISD::MPYHH, MVT::v8i16, rA, rB));
1928 SDOperand HHProd_v4i32 =
1929 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
1930 DAG.getCopyFromReg(HHProd, HiProdReg, MVT::v4i32));
1932 return DAG.getNode(SPUISD::SELB, MVT::v8i16,
1933 DAG.getNode(SPUISD::MPY, MVT::v8i16, rA, rB),
1934 DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
1935 DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32,
1937 DAG.getConstant(16, MVT::i16))),
1938 DAG.getCopyFromReg(FSMBOp, FSMBIreg, MVT::v4i32));
1941 // This M00sE is N@stI! (apologies to Monty Python)
1943 // SPU doesn't know how to do any 8-bit multiplication, so the solution
1944 // is to break it all apart, sign extend, and reassemble the various
1945 // intermediate products.
1947 SDOperand rA = Op.getOperand(0);
1948 SDOperand rB = Op.getOperand(1);
1949 SDOperand c8 = DAG.getConstant(8, MVT::i32);
1950 SDOperand c16 = DAG.getConstant(16, MVT::i32);
1953 DAG.getNode(SPUISD::MPY, MVT::v8i16,
1954 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rA),
1955 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rB));
1957 SDOperand rALH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rA, c8);
1959 SDOperand rBLH = DAG.getNode(SPUISD::VEC_SRA, MVT::v8i16, rB, c8);
1962 DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16,
1963 DAG.getNode(SPUISD::MPY, MVT::v8i16, rALH, rBLH), c8);
1965 SDOperand FSMBmask = DAG.getNode(SPUISD::FSMBI, MVT::v8i16,
1966 DAG.getConstant(0x2222, MVT::i16));
1968 SDOperand LoProdParts =
1969 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
1970 DAG.getNode(SPUISD::SELB, MVT::v8i16,
1971 LLProd, LHProd, FSMBmask));
1973 SDOperand LoProdMask = DAG.getConstant(0xffff, MVT::i32);
1976 DAG.getNode(ISD::AND, MVT::v4i32,
1978 DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
1979 LoProdMask, LoProdMask,
1980 LoProdMask, LoProdMask));
1983 DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32,
1984 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rA), c16);
1987 DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32,
1988 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, rB), c16);
1991 DAG.getNode(SPUISD::MPY, MVT::v8i16,
1992 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rAH),
1993 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, rBH));
1995 SDOperand HHProd_1 =
1996 DAG.getNode(SPUISD::MPY, MVT::v8i16,
1997 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
1998 DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rAH, c8)),
1999 DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16,
2000 DAG.getNode(SPUISD::VEC_SRA, MVT::v4i32, rBH, c8)));
2003 DAG.getNode(SPUISD::SELB, MVT::v8i16,
2005 DAG.getNode(SPUISD::VEC_SHL, MVT::v8i16, HHProd_1, c8),
2009 DAG.getNode(SPUISD::VEC_SHL, MVT::v4i32, HHProd, c16);
2011 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8,
2012 DAG.getNode(ISD::OR, MVT::v4i32,
2017 cerr << "CellSPU: Unknown vector multiplication, got "
2018 << MVT::getValueTypeString(Op.getValueType())
2027 static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
2028 MachineFunction &MF = DAG.getMachineFunction();
2029 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2031 SDOperand A = Op.getOperand(0);
2032 SDOperand B = Op.getOperand(1);
2033 unsigned VT = Op.getValueType();
2035 unsigned VRegBR, VRegC;
2037 if (VT == MVT::f32) {
2038 VRegBR = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
2039 VRegC = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
2041 VRegBR = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
2042 VRegC = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
2044 // TODO: make sure we're feeding FPInterp the right arguments
2045 // Right now: fi B, frest(B)
2048 // (Floating Interpolate (FP Reciprocal Estimate B))
2050 DAG.getCopyToReg(DAG.getEntryNode(), VRegBR,
2051 DAG.getNode(SPUISD::FPInterp, VT, B,
2052 DAG.getNode(SPUISD::FPRecipEst, VT, B)));
2054 // Computes A * BRcpl and stores in a temporary register
2056 DAG.getCopyToReg(BRcpl, VRegC,
2057 DAG.getNode(ISD::FMUL, VT, A,
2058 DAG.getCopyFromReg(BRcpl, VRegBR, VT)));
2059 // What's the Chain variable do? It's magic!
2060 // TODO: set Chain = Op(0).getEntryNode()
2062 return DAG.getNode(ISD::FADD, VT,
2063 DAG.getCopyFromReg(AxBRcpl, VRegC, VT),
2064 DAG.getNode(ISD::FMUL, VT,
2065 DAG.getCopyFromReg(AxBRcpl, VRegBR, VT),
2066 DAG.getNode(ISD::FSUB, VT, A,
2067 DAG.getNode(ISD::FMUL, VT, B,
2068 DAG.getCopyFromReg(AxBRcpl, VRegC, VT)))));
2071 static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2072 unsigned VT = Op.getValueType();
2073 SDOperand N = Op.getOperand(0);
2074 SDOperand Elt = Op.getOperand(1);
2075 SDOperand ShufMask[16];
2076 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt);
2078 assert(C != 0 && "LowerEXTRACT_VECTOR_ELT expecting constant SDNode");
2080 int EltNo = (int) C->getValue();
2083 if (VT == MVT::i8 && EltNo >= 16)
2084 assert(0 && "SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
2085 else if (VT == MVT::i16 && EltNo >= 8)
2086 assert(0 && "SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
2087 else if (VT == MVT::i32 && EltNo >= 4)
2088 assert(0 && "SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
2089 else if (VT == MVT::i64 && EltNo >= 2)
2090 assert(0 && "SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
2092 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
2093 // i32 and i64: Element 0 is the preferred slot
2094 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT, N);
2097 // Need to generate shuffle mask and extract:
2098 int prefslot_begin = -1, prefslot_end = -1;
2099 int elt_byte = EltNo * MVT::getSizeInBits(VT) / 8;
2103 prefslot_begin = prefslot_end = 3;
2107 prefslot_begin = 2; prefslot_end = 3;
2111 prefslot_begin = 0; prefslot_end = 3;
2115 prefslot_begin = 0; prefslot_end = 7;
2120 assert(prefslot_begin != -1 && prefslot_end != -1 &&
2121 "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
2123 for (int i = 0; i < 16; ++i) {
2124 // zero fill uppper part of preferred slot, don't care about the
2126 unsigned int mask_val;
2128 if (i <= prefslot_end) {
2130 ((i < prefslot_begin)
2132 : elt_byte + (i - prefslot_begin));
2134 ShufMask[i] = DAG.getConstant(mask_val, MVT::i8);
2136 ShufMask[i] = ShufMask[i % (prefslot_end + 1)];
2139 SDOperand ShufMaskVec =
2140 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2142 sizeof(ShufMask) / sizeof(ShufMask[0]));
2144 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
2145 DAG.getNode(SPUISD::SHUFB, N.getValueType(),
2146 N, N, ShufMaskVec));
2150 static SDOperand LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2151 SDOperand VecOp = Op.getOperand(0);
2152 SDOperand ValOp = Op.getOperand(1);
2153 SDOperand IdxOp = Op.getOperand(2);
2154 MVT::ValueType VT = Op.getValueType();
2156 ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
2157 assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
2159 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2160 // Use $2 because it's always 16-byte aligned and it's available:
2161 SDOperand PtrBase = DAG.getRegister(SPU::R2, PtrVT);
2164 DAG.getNode(SPUISD::SHUFB, VT,
2165 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, ValOp),
2167 DAG.getNode(SPUISD::INSERT_MASK, VT,
2168 DAG.getNode(ISD::ADD, PtrVT,
2170 DAG.getConstant(CN->getValue(),
2176 static SDOperand LowerI8Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
2178 SDOperand N0 = Op.getOperand(0); // Everything has at least one operand
2180 assert(Op.getValueType() == MVT::i8);
2183 assert(0 && "Unhandled i8 math operator");
2187 // 8-bit subtraction: Promote the arguments up to 16-bits and truncate
2189 SDOperand N1 = Op.getOperand(1);
2190 N0 = (N0.getOpcode() != ISD::Constant
2191 ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
2192 : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
2193 N1 = (N1.getOpcode() != ISD::Constant
2194 ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N1)
2195 : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
2196 return DAG.getNode(ISD::TRUNCATE, MVT::i8,
2197 DAG.getNode(Opc, MVT::i16, N0, N1));
2201 SDOperand N1 = Op.getOperand(1);
2203 N0 = (N0.getOpcode() != ISD::Constant
2204 ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
2205 : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
2206 N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE);
2207 N1 = (N1.getOpcode() != ISD::Constant
2208 ? DAG.getNode(N1Opc, MVT::i16, N1)
2209 : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
2210 SDOperand ExpandArg =
2211 DAG.getNode(ISD::OR, MVT::i16, N0,
2212 DAG.getNode(ISD::SHL, MVT::i16,
2213 N0, DAG.getConstant(8, MVT::i16)));
2214 return DAG.getNode(ISD::TRUNCATE, MVT::i8,
2215 DAG.getNode(Opc, MVT::i16, ExpandArg, N1));
2219 SDOperand N1 = Op.getOperand(1);
2221 N0 = (N0.getOpcode() != ISD::Constant
2222 ? DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, N0)
2223 : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
2224 N1Opc = (N1.getValueType() < MVT::i16 ? ISD::ZERO_EXTEND : ISD::TRUNCATE);
2225 N1 = (N1.getOpcode() != ISD::Constant
2226 ? DAG.getNode(N1Opc, MVT::i16, N1)
2227 : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
2228 return DAG.getNode(ISD::TRUNCATE, MVT::i8,
2229 DAG.getNode(Opc, MVT::i16, N0, N1));
2232 SDOperand N1 = Op.getOperand(1);
2234 N0 = (N0.getOpcode() != ISD::Constant
2235 ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
2236 : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
2237 N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE);
2238 N1 = (N1.getOpcode() != ISD::Constant
2239 ? DAG.getNode(N1Opc, MVT::i16, N1)
2240 : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
2241 return DAG.getNode(ISD::TRUNCATE, MVT::i8,
2242 DAG.getNode(Opc, MVT::i16, N0, N1));
2245 SDOperand N1 = Op.getOperand(1);
2247 N0 = (N0.getOpcode() != ISD::Constant
2248 ? DAG.getNode(ISD::SIGN_EXTEND, MVT::i16, N0)
2249 : DAG.getConstant(cast<ConstantSDNode>(N0)->getValue(), MVT::i16));
2250 N1Opc = (N1.getValueType() < MVT::i16 ? ISD::SIGN_EXTEND : ISD::TRUNCATE);
2251 N1 = (N1.getOpcode() != ISD::Constant
2252 ? DAG.getNode(N1Opc, MVT::i16, N1)
2253 : DAG.getConstant(cast<ConstantSDNode>(N1)->getValue(), MVT::i16));
2254 return DAG.getNode(ISD::TRUNCATE, MVT::i8,
2255 DAG.getNode(Opc, MVT::i16, N0, N1));
2263 static SDOperand LowerI64Math(SDOperand Op, SelectionDAG &DAG, unsigned Opc)
2265 MVT::ValueType VT = Op.getValueType();
2267 MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
2269 SDOperand Op0 = Op.getOperand(0);
2272 case ISD::ZERO_EXTEND:
2273 case ISD::SIGN_EXTEND:
2274 case ISD::ANY_EXTEND: {
2275 MVT::ValueType Op0VT = Op0.getValueType();
2277 MVT::getVectorType(Op0VT, (128 / MVT::getSizeInBits(Op0VT)));
2279 assert(Op0VT == MVT::i32
2280 && "CellSPU: Zero/sign extending something other than i32");
2281 DEBUG(cerr << "CellSPU: LowerI64Math custom lowering zero/sign/any extend\n");
2283 unsigned NewOpc = (Opc == ISD::SIGN_EXTEND
2284 ? SPUISD::ROTBYTES_RIGHT_S
2285 : SPUISD::ROTQUAD_RZ_BYTES);
2286 SDOperand PromoteScalar =
2287 DAG.getNode(SPUISD::PROMOTE_SCALAR, Op0VecVT, Op0);
2289 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
2290 DAG.getNode(ISD::BIT_CONVERT, VecVT,
2291 DAG.getNode(NewOpc, Op0VecVT,
2293 DAG.getConstant(4, MVT::i32))));
2297 SDOperand ShiftAmt = Op.getOperand(1);
2298 unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
2299 SDOperand Op0Vec = DAG.getNode(SPUISD::PROMOTE_SCALAR, VecVT, Op0);
2300 SDOperand MaskLower =
2301 DAG.getNode(SPUISD::SELB, VecVT,
2303 DAG.getConstant(0, VecVT),
2304 DAG.getNode(SPUISD::FSMBI, VecVT,
2305 DAG.getConstant(0xff00ULL, MVT::i16)));
2306 SDOperand ShiftAmtBytes =
2307 DAG.getNode(ISD::SRL, ShiftAmtVT,
2309 DAG.getConstant(3, ShiftAmtVT));
2310 SDOperand ShiftAmtBits =
2311 DAG.getNode(ISD::AND, ShiftAmtVT,
2313 DAG.getConstant(7, ShiftAmtVT));
2315 return DAG.getNode(SPUISD::EXTRACT_ELT0, VT,
2316 DAG.getNode(SPUISD::SHLQUAD_L_BITS, VecVT,
2317 DAG.getNode(SPUISD::SHLQUAD_L_BYTES, VecVT,
2318 MaskLower, ShiftAmtBytes),
2323 unsigned VT = unsigned(Op.getValueType());
2324 SDOperand ShiftAmt = Op.getOperand(1);
2325 unsigned ShiftAmtVT = unsigned(ShiftAmt.getValueType());
2326 SDOperand ShiftAmtBytes =
2327 DAG.getNode(ISD::SRL, ShiftAmtVT,
2329 DAG.getConstant(3, ShiftAmtVT));
2330 SDOperand ShiftAmtBits =
2331 DAG.getNode(ISD::AND, ShiftAmtVT,
2333 DAG.getConstant(7, ShiftAmtVT));
2335 return DAG.getNode(SPUISD::ROTQUAD_RZ_BITS, VT,
2336 DAG.getNode(SPUISD::ROTQUAD_RZ_BYTES, VT,
2337 Op0, ShiftAmtBytes),
2345 //! Lower byte immediate operations for v16i8 vectors:
2347 LowerByteImmed(SDOperand Op, SelectionDAG &DAG) {
2350 MVT::ValueType VT = Op.getValueType();
2352 ConstVec = Op.getOperand(0);
2353 Arg = Op.getOperand(1);
2354 if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
2355 if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
2356 ConstVec = ConstVec.getOperand(0);
2358 ConstVec = Op.getOperand(1);
2359 Arg = Op.getOperand(0);
2360 if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
2361 ConstVec = ConstVec.getOperand(0);
2366 if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
2367 uint64_t VectorBits[2];
2368 uint64_t UndefBits[2];
2369 uint64_t SplatBits, SplatUndef;
2372 if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits, UndefBits)
2373 && isConstantSplat(VectorBits, UndefBits,
2374 MVT::getSizeInBits(MVT::getVectorElementType(VT)),
2375 SplatBits, SplatUndef, SplatSize)) {
2376 SDOperand tcVec[16];
2377 SDOperand tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
2378 const size_t tcVecSize = sizeof(tcVec) / sizeof(tcVec[0]);
2380 // Turn the BUILD_VECTOR into a set of target constants:
2381 for (size_t i = 0; i < tcVecSize; ++i)
2384 return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
2385 DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize));
2392 //! Lower i32 multiplication
2393 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG, unsigned VT,
2397 cerr << "CellSPU: Unknown LowerMUL value type, got "
2398 << MVT::getValueTypeString(Op.getValueType())
2404 SDOperand rA = Op.getOperand(0);
2405 SDOperand rB = Op.getOperand(1);
2407 return DAG.getNode(ISD::ADD, MVT::i32,
2408 DAG.getNode(ISD::ADD, MVT::i32,
2409 DAG.getNode(SPUISD::MPYH, MVT::i32, rA, rB),
2410 DAG.getNode(SPUISD::MPYH, MVT::i32, rB, rA)),
2411 DAG.getNode(SPUISD::MPYU, MVT::i32, rA, rB));
2418 //! Custom lowering for CTPOP (count population)
2420 Custom lowering code that counts the number ones in the input
2421 operand. SPU has such an instruction, but it counts the number of
2422 ones per byte, which then have to be accumulated.
2424 static SDOperand LowerCTPOP(SDOperand Op, SelectionDAG &DAG) {
2425 unsigned VT = Op.getValueType();
2426 unsigned vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
2430 SDOperand N = Op.getOperand(0);
2431 SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
2433 SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
2434 SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
2436 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i8, CNTB, Elt0);
2440 MachineFunction &MF = DAG.getMachineFunction();
2441 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2443 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
2445 SDOperand N = Op.getOperand(0);
2446 SDOperand Elt0 = DAG.getConstant(0, MVT::i16);
2447 SDOperand Mask0 = DAG.getConstant(0x0f, MVT::i16);
2448 SDOperand Shift1 = DAG.getConstant(8, MVT::i16);
2450 SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
2451 SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
2453 // CNTB_result becomes the chain to which all of the virtual registers
2454 // CNTB_reg, SUM1_reg become associated:
2455 SDOperand CNTB_result =
2456 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, CNTB, Elt0);
2458 SDOperand CNTB_rescopy =
2459 DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
2461 SDOperand Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i16);
2463 return DAG.getNode(ISD::AND, MVT::i16,
2464 DAG.getNode(ISD::ADD, MVT::i16,
2465 DAG.getNode(ISD::SRL, MVT::i16,
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2475 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2476 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2478 SDOperand N = Op.getOperand(0);
2479 SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
2480 SDOperand Mask0 = DAG.getConstant(0xff, MVT::i32);
2481 SDOperand Shift1 = DAG.getConstant(16, MVT::i32);
2482 SDOperand Shift2 = DAG.getConstant(8, MVT::i32);
2484 SDOperand Promote = DAG.getNode(SPUISD::PROMOTE_SCALAR, vecVT, N, N);
2485 SDOperand CNTB = DAG.getNode(SPUISD::CNTB, vecVT, Promote);
2487 // CNTB_result becomes the chain to which all of the virtual registers
2488 // CNTB_reg, SUM1_reg become associated:
2489 SDOperand CNTB_result =
2490 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, CNTB, Elt0);
2492 SDOperand CNTB_rescopy =
2493 DAG.getCopyToReg(CNTB_result, CNTB_reg, CNTB_result);
2496 DAG.getNode(ISD::SRL, MVT::i32,
2497 DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32), Shift1);
2500 DAG.getNode(ISD::ADD, MVT::i32,
2501 Comp1, DAG.getCopyFromReg(CNTB_rescopy, CNTB_reg, MVT::i32));
2503 SDOperand Sum1_rescopy =
2504 DAG.getCopyToReg(CNTB_result, SUM1_reg, Sum1);
2507 DAG.getNode(ISD::SRL, MVT::i32,
2508 DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32),
2511 DAG.getNode(ISD::ADD, MVT::i32, Comp2,
2512 DAG.getCopyFromReg(Sum1_rescopy, SUM1_reg, MVT::i32));
2514 return DAG.getNode(ISD::AND, MVT::i32, Sum2, Mask0);
2524 /// LowerOperation - Provide custom lowering hooks for some operations.
2527 SPUTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG)
2529 unsigned Opc = (unsigned) Op.getOpcode();
2530 unsigned VT = (unsigned) Op.getValueType();
2534 cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
2535 cerr << "Op.getOpcode() = " << Opc << "\n";
2536 cerr << "*Op.Val:\n";
2543 return LowerLOAD(Op, DAG, SPUTM.getSubtargetImpl());
2545 return LowerSTORE(Op, DAG, SPUTM.getSubtargetImpl());
2546 case ISD::ConstantPool:
2547 return LowerConstantPool(Op, DAG, SPUTM.getSubtargetImpl());
2548 case ISD::GlobalAddress:
2549 return LowerGlobalAddress(Op, DAG, SPUTM.getSubtargetImpl());
2550 case ISD::JumpTable:
2551 return LowerJumpTable(Op, DAG, SPUTM.getSubtargetImpl());
2553 return LowerConstant(Op, DAG);
2554 case ISD::ConstantFP:
2555 return LowerConstantFP(Op, DAG);
2557 return LowerBRCOND(Op, DAG);
2558 case ISD::FORMAL_ARGUMENTS:
2559 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2561 return LowerCALL(Op, DAG, SPUTM.getSubtargetImpl());
2563 return LowerRET(Op, DAG, getTargetMachine());
2566 // i8, i64 math ops:
2567 case ISD::ZERO_EXTEND:
2568 case ISD::SIGN_EXTEND:
2569 case ISD::ANY_EXTEND:
2577 return LowerI8Math(Op, DAG, Opc);
2578 else if (VT == MVT::i64)
2579 return LowerI64Math(Op, DAG, Opc);
2582 // Vector-related lowering.
2583 case ISD::BUILD_VECTOR:
2584 return LowerBUILD_VECTOR(Op, DAG);
2585 case ISD::SCALAR_TO_VECTOR:
2586 return LowerSCALAR_TO_VECTOR(Op, DAG);
2587 case ISD::VECTOR_SHUFFLE:
2588 return LowerVECTOR_SHUFFLE(Op, DAG);
2589 case ISD::EXTRACT_VECTOR_ELT:
2590 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2591 case ISD::INSERT_VECTOR_ELT:
2592 return LowerINSERT_VECTOR_ELT(Op, DAG);
2594 // Look for ANDBI, ORBI and XORBI opportunities and lower appropriately:
2598 return LowerByteImmed(Op, DAG);
2600 // Vector and i8 multiply:
2602 if (MVT::isVector(VT))
2603 return LowerVectorMUL(Op, DAG);
2604 else if (VT == MVT::i8)
2605 return LowerI8Math(Op, DAG, Opc);
2607 return LowerMUL(Op, DAG, VT, Opc);
2610 if (VT == MVT::f32 || VT == MVT::v4f32)
2611 return LowerFDIVf32(Op, DAG);
2612 // else if (Op.getValueType() == MVT::f64)
2613 // return LowerFDIVf64(Op, DAG);
2615 assert(0 && "Calling FDIV on unsupported MVT");
2618 return LowerCTPOP(Op, DAG);
2624 //===----------------------------------------------------------------------===//
2625 // Target Optimization Hooks
2626 //===----------------------------------------------------------------------===//
2629 SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
2632 TargetMachine &TM = getTargetMachine();
2634 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
2635 SelectionDAG &DAG = DCI.DAG;
2636 SDOperand Op0 = N->getOperand(0); // everything has at least one operand
2637 SDOperand Result; // Initially, NULL result
2639 switch (N->getOpcode()) {
2642 SDOperand Op1 = N->getOperand(1);
2644 if ((Op1.getOpcode() == ISD::Constant
2645 || Op1.getOpcode() == ISD::TargetConstant)
2646 && Op0.getOpcode() == SPUISD::IndirectAddr) {
2647 SDOperand Op01 = Op0.getOperand(1);
2648 if (Op01.getOpcode() == ISD::Constant
2649 || Op01.getOpcode() == ISD::TargetConstant) {
2650 // (add <const>, (SPUindirect <arg>, <const>)) ->
2651 // (SPUindirect <arg>, <const + const>)
2652 ConstantSDNode *CN0 = cast<ConstantSDNode>(Op1);
2653 ConstantSDNode *CN1 = cast<ConstantSDNode>(Op01);
2654 SDOperand combinedConst =
2655 DAG.getConstant(CN0->getValue() + CN1->getValue(),
2656 Op0.getValueType());
2658 DEBUG(cerr << "Replace: (add " << CN0->getValue() << ", "
2659 << "(SPUindirect <arg>, " << CN1->getValue() << "))\n");
2660 DEBUG(cerr << "With: (SPUindirect <arg>, "
2661 << CN0->getValue() + CN1->getValue() << ")\n");
2662 return DAG.getNode(SPUISD::IndirectAddr, Op0.getValueType(),
2663 Op0.getOperand(0), combinedConst);
2665 } else if ((Op0.getOpcode() == ISD::Constant
2666 || Op0.getOpcode() == ISD::TargetConstant)
2667 && Op1.getOpcode() == SPUISD::IndirectAddr) {
2668 SDOperand Op11 = Op1.getOperand(1);
2669 if (Op11.getOpcode() == ISD::Constant
2670 || Op11.getOpcode() == ISD::TargetConstant) {
2671 // (add (SPUindirect <arg>, <const>), <const>) ->
2672 // (SPUindirect <arg>, <const + const>)
2673 ConstantSDNode *CN0 = cast<ConstantSDNode>(Op0);
2674 ConstantSDNode *CN1 = cast<ConstantSDNode>(Op11);
2675 SDOperand combinedConst =
2676 DAG.getConstant(CN0->getValue() + CN1->getValue(),
2677 Op0.getValueType());
2679 DEBUG(cerr << "Replace: (add " << CN0->getValue() << ", "
2680 << "(SPUindirect <arg>, " << CN1->getValue() << "))\n");
2681 DEBUG(cerr << "With: (SPUindirect <arg>, "
2682 << CN0->getValue() + CN1->getValue() << ")\n");
2684 return DAG.getNode(SPUISD::IndirectAddr, Op1.getValueType(),
2685 Op1.getOperand(0), combinedConst);
2690 case ISD::SIGN_EXTEND:
2691 case ISD::ZERO_EXTEND:
2692 case ISD::ANY_EXTEND: {
2693 if (Op0.getOpcode() == SPUISD::EXTRACT_ELT0 &&
2694 N->getValueType(0) == Op0.getValueType()) {
2695 // (any_extend (SPUextract_elt0 <arg>)) ->
2696 // (SPUextract_elt0 <arg>)
2697 // Types must match, however...
2698 DEBUG(cerr << "Replace: ");
2699 DEBUG(N->dump(&DAG));
2700 DEBUG(cerr << "\nWith: ");
2701 DEBUG(Op0.Val->dump(&DAG));
2702 DEBUG(cerr << "\n");
2708 case SPUISD::IndirectAddr: {
2709 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
2710 ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(1));
2711 if (CN->getValue() == 0) {
2712 // (SPUindirect (SPUaform <addr>, 0), 0) ->
2713 // (SPUaform <addr>, 0)
2715 DEBUG(cerr << "Replace: ");
2716 DEBUG(N->dump(&DAG));
2717 DEBUG(cerr << "\nWith: ");
2718 DEBUG(Op0.Val->dump(&DAG));
2719 DEBUG(cerr << "\n");
2726 case SPUISD::SHLQUAD_L_BITS:
2727 case SPUISD::SHLQUAD_L_BYTES:
2728 case SPUISD::VEC_SHL:
2729 case SPUISD::VEC_SRL:
2730 case SPUISD::VEC_SRA:
2731 case SPUISD::ROTQUAD_RZ_BYTES:
2732 case SPUISD::ROTQUAD_RZ_BITS: {
2733 SDOperand Op1 = N->getOperand(1);
2735 if (isa<ConstantSDNode>(Op1)) {
2736 // Kill degenerate vector shifts:
2737 ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
2739 if (CN->getValue() == 0) {
2745 case SPUISD::PROMOTE_SCALAR: {
2746 switch (Op0.getOpcode()) {
2749 case ISD::ANY_EXTEND:
2750 case ISD::ZERO_EXTEND:
2751 case ISD::SIGN_EXTEND: {
2752 // (SPUpromote_scalar (any|sign|zero_extend (SPUextract_elt0 <arg>))) ->
2754 // but only if the SPUpromote_scalar and <arg> types match.
2755 SDOperand Op00 = Op0.getOperand(0);
2756 if (Op00.getOpcode() == SPUISD::EXTRACT_ELT0) {
2757 SDOperand Op000 = Op00.getOperand(0);
2758 if (Op000.getValueType() == N->getValueType(0)) {
2764 case SPUISD::EXTRACT_ELT0: {
2765 // (SPUpromote_scalar (SPUextract_elt0 <arg>)) ->
2767 Result = Op0.getOperand(0);
2774 // Otherwise, return unchanged.
2777 DEBUG(cerr << "\nReplace.SPU: ");
2778 DEBUG(N->dump(&DAG));
2779 DEBUG(cerr << "\nWith: ");
2780 DEBUG(Result.Val->dump(&DAG));
2781 DEBUG(cerr << "\n");
2788 //===----------------------------------------------------------------------===//
2789 // Inline Assembly Support
2790 //===----------------------------------------------------------------------===//
2792 /// getConstraintType - Given a constraint letter, return the type of
2793 /// constraint it is for this target.
2794 SPUTargetLowering::ConstraintType
2795 SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const {
2796 if (ConstraintLetter.size() == 1) {
2797 switch (ConstraintLetter[0]) {
2804 return C_RegisterClass;
2807 return TargetLowering::getConstraintType(ConstraintLetter);
2810 std::pair<unsigned, const TargetRegisterClass*>
2811 SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2812 MVT::ValueType VT) const
2814 if (Constraint.size() == 1) {
2815 // GCC RS6000 Constraint Letters
2816 switch (Constraint[0]) {
2820 return std::make_pair(0U, SPU::R64CRegisterClass);
2821 return std::make_pair(0U, SPU::R32CRegisterClass);
2824 return std::make_pair(0U, SPU::R32FPRegisterClass);
2825 else if (VT == MVT::f64)
2826 return std::make_pair(0U, SPU::R64FPRegisterClass);
2829 return std::make_pair(0U, SPU::GPRCRegisterClass);
2833 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2836 //! Compute used/known bits for a SPU operand
2838 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2842 const SelectionDAG &DAG,
2843 unsigned Depth ) const {
2845 const uint64_t uint64_sizebits = sizeof(uint64_t) * 8;
2848 switch (Op.getOpcode()) {
2850 // KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2860 case SPUISD::PROMOTE_SCALAR: {
2861 SDOperand Op0 = Op.getOperand(0);
2862 MVT::ValueType Op0VT = Op0.getValueType();
2863 unsigned Op0VTBits = MVT::getSizeInBits(Op0VT);
2864 uint64_t InMask = MVT::getIntVTBitMask(Op0VT);
2865 KnownZero |= APInt(Op0VTBits, ~InMask, false);
2866 KnownOne |= APInt(Op0VTBits, InMask, false);
2870 case SPUISD::LDRESULT:
2871 case SPUISD::EXTRACT_ELT0:
2872 case SPUISD::EXTRACT_ELT0_CHAINED: {
2873 MVT::ValueType OpVT = Op.getValueType();
2874 unsigned OpVTBits = MVT::getSizeInBits(OpVT);
2875 uint64_t InMask = MVT::getIntVTBitMask(OpVT);
2876 KnownZero |= APInt(OpVTBits, ~InMask, false);
2877 KnownOne |= APInt(OpVTBits, InMask, false);
2882 case EXTRACT_I1_ZEXT:
2883 case EXTRACT_I1_SEXT:
2884 case EXTRACT_I8_ZEXT:
2885 case EXTRACT_I8_SEXT:
2890 case SPUISD::SHLQUAD_L_BITS:
2891 case SPUISD::SHLQUAD_L_BYTES:
2892 case SPUISD::VEC_SHL:
2893 case SPUISD::VEC_SRL:
2894 case SPUISD::VEC_SRA:
2895 case SPUISD::VEC_ROTL:
2896 case SPUISD::VEC_ROTR:
2897 case SPUISD::ROTQUAD_RZ_BYTES:
2898 case SPUISD::ROTQUAD_RZ_BITS:
2899 case SPUISD::ROTBYTES_RIGHT_S:
2900 case SPUISD::ROTBYTES_LEFT:
2901 case SPUISD::ROTBYTES_LEFT_CHAINED:
2911 // LowerAsmOperandForConstraint
2913 SPUTargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
2914 char ConstraintLetter,
2915 std::vector<SDOperand> &Ops,
2916 SelectionDAG &DAG) const {
2917 // Default, for the time being, to the base class handler
2918 TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
2921 /// isLegalAddressImmediate - Return true if the integer value can be used
2922 /// as the offset of the target addressing mode.
2923 bool SPUTargetLowering::isLegalAddressImmediate(int64_t V, const Type *Ty) const {
2924 // SPU's addresses are 256K:
2925 return (V > -(1 << 18) && V < (1 << 18) - 1);
2928 bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {