2 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SPUTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUISelLowering.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUFrameInfo.h"
18 #include "SPUMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/VectorExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
40 // Used in getTargetNodeName() below
42 std::map<unsigned, const char *> node_names;
44 //! EVT mapping to useful data for Cell SPU
45 struct valtype_map_s {
50 const valtype_map_s valtype_map[] = {
61 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
63 const valtype_map_s *getValueTypeMapEntry(EVT VT) {
64 const valtype_map_s *retval = 0;
66 for (size_t i = 0; i < n_valtype_map; ++i) {
67 if (valtype_map[i].valtype == VT) {
68 retval = valtype_map + i;
75 report_fatal_error("getValueTypeMapEntry returns NULL for " +
76 Twine(VT.getEVTString()));
83 //! Expand a library call into an actual call DAG node
86 This code is taken from SelectionDAGLegalize, since it is not exposed as
87 part of the LLVM SelectionDAG API.
91 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
92 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
93 // The input chain to this libcall is the entry node of the function.
94 // Legalizing the call will automatically add the previous call to the
96 SDValue InChain = DAG.getEntryNode();
98 TargetLowering::ArgListTy Args;
99 TargetLowering::ArgListEntry Entry;
100 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
101 EVT ArgVT = Op.getOperand(i).getValueType();
102 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
103 Entry.Node = Op.getOperand(i);
105 Entry.isSExt = isSigned;
106 Entry.isZExt = !isSigned;
107 Args.push_back(Entry);
109 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
112 // Splice the libcall in wherever FindInputOutputChains tells us to.
114 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
115 std::pair<SDValue, SDValue> CallInfo =
116 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
117 0, TLI.getLibcallCallingConv(LC), false,
118 /*isReturnValueUsed=*/true,
119 Callee, Args, DAG, Op.getDebugLoc());
121 return CallInfo.first;
125 SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
126 : TargetLowering(TM, new TargetLoweringObjectFileELF()),
128 // Fold away setcc operations if possible.
131 // Use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(true);
133 setUseUnderscoreLongJmp(true);
135 // Set RTLIB libcall names as used by SPU:
136 setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
138 // Set up the SPU's register classes:
139 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
140 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
141 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
142 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
143 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
144 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
145 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
147 // SPU has no sign or zero extended loads for i1, i8, i16:
148 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
155 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
156 setTruncStoreAction(MVT::i128, MVT::i32, Expand);
157 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i128, MVT::i8, Expand);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 // SPU constant load actions are custom lowered:
163 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
164 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
166 // SPU's loads and stores have to be custom lowered:
167 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
169 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
171 setOperationAction(ISD::LOAD, VT, Custom);
172 setOperationAction(ISD::STORE, VT, Custom);
173 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
174 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
175 setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
177 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
178 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
179 setTruncStoreAction(VT, StoreVT, Expand);
183 for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
185 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
187 setOperationAction(ISD::LOAD, VT, Custom);
188 setOperationAction(ISD::STORE, VT, Custom);
190 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
191 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
192 setTruncStoreAction(VT, StoreVT, Expand);
196 // Expand the jumptable branches
197 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
198 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
200 // Custom lower SELECT_CC for most cases, but expand by default
201 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
202 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
203 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
204 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
205 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
207 // SPU has no intrinsics for these particular operations:
208 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
210 // SPU has no division/remainder instructions
211 setOperationAction(ISD::SREM, MVT::i8, Expand);
212 setOperationAction(ISD::UREM, MVT::i8, Expand);
213 setOperationAction(ISD::SDIV, MVT::i8, Expand);
214 setOperationAction(ISD::UDIV, MVT::i8, Expand);
215 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
216 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
217 setOperationAction(ISD::SREM, MVT::i16, Expand);
218 setOperationAction(ISD::UREM, MVT::i16, Expand);
219 setOperationAction(ISD::SDIV, MVT::i16, Expand);
220 setOperationAction(ISD::UDIV, MVT::i16, Expand);
221 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
222 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
223 setOperationAction(ISD::SREM, MVT::i32, Expand);
224 setOperationAction(ISD::UREM, MVT::i32, Expand);
225 setOperationAction(ISD::SDIV, MVT::i32, Expand);
226 setOperationAction(ISD::UDIV, MVT::i32, Expand);
227 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
228 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
229 setOperationAction(ISD::SREM, MVT::i64, Expand);
230 setOperationAction(ISD::UREM, MVT::i64, Expand);
231 setOperationAction(ISD::SDIV, MVT::i64, Expand);
232 setOperationAction(ISD::UDIV, MVT::i64, Expand);
233 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
234 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
235 setOperationAction(ISD::SREM, MVT::i128, Expand);
236 setOperationAction(ISD::UREM, MVT::i128, Expand);
237 setOperationAction(ISD::SDIV, MVT::i128, Expand);
238 setOperationAction(ISD::UDIV, MVT::i128, Expand);
239 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
240 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
242 // We don't support sin/cos/sqrt/fmod
243 setOperationAction(ISD::FSIN , MVT::f64, Expand);
244 setOperationAction(ISD::FCOS , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f64, Expand);
246 setOperationAction(ISD::FSIN , MVT::f32, Expand);
247 setOperationAction(ISD::FCOS , MVT::f32, Expand);
248 setOperationAction(ISD::FREM , MVT::f32, Expand);
250 // Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
252 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
253 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
258 // SPU can do rotate right and left, so legalize it... but customize for i8
259 // because instructions don't exist.
261 // FIXME: Change from "expand" to appropriate type once ROTR is supported in
263 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
264 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
265 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
267 setOperationAction(ISD::ROTL, MVT::i32, Legal);
268 setOperationAction(ISD::ROTL, MVT::i16, Legal);
269 setOperationAction(ISD::ROTL, MVT::i8, Custom);
271 // SPU has no native version of shift left/right for i8
272 setOperationAction(ISD::SHL, MVT::i8, Custom);
273 setOperationAction(ISD::SRL, MVT::i8, Custom);
274 setOperationAction(ISD::SRA, MVT::i8, Custom);
276 // Make these operations legal and handle them during instruction selection:
277 setOperationAction(ISD::SHL, MVT::i64, Legal);
278 setOperationAction(ISD::SRL, MVT::i64, Legal);
279 setOperationAction(ISD::SRA, MVT::i64, Legal);
281 // Custom lower i8, i32 and i64 multiplications
282 setOperationAction(ISD::MUL, MVT::i8, Custom);
283 setOperationAction(ISD::MUL, MVT::i32, Legal);
284 setOperationAction(ISD::MUL, MVT::i64, Legal);
286 // Expand double-width multiplication
287 // FIXME: It would probably be reasonable to support some of these operations
288 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
289 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
290 setOperationAction(ISD::MULHU, MVT::i8, Expand);
291 setOperationAction(ISD::MULHS, MVT::i8, Expand);
292 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
293 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
294 setOperationAction(ISD::MULHU, MVT::i16, Expand);
295 setOperationAction(ISD::MULHS, MVT::i16, Expand);
296 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
297 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
298 setOperationAction(ISD::MULHU, MVT::i32, Expand);
299 setOperationAction(ISD::MULHS, MVT::i32, Expand);
300 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
301 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
302 setOperationAction(ISD::MULHU, MVT::i64, Expand);
303 setOperationAction(ISD::MULHS, MVT::i64, Expand);
305 // Need to custom handle (some) common i8, i64 math ops
306 setOperationAction(ISD::ADD, MVT::i8, Custom);
307 setOperationAction(ISD::ADD, MVT::i64, Legal);
308 setOperationAction(ISD::SUB, MVT::i8, Custom);
309 setOperationAction(ISD::SUB, MVT::i64, Legal);
311 // SPU does not have BSWAP. It does have i32 support CTLZ.
312 // CTPOP has to be custom lowered.
313 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
314 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
316 setOperationAction(ISD::CTPOP, MVT::i8, Custom);
317 setOperationAction(ISD::CTPOP, MVT::i16, Custom);
318 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
319 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
320 setOperationAction(ISD::CTPOP, MVT::i128, Expand);
322 setOperationAction(ISD::CTTZ , MVT::i8, Expand);
323 setOperationAction(ISD::CTTZ , MVT::i16, Expand);
324 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
325 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
326 setOperationAction(ISD::CTTZ , MVT::i128, Expand);
328 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
329 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
330 setOperationAction(ISD::CTLZ , MVT::i32, Legal);
331 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
332 setOperationAction(ISD::CTLZ , MVT::i128, Expand);
334 // SPU has a version of select that implements (a&~c)|(b&c), just like
335 // select ought to work:
336 setOperationAction(ISD::SELECT, MVT::i8, Legal);
337 setOperationAction(ISD::SELECT, MVT::i16, Legal);
338 setOperationAction(ISD::SELECT, MVT::i32, Legal);
339 setOperationAction(ISD::SELECT, MVT::i64, Legal);
341 setOperationAction(ISD::SETCC, MVT::i8, Legal);
342 setOperationAction(ISD::SETCC, MVT::i16, Legal);
343 setOperationAction(ISD::SETCC, MVT::i32, Legal);
344 setOperationAction(ISD::SETCC, MVT::i64, Legal);
345 setOperationAction(ISD::SETCC, MVT::f64, Custom);
347 // Custom lower i128 -> i64 truncates
348 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
350 // Custom lower i32/i64 -> i128 sign extend
351 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
353 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
354 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
355 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
357 // SPU has a legal FP -> signed INT instruction for f32, but for f64, need
358 // to expand to a libcall, hence the custom lowering:
359 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
361 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
362 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
363 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
364 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
366 // FDIV on SPU requires custom lowering
367 setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
369 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
370 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
371 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
372 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
373 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
380 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
381 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
382 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
384 // We cannot sextinreg(i1). Expand to shifts.
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
387 // We want to legalize GlobalAddress and ConstantPool nodes into the
388 // appropriate instructions to materialize the address.
389 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
391 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
393 setOperationAction(ISD::GlobalAddress, VT, Custom);
394 setOperationAction(ISD::ConstantPool, VT, Custom);
395 setOperationAction(ISD::JumpTable, VT, Custom);
398 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
399 setOperationAction(ISD::VASTART , MVT::Other, Custom);
401 // Use the default implementation.
402 setOperationAction(ISD::VAARG , MVT::Other, Expand);
403 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
406 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
407 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
408 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
410 // Cell SPU has instructions for converting between i64 and fp.
411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
414 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
415 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
417 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
418 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
420 // First set operation action for all vector types to expand. Then we
421 // will selectively turn on ones that can be effectively codegen'd.
422 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
423 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
424 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
425 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
426 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
427 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
429 // "Odd size" vector classes that we're willing to support:
430 addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass);
432 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
433 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
434 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
436 // add/sub are legal for all supported vector VT's.
437 setOperationAction(ISD::ADD, VT, Legal);
438 setOperationAction(ISD::SUB, VT, Legal);
439 // mul has to be custom lowered.
440 setOperationAction(ISD::MUL, VT, Legal);
442 setOperationAction(ISD::AND, VT, Legal);
443 setOperationAction(ISD::OR, VT, Legal);
444 setOperationAction(ISD::XOR, VT, Legal);
445 setOperationAction(ISD::LOAD, VT, Legal);
446 setOperationAction(ISD::SELECT, VT, Legal);
447 setOperationAction(ISD::STORE, VT, Legal);
449 // These operations need to be expanded:
450 setOperationAction(ISD::SDIV, VT, Expand);
451 setOperationAction(ISD::SREM, VT, Expand);
452 setOperationAction(ISD::UDIV, VT, Expand);
453 setOperationAction(ISD::UREM, VT, Expand);
455 // Custom lower build_vector, constant pool spills, insert and
456 // extract vector elements:
457 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
458 setOperationAction(ISD::ConstantPool, VT, Custom);
459 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
462 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
465 setOperationAction(ISD::AND, MVT::v16i8, Custom);
466 setOperationAction(ISD::OR, MVT::v16i8, Custom);
467 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
468 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
470 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
472 setShiftAmountType(MVT::i32);
473 setBooleanContents(ZeroOrNegativeOneBooleanContent);
475 setStackPointerRegisterToSaveRestore(SPU::R1);
477 // We have target-specific dag combine patterns for the following nodes:
478 setTargetDAGCombine(ISD::ADD);
479 setTargetDAGCombine(ISD::ZERO_EXTEND);
480 setTargetDAGCombine(ISD::SIGN_EXTEND);
481 setTargetDAGCombine(ISD::ANY_EXTEND);
483 computeRegisterProperties();
485 // Set pre-RA register scheduler default to BURR, which produces slightly
486 // better code than the default (could also be TDRR, but TargetLowering.h
487 // needs a mod to support that model):
488 setSchedulingPreference(Sched::RegPressure);
492 SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
494 if (node_names.empty()) {
495 node_names[(unsigned) SPUISD::RET_FLAG] = "SPUISD::RET_FLAG";
496 node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi";
497 node_names[(unsigned) SPUISD::Lo] = "SPUISD::Lo";
498 node_names[(unsigned) SPUISD::PCRelAddr] = "SPUISD::PCRelAddr";
499 node_names[(unsigned) SPUISD::AFormAddr] = "SPUISD::AFormAddr";
500 node_names[(unsigned) SPUISD::IndirectAddr] = "SPUISD::IndirectAddr";
501 node_names[(unsigned) SPUISD::LDRESULT] = "SPUISD::LDRESULT";
502 node_names[(unsigned) SPUISD::CALL] = "SPUISD::CALL";
503 node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB";
504 node_names[(unsigned) SPUISD::SHUFFLE_MASK] = "SPUISD::SHUFFLE_MASK";
505 node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
506 node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC";
507 node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT";
508 node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS";
509 node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES";
510 node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL";
511 node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR";
512 node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
513 node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] =
514 "SPUISD::ROTBYTES_LEFT_BITS";
515 node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK";
516 node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB";
517 node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
518 node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
519 node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
522 std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
524 return ((i != node_names.end()) ? i->second : 0);
527 /// getFunctionAlignment - Return the Log2 alignment of this function.
528 unsigned SPUTargetLowering::getFunctionAlignment(const Function *) const {
532 //===----------------------------------------------------------------------===//
533 // Return the Cell SPU's SETCC result type
534 //===----------------------------------------------------------------------===//
536 MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
537 // i16 and i32 are valid SETCC result types
538 return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
539 VT.getSimpleVT().SimpleTy :
543 //===----------------------------------------------------------------------===//
544 // Calling convention code:
545 //===----------------------------------------------------------------------===//
547 #include "SPUGenCallingConv.inc"
549 //===----------------------------------------------------------------------===//
550 // LowerOperation implementation
551 //===----------------------------------------------------------------------===//
553 /// Custom lower loads for CellSPU
555 All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
556 within a 16-byte block, we have to rotate to extract the requested element.
558 For extending loads, we also want to ensure that the following sequence is
559 emitted, e.g. for MVT::f32 extending load to MVT::f64:
563 %2 v16i8,ch = rotate %1
564 %3 v4f8, ch = bitconvert %2
565 %4 f32 = vec2perfslot %3
566 %5 f64 = fp_extend %4
570 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
571 LoadSDNode *LN = cast<LoadSDNode>(Op);
572 SDValue the_chain = LN->getChain();
573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
574 EVT InVT = LN->getMemoryVT();
575 EVT OutVT = Op.getValueType();
576 ISD::LoadExtType ExtType = LN->getExtensionType();
577 unsigned alignment = LN->getAlignment();
578 const valtype_map_s *vtm = getValueTypeMapEntry(InVT);
579 DebugLoc dl = Op.getDebugLoc();
581 switch (LN->getAddressingMode()) {
582 case ISD::UNINDEXED: {
584 SDValue basePtr = LN->getBasePtr();
587 if (alignment == 16) {
590 // Special cases for a known aligned load to simplify the base pointer
591 // and the rotation amount:
592 if (basePtr.getOpcode() == ISD::ADD
593 && (CN = dyn_cast<ConstantSDNode > (basePtr.getOperand(1))) != 0) {
594 // Known offset into basePtr
595 int64_t offset = CN->getSExtValue();
596 int64_t rotamt = int64_t((offset & 0xf) - vtm->prefslot_byte);
601 rotate = DAG.getConstant(rotamt, MVT::i16);
603 // Simplify the base pointer for this case:
604 basePtr = basePtr.getOperand(0);
605 if ((offset & ~0xf) > 0) {
606 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
608 DAG.getConstant((offset & ~0xf), PtrVT));
610 } else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
611 || (basePtr.getOpcode() == SPUISD::IndirectAddr
612 && basePtr.getOperand(0).getOpcode() == SPUISD::Hi
613 && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
614 // Plain aligned a-form address: rotate into preferred slot
615 // Same for (SPUindirect (SPUhi ...), (SPUlo ...))
616 int64_t rotamt = -vtm->prefslot_byte;
619 rotate = DAG.getConstant(rotamt, MVT::i16);
621 // Offset the rotate amount by the basePtr and the preferred slot
623 int64_t rotamt = -vtm->prefslot_byte;
626 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
628 DAG.getConstant(rotamt, PtrVT));
631 // Unaligned load: must be more pessimistic about addressing modes:
632 if (basePtr.getOpcode() == ISD::ADD) {
633 MachineFunction &MF = DAG.getMachineFunction();
634 MachineRegisterInfo &RegInfo = MF.getRegInfo();
635 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
638 SDValue Op0 = basePtr.getOperand(0);
639 SDValue Op1 = basePtr.getOperand(1);
641 if (isa<ConstantSDNode>(Op1)) {
642 // Convert the (add <ptr>, <const>) to an indirect address contained
643 // in a register. Note that this is done because we need to avoid
644 // creating a 0(reg) d-form address due to the SPU's block loads.
645 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
646 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
647 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
649 // Convert the (add <arg1>, <arg2>) to an indirect address, which
650 // will likely be lowered as a reg(reg) x-form address.
651 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
654 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
656 DAG.getConstant(0, PtrVT));
659 // Offset the rotate amount by the basePtr and the preferred slot
661 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
663 DAG.getConstant(-vtm->prefslot_byte, PtrVT));
666 // Re-emit as a v16i8 vector load
667 result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
668 LN->getSrcValue(), LN->getSrcValueOffset(),
669 LN->isVolatile(), LN->isNonTemporal(), 16);
672 the_chain = result.getValue(1);
674 // Rotate into the preferred slot:
675 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
676 result.getValue(0), rotate);
678 // Convert the loaded v16i8 vector to the appropriate vector type
679 // specified by the operand:
680 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
681 InVT, (128 / InVT.getSizeInBits()));
682 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
683 DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
685 // Handle extending loads by extending the scalar result:
686 if (ExtType == ISD::SEXTLOAD) {
687 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result);
688 } else if (ExtType == ISD::ZEXTLOAD) {
689 result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result);
690 } else if (ExtType == ISD::EXTLOAD) {
691 unsigned NewOpc = ISD::ANY_EXTEND;
693 if (OutVT.isFloatingPoint())
694 NewOpc = ISD::FP_EXTEND;
696 result = DAG.getNode(NewOpc, dl, OutVT, result);
699 SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
700 SDValue retops[2] = {
705 result = DAG.getNode(SPUISD::LDRESULT, dl, retvts,
706 retops, sizeof(retops) / sizeof(retops[0]));
713 case ISD::LAST_INDEXED_MODE:
715 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
717 Twine((unsigned)LN->getAddressingMode()));
725 /// Custom lower stores for CellSPU
727 All CellSPU stores are aligned to 16-byte boundaries, so for elements
728 within a 16-byte block, we have to generate a shuffle to insert the
729 requested element into its place, then store the resulting block.
732 LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
733 StoreSDNode *SN = cast<StoreSDNode>(Op);
734 SDValue Value = SN->getValue();
735 EVT VT = Value.getValueType();
736 EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
737 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
738 DebugLoc dl = Op.getDebugLoc();
739 unsigned alignment = SN->getAlignment();
741 switch (SN->getAddressingMode()) {
742 case ISD::UNINDEXED: {
743 // The vector type we really want to load from the 16-byte chunk.
744 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
745 VT, (128 / VT.getSizeInBits()));
747 SDValue alignLoadVec;
748 SDValue basePtr = SN->getBasePtr();
749 SDValue the_chain = SN->getChain();
750 SDValue insertEltOffs;
752 if (alignment == 16) {
755 // Special cases for a known aligned load to simplify the base pointer
756 // and insertion byte:
757 if (basePtr.getOpcode() == ISD::ADD
758 && (CN = dyn_cast<ConstantSDNode>(basePtr.getOperand(1))) != 0) {
759 // Known offset into basePtr
760 int64_t offset = CN->getSExtValue();
762 // Simplify the base pointer for this case:
763 basePtr = basePtr.getOperand(0);
764 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
766 DAG.getConstant((offset & 0xf), PtrVT));
768 if ((offset & ~0xf) > 0) {
769 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
771 DAG.getConstant((offset & ~0xf), PtrVT));
774 // Otherwise, assume it's at byte 0 of basePtr
775 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
777 DAG.getConstant(0, PtrVT));
780 // Unaligned load: must be more pessimistic about addressing modes:
781 if (basePtr.getOpcode() == ISD::ADD) {
782 MachineFunction &MF = DAG.getMachineFunction();
783 MachineRegisterInfo &RegInfo = MF.getRegInfo();
784 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
787 SDValue Op0 = basePtr.getOperand(0);
788 SDValue Op1 = basePtr.getOperand(1);
790 if (isa<ConstantSDNode>(Op1)) {
791 // Convert the (add <ptr>, <const>) to an indirect address contained
792 // in a register. Note that this is done because we need to avoid
793 // creating a 0(reg) d-form address due to the SPU's block loads.
794 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
795 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
796 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
798 // Convert the (add <arg1>, <arg2>) to an indirect address, which
799 // will likely be lowered as a reg(reg) x-form address.
800 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
803 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
805 DAG.getConstant(0, PtrVT));
808 // Insertion point is solely determined by basePtr's contents
809 insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
811 DAG.getConstant(0, PtrVT));
814 // Re-emit as a v16i8 vector load
815 alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
816 SN->getSrcValue(), SN->getSrcValueOffset(),
817 SN->isVolatile(), SN->isNonTemporal(), 16);
820 the_chain = alignLoadVec.getValue(1);
822 LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
823 SDValue theValue = SN->getValue();
827 && (theValue.getOpcode() == ISD::AssertZext
828 || theValue.getOpcode() == ISD::AssertSext)) {
829 // Drill down and get the value for zero- and sign-extended
831 theValue = theValue.getOperand(0);
834 // If the base pointer is already a D-form address, then just create
835 // a new D-form address with a slot offset and the orignal base pointer.
836 // Otherwise generate a D-form address with the slot offset relative
837 // to the stack pointer, which is always aligned.
839 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
840 errs() << "CellSPU LowerSTORE: basePtr = ";
841 basePtr.getNode()->dump(&DAG);
846 SDValue insertEltOp =
847 DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT, insertEltOffs);
848 SDValue vectorizeOp =
849 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT, theValue);
851 result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
852 vectorizeOp, alignLoadVec,
853 DAG.getNode(ISD::BIT_CONVERT, dl,
854 MVT::v4i32, insertEltOp));
856 result = DAG.getStore(the_chain, dl, result, basePtr,
857 LN->getSrcValue(), LN->getSrcValueOffset(),
858 LN->isVolatile(), LN->isNonTemporal(),
861 #if 0 && !defined(NDEBUG)
862 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
863 const SDValue ¤tRoot = DAG.getRoot();
866 errs() << "------- CellSPU:LowerStore result:\n";
868 errs() << "-------\n";
869 DAG.setRoot(currentRoot);
880 case ISD::LAST_INDEXED_MODE:
882 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
884 Twine((unsigned)SN->getAddressingMode()));
892 //! Generate the address of a constant pool entry.
894 LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
895 EVT PtrVT = Op.getValueType();
896 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
897 const Constant *C = CP->getConstVal();
898 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
899 SDValue Zero = DAG.getConstant(0, PtrVT);
900 const TargetMachine &TM = DAG.getTarget();
901 // FIXME there is no actual debug info here
902 DebugLoc dl = Op.getDebugLoc();
904 if (TM.getRelocationModel() == Reloc::Static) {
905 if (!ST->usingLargeMem()) {
906 // Just return the SDValue with the constant pool address in it.
907 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero);
909 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero);
910 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero);
911 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
915 llvm_unreachable("LowerConstantPool: Relocation model other than static"
920 //! Alternate entry point for generating the address of a constant pool entry
922 SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) {
923 return ::LowerConstantPool(Op, DAG, TM.getSubtargetImpl());
927 LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
928 EVT PtrVT = Op.getValueType();
929 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
930 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
931 SDValue Zero = DAG.getConstant(0, PtrVT);
932 const TargetMachine &TM = DAG.getTarget();
933 // FIXME there is no actual debug info here
934 DebugLoc dl = Op.getDebugLoc();
936 if (TM.getRelocationModel() == Reloc::Static) {
937 if (!ST->usingLargeMem()) {
938 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero);
940 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero);
941 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero);
942 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
946 llvm_unreachable("LowerJumpTable: Relocation model other than static"
952 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
953 EVT PtrVT = Op.getValueType();
954 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
955 const GlobalValue *GV = GSDN->getGlobal();
956 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
957 PtrVT, GSDN->getOffset());
958 const TargetMachine &TM = DAG.getTarget();
959 SDValue Zero = DAG.getConstant(0, PtrVT);
960 // FIXME there is no actual debug info here
961 DebugLoc dl = Op.getDebugLoc();
963 if (TM.getRelocationModel() == Reloc::Static) {
964 if (!ST->usingLargeMem()) {
965 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero);
967 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero);
968 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero);
969 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
972 report_fatal_error("LowerGlobalAddress: Relocation model other than static"
980 //! Custom lower double precision floating point constants
982 LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
983 EVT VT = Op.getValueType();
984 // FIXME there is no actual debug info here
985 DebugLoc dl = Op.getDebugLoc();
987 if (VT == MVT::f64) {
988 ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
991 "LowerConstantFP: Node is not ConstantFPSDNode");
993 uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
994 SDValue T = DAG.getConstant(dbits, MVT::i64);
995 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
996 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
997 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
1004 SPUTargetLowering::LowerFormalArguments(SDValue Chain,
1005 CallingConv::ID CallConv, bool isVarArg,
1006 const SmallVectorImpl<ISD::InputArg>
1008 DebugLoc dl, SelectionDAG &DAG,
1009 SmallVectorImpl<SDValue> &InVals)
1012 MachineFunction &MF = DAG.getMachineFunction();
1013 MachineFrameInfo *MFI = MF.getFrameInfo();
1014 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1015 SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>();
1017 unsigned ArgOffset = SPUFrameInfo::minStackSize();
1018 unsigned ArgRegIdx = 0;
1019 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1021 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1023 SmallVector<CCValAssign, 16> ArgLocs;
1024 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1026 // FIXME: allow for other calling conventions
1027 CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
1029 // Add DAG nodes to load the arguments or copy them out of registers.
1030 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1031 EVT ObjectVT = Ins[ArgNo].VT;
1032 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1034 CCValAssign &VA = ArgLocs[ArgNo];
1036 if (VA.isRegLoc()) {
1037 const TargetRegisterClass *ArgRegClass;
1039 switch (ObjectVT.getSimpleVT().SimpleTy) {
1041 report_fatal_error("LowerFormalArguments Unhandled argument type: " +
1042 Twine(ObjectVT.getEVTString()));
1044 ArgRegClass = &SPU::R8CRegClass;
1047 ArgRegClass = &SPU::R16CRegClass;
1050 ArgRegClass = &SPU::R32CRegClass;
1053 ArgRegClass = &SPU::R64CRegClass;
1056 ArgRegClass = &SPU::GPRCRegClass;
1059 ArgRegClass = &SPU::R32FPRegClass;
1062 ArgRegClass = &SPU::R64FPRegClass;
1071 ArgRegClass = &SPU::VECREGRegClass;
1075 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
1076 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1077 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1080 // We need to load the argument to a virtual register if we determined
1081 // above that we ran out of physical registers of the appropriate type
1082 // or we're forced to do vararg
1083 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
1084 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1085 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
1086 ArgOffset += StackSlotSize;
1089 InVals.push_back(ArgVal);
1091 Chain = ArgVal.getOperand(0);
1096 // FIXME: we should be able to query the argument registers from
1097 // tablegen generated code.
1098 static const unsigned ArgRegs[] = {
1099 SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
1100 SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
1101 SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
1102 SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
1103 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
1104 SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
1105 SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
1106 SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
1107 SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
1108 SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
1109 SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
1111 // size of ArgRegs array
1112 unsigned NumArgRegs = 77;
1114 // We will spill (79-3)+1 registers to the stack
1115 SmallVector<SDValue, 79-3+1> MemOps;
1117 // Create the frame slot
1118 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
1119 FuncInfo->setVarArgsFrameIndex(
1120 MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
1121 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1122 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
1123 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1124 SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0,
1126 Chain = Store.getOperand(0);
1127 MemOps.push_back(Store);
1129 // Increment address by stack slot size for the next stored argument
1130 ArgOffset += StackSlotSize;
1132 if (!MemOps.empty())
1133 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1134 &MemOps[0], MemOps.size());
1140 /// isLSAAddress - Return the immediate to use if the specified
1141 /// value is representable as a LSA address.
1142 static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
1143 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1146 int Addr = C->getZExtValue();
1147 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1148 (Addr << 14 >> 14) != Addr)
1149 return 0; // Top 14 bits have to be sext of immediate.
1151 return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
1155 SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1156 CallingConv::ID CallConv, bool isVarArg,
1158 const SmallVectorImpl<ISD::OutputArg> &Outs,
1159 const SmallVectorImpl<SDValue> &OutVals,
1160 const SmallVectorImpl<ISD::InputArg> &Ins,
1161 DebugLoc dl, SelectionDAG &DAG,
1162 SmallVectorImpl<SDValue> &InVals) const {
1163 // CellSPU target does not yet support tail call optimization.
1166 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
1167 unsigned NumOps = Outs.size();
1168 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1170 SmallVector<CCValAssign, 16> ArgLocs;
1171 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1173 // FIXME: allow for other calling conventions
1174 CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
1176 const unsigned NumArgRegs = ArgLocs.size();
1179 // Handy pointer type
1180 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1182 // Set up a copy of the stack pointer for use loading and storing any
1183 // arguments that may not fit in the registers available for argument
1185 SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1187 // Figure out which arguments are going to go in registers, and which in
1189 unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
1190 unsigned ArgRegIdx = 0;
1192 // Keep track of registers passing arguments
1193 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
1194 // And the arguments passed on the stack
1195 SmallVector<SDValue, 8> MemOpChains;
1197 for (; ArgRegIdx != NumOps; ++ArgRegIdx) {
1198 SDValue Arg = OutVals[ArgRegIdx];
1199 CCValAssign &VA = ArgLocs[ArgRegIdx];
1201 // PtrOff will be used to store the current argument to the stack if a
1202 // register cannot be found for it.
1203 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1204 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
1206 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
1207 default: llvm_unreachable("Unexpected ValueType for argument!");
1221 if (ArgRegIdx != NumArgRegs) {
1222 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1224 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
1226 ArgOffset += StackSlotSize;
1232 // Accumulate how many bytes are to be pushed on the stack, including the
1233 // linkage area, and parameter passing area. According to the SPU ABI,
1234 // we minimally need space for [LR] and [SP].
1235 unsigned NumStackBytes = ArgOffset - SPUFrameInfo::minStackSize();
1237 // Insert a call sequence start
1238 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes,
1241 if (!MemOpChains.empty()) {
1242 // Adjust the stack pointer for the stack arguments.
1243 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1244 &MemOpChains[0], MemOpChains.size());
1247 // Build a sequence of copy-to-reg nodes chained together with token chain
1248 // and flag operands which copy the outgoing args into the appropriate regs.
1250 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1251 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1252 RegsToPass[i].second, InFlag);
1253 InFlag = Chain.getValue(1);
1256 SmallVector<SDValue, 8> Ops;
1257 unsigned CallOpc = SPUISD::CALL;
1259 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1260 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1261 // node so that legalize doesn't hack it.
1262 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1263 const GlobalValue *GV = G->getGlobal();
1264 EVT CalleeVT = Callee.getValueType();
1265 SDValue Zero = DAG.getConstant(0, PtrVT);
1266 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, CalleeVT);
1268 if (!ST->usingLargeMem()) {
1269 // Turn calls to targets that are defined (i.e., have bodies) into BRSL
1270 // style calls, otherwise, external symbols are BRASL calls. This assumes
1271 // that declared/defined symbols are in the same compilation unit and can
1272 // be reached through PC-relative jumps.
1275 // This may be an unsafe assumption for JIT and really large compilation
1277 if (GV->isDeclaration()) {
1278 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero);
1280 Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero);
1283 // "Large memory" mode: Turn all calls into indirect calls with a X-form
1285 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero);
1287 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1288 EVT CalleeVT = Callee.getValueType();
1289 SDValue Zero = DAG.getConstant(0, PtrVT);
1290 SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(),
1291 Callee.getValueType());
1293 if (!ST->usingLargeMem()) {
1294 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero);
1296 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero);
1298 } else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
1299 // If this is an absolute destination address that appears to be a legal
1300 // local store address, use the munged value.
1301 Callee = SDValue(Dest, 0);
1304 Ops.push_back(Chain);
1305 Ops.push_back(Callee);
1307 // Add argument registers to the end of the list so that they are known live
1309 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1310 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1311 RegsToPass[i].second.getValueType()));
1313 if (InFlag.getNode())
1314 Ops.push_back(InFlag);
1315 // Returns a chain and a flag for retval copy to use.
1316 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1317 &Ops[0], Ops.size());
1318 InFlag = Chain.getValue(1);
1320 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumStackBytes, true),
1321 DAG.getIntPtrConstant(0, true), InFlag);
1323 InFlag = Chain.getValue(1);
1325 // If the function returns void, just return the chain.
1329 // If the call has results, copy the values out of the ret val registers.
1330 switch (Ins[0].VT.getSimpleVT().SimpleTy) {
1331 default: llvm_unreachable("Unexpected ret value!");
1332 case MVT::Other: break;
1334 if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
1335 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
1336 MVT::i32, InFlag).getValue(1);
1337 InVals.push_back(Chain.getValue(0));
1338 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
1339 Chain.getValue(2)).getValue(1);
1340 InVals.push_back(Chain.getValue(0));
1342 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
1343 InFlag).getValue(1);
1344 InVals.push_back(Chain.getValue(0));
1359 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
1360 InFlag).getValue(1);
1361 InVals.push_back(Chain.getValue(0));
1369 SPUTargetLowering::LowerReturn(SDValue Chain,
1370 CallingConv::ID CallConv, bool isVarArg,
1371 const SmallVectorImpl<ISD::OutputArg> &Outs,
1372 const SmallVectorImpl<SDValue> &OutVals,
1373 DebugLoc dl, SelectionDAG &DAG) const {
1375 SmallVector<CCValAssign, 16> RVLocs;
1376 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1377 RVLocs, *DAG.getContext());
1378 CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
1380 // If this is the first return lowered for this function, add the regs to the
1381 // liveout set for the function.
1382 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1383 for (unsigned i = 0; i != RVLocs.size(); ++i)
1384 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1389 // Copy the result values into the output registers.
1390 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1391 CCValAssign &VA = RVLocs[i];
1392 assert(VA.isRegLoc() && "Can only return in registers!");
1393 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1395 Flag = Chain.getValue(1);
1399 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1401 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
1405 //===----------------------------------------------------------------------===//
1406 // Vector related lowering:
1407 //===----------------------------------------------------------------------===//
1409 static ConstantSDNode *
1410 getVecImm(SDNode *N) {
1411 SDValue OpVal(0, 0);
1413 // Check to see if this buildvec has a single non-undef value in its elements.
1414 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1415 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1416 if (OpVal.getNode() == 0)
1417 OpVal = N->getOperand(i);
1418 else if (OpVal != N->getOperand(i))
1422 if (OpVal.getNode() != 0) {
1423 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1431 /// get_vec_i18imm - Test if this vector is a vector filled with the same value
1432 /// and the value fits into an unsigned 18-bit constant, and if so, return the
1434 SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
1436 if (ConstantSDNode *CN = getVecImm(N)) {
1437 uint64_t Value = CN->getZExtValue();
1438 if (ValueType == MVT::i64) {
1439 uint64_t UValue = CN->getZExtValue();
1440 uint32_t upper = uint32_t(UValue >> 32);
1441 uint32_t lower = uint32_t(UValue);
1444 Value = Value >> 32;
1446 if (Value <= 0x3ffff)
1447 return DAG.getTargetConstant(Value, ValueType);
1453 /// get_vec_i16imm - Test if this vector is a vector filled with the same value
1454 /// and the value fits into a signed 16-bit constant, and if so, return the
1456 SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
1458 if (ConstantSDNode *CN = getVecImm(N)) {
1459 int64_t Value = CN->getSExtValue();
1460 if (ValueType == MVT::i64) {
1461 uint64_t UValue = CN->getZExtValue();
1462 uint32_t upper = uint32_t(UValue >> 32);
1463 uint32_t lower = uint32_t(UValue);
1466 Value = Value >> 32;
1468 if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
1469 return DAG.getTargetConstant(Value, ValueType);
1476 /// get_vec_i10imm - Test if this vector is a vector filled with the same value
1477 /// and the value fits into a signed 10-bit constant, and if so, return the
1479 SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
1481 if (ConstantSDNode *CN = getVecImm(N)) {
1482 int64_t Value = CN->getSExtValue();
1483 if (ValueType == MVT::i64) {
1484 uint64_t UValue = CN->getZExtValue();
1485 uint32_t upper = uint32_t(UValue >> 32);
1486 uint32_t lower = uint32_t(UValue);
1489 Value = Value >> 32;
1491 if (isInt<10>(Value))
1492 return DAG.getTargetConstant(Value, ValueType);
1498 /// get_vec_i8imm - Test if this vector is a vector filled with the same value
1499 /// and the value fits into a signed 8-bit constant, and if so, return the
1502 /// @note: The incoming vector is v16i8 because that's the only way we can load
1503 /// constant vectors. Thus, we test to see if the upper and lower bytes are the
1505 SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
1507 if (ConstantSDNode *CN = getVecImm(N)) {
1508 int Value = (int) CN->getZExtValue();
1509 if (ValueType == MVT::i16
1510 && Value <= 0xffff /* truncated from uint64_t */
1511 && ((short) Value >> 8) == ((short) Value & 0xff))
1512 return DAG.getTargetConstant(Value & 0xff, ValueType);
1513 else if (ValueType == MVT::i8
1514 && (Value & 0xff) == Value)
1515 return DAG.getTargetConstant(Value, ValueType);
1521 /// get_ILHUvec_imm - Test if this vector is a vector filled with the same value
1522 /// and the value fits into a signed 16-bit constant, and if so, return the
1524 SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
1526 if (ConstantSDNode *CN = getVecImm(N)) {
1527 uint64_t Value = CN->getZExtValue();
1528 if ((ValueType == MVT::i32
1529 && ((unsigned) Value & 0xffff0000) == (unsigned) Value)
1530 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1531 return DAG.getTargetConstant(Value >> 16, ValueType);
1537 /// get_v4i32_imm - Catch-all for general 32-bit constant vectors
1538 SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
1539 if (ConstantSDNode *CN = getVecImm(N)) {
1540 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
1546 /// get_v4i32_imm - Catch-all for general 64-bit constant vectors
1547 SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
1548 if (ConstantSDNode *CN = getVecImm(N)) {
1549 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1555 //! Lower a BUILD_VECTOR instruction creatively:
1557 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
1558 EVT VT = Op.getValueType();
1559 EVT EltVT = VT.getVectorElementType();
1560 DebugLoc dl = Op.getDebugLoc();
1561 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(Op.getNode());
1562 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR");
1563 unsigned minSplatBits = EltVT.getSizeInBits();
1565 if (minSplatBits < 16)
1568 APInt APSplatBits, APSplatUndef;
1569 unsigned SplatBitSize;
1572 if (!BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1573 HasAnyUndefs, minSplatBits)
1574 || minSplatBits < SplatBitSize)
1575 return SDValue(); // Wasn't a constant vector or splat exceeded min
1577 uint64_t SplatBits = APSplatBits.getZExtValue();
1579 switch (VT.getSimpleVT().SimpleTy) {
1581 report_fatal_error("CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " +
1582 Twine(VT.getEVTString()));
1585 uint32_t Value32 = uint32_t(SplatBits);
1586 assert(SplatBitSize == 32
1587 && "LowerBUILD_VECTOR: Unexpected floating point vector element.");
1588 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1589 SDValue T = DAG.getConstant(Value32, MVT::i32);
1590 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
1591 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
1595 uint64_t f64val = uint64_t(SplatBits);
1596 assert(SplatBitSize == 64
1597 && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
1598 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1599 SDValue T = DAG.getConstant(f64val, MVT::i64);
1600 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
1601 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1605 // 8-bit constants have to be expanded to 16-bits
1606 unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
1607 SmallVector<SDValue, 8> Ops;
1609 Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
1610 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
1611 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
1614 unsigned short Value16 = SplatBits;
1615 SDValue T = DAG.getConstant(Value16, EltVT);
1616 SmallVector<SDValue, 8> Ops;
1619 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1622 SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
1623 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
1629 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
1639 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
1641 uint32_t upper = uint32_t(SplatVal >> 32);
1642 uint32_t lower = uint32_t(SplatVal);
1644 if (upper == lower) {
1645 // Magic constant that can be matched by IL, ILA, et. al.
1646 SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
1647 return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1648 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1649 Val, Val, Val, Val));
1651 bool upper_special, lower_special;
1653 // NOTE: This code creates common-case shuffle masks that can be easily
1654 // detected as common expressions. It is not attempting to create highly
1655 // specialized masks to replace any and all 0's, 0xff's and 0x80's.
1657 // Detect if the upper or lower half is a special shuffle mask pattern:
1658 upper_special = (upper == 0 || upper == 0xffffffff || upper == 0x80000000);
1659 lower_special = (lower == 0 || lower == 0xffffffff || lower == 0x80000000);
1661 // Both upper and lower are special, lower to a constant pool load:
1662 if (lower_special && upper_special) {
1663 SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
1664 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
1665 SplatValCN, SplatValCN);
1670 SmallVector<SDValue, 16> ShufBytes;
1673 // Create lower vector if not a special pattern
1674 if (!lower_special) {
1675 SDValue LO32C = DAG.getConstant(lower, MVT::i32);
1676 LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1677 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1678 LO32C, LO32C, LO32C, LO32C));
1681 // Create upper vector if not a special pattern
1682 if (!upper_special) {
1683 SDValue HI32C = DAG.getConstant(upper, MVT::i32);
1684 HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1685 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1686 HI32C, HI32C, HI32C, HI32C));
1689 // If either upper or lower are special, then the two input operands are
1690 // the same (basically, one of them is a "don't care")
1696 for (int i = 0; i < 4; ++i) {
1698 for (int j = 0; j < 4; ++j) {
1700 bool process_upper, process_lower;
1702 process_upper = (upper_special && (i & 1) == 0);
1703 process_lower = (lower_special && (i & 1) == 1);
1705 if (process_upper || process_lower) {
1706 if ((process_upper && upper == 0)
1707 || (process_lower && lower == 0))
1709 else if ((process_upper && upper == 0xffffffff)
1710 || (process_lower && lower == 0xffffffff))
1712 else if ((process_upper && upper == 0x80000000)
1713 || (process_lower && lower == 0x80000000))
1714 val |= (j == 0 ? 0xe0 : 0x80);
1716 val |= i * 4 + j + ((i & 1) * 16);
1719 ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
1722 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
1723 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1724 &ShufBytes[0], ShufBytes.size()));
1728 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1729 /// which the Cell can operate. The code inspects V3 to ascertain whether the
1730 /// permutation vector, V3, is monotonically increasing with one "exception"
1731 /// element, e.g., (0, 1, _, 3). If this is the case, then generate a
1732 /// SHUFFLE_MASK synthetic instruction. Otherwise, spill V3 to the constant pool.
1733 /// In either case, the net result is going to eventually invoke SHUFB to
1734 /// permute/shuffle the bytes from V1 and V2.
1736 /// SHUFFLE_MASK is eventually selected as one of the C*D instructions, generate
1737 /// control word for byte/halfword/word insertion. This takes care of a single
1738 /// element move from V2 into V1.
1740 /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
1741 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1742 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1743 SDValue V1 = Op.getOperand(0);
1744 SDValue V2 = Op.getOperand(1);
1745 DebugLoc dl = Op.getDebugLoc();
1747 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1749 // If we have a single element being moved from V1 to V2, this can be handled
1750 // using the C*[DX] compute mask instructions, but the vector elements have
1751 // to be monotonically increasing with one exception element.
1752 EVT VecVT = V1.getValueType();
1753 EVT EltVT = VecVT.getVectorElementType();
1754 unsigned EltsFromV2 = 0;
1756 unsigned V2EltIdx0 = 0;
1757 unsigned CurrElt = 0;
1758 unsigned MaxElts = VecVT.getVectorNumElements();
1759 unsigned PrevElt = 0;
1761 bool monotonic = true;
1763 EVT maskVT; // which of the c?d instructions to use
1765 if (EltVT == MVT::i8) {
1767 maskVT = MVT::v16i8;
1768 } else if (EltVT == MVT::i16) {
1770 maskVT = MVT::v8i16;
1771 } else if (VecVT == MVT::v2i32 || VecVT == MVT::v2f32 ) {
1773 maskVT = MVT::v4i32;
1774 } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
1776 maskVT = MVT::v4i32;
1777 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1779 maskVT = MVT::v2i64;
1781 llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
1783 for (unsigned i = 0; i != MaxElts; ++i) {
1784 if (SVN->getMaskElt(i) < 0)
1787 unsigned SrcElt = SVN->getMaskElt(i);
1790 if (SrcElt >= V2EltIdx0) {
1791 if (1 >= (++EltsFromV2)) {
1792 V2Elt = (V2EltIdx0 - SrcElt) << 2;
1794 } else if (CurrElt != SrcElt) {
1802 if (PrevElt > 0 && SrcElt < MaxElts) {
1803 if ((PrevElt == SrcElt - 1)
1804 || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
1811 } else if (i == 0) {
1812 // First time through, need to keep track of previous element
1815 // This isn't a rotation, takes elements from vector 2
1821 if (EltsFromV2 == 1 && monotonic) {
1822 // Compute mask and shuffle
1823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1825 // As SHUFFLE_MASK becomes a c?d instruction, feed it an address
1826 // R1 ($sp) is used here only as it is guaranteed to have last bits zero
1827 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
1828 DAG.getRegister(SPU::R1, PtrVT),
1829 DAG.getConstant(V2Elt, MVT::i32));
1830 SDValue ShufMaskOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl,
1833 // Use shuffle mask in SHUFB synthetic instruction:
1834 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
1836 } else if (rotate) {
1837 int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
1839 return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
1840 V1, DAG.getConstant(rotamt, MVT::i16));
1842 // Convert the SHUFFLE_VECTOR mask's input element units to the
1844 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
1846 SmallVector<SDValue, 16> ResultMask;
1847 for (unsigned i = 0, e = MaxElts; i != e; ++i) {
1848 unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
1850 for (unsigned j = 0; j < BytesPerElement; ++j)
1851 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
1853 // For half vectors padd the mask with zeros for the second half.
1854 // This is needed because mask is assumed to be full vector elsewhere in
1856 if(VecVT == MVT::v2i32 || VecVT == MVT::v2f32)
1857 for( unsigned i = 0; i < 2; ++i )
1859 for (unsigned j = 0; j < BytesPerElement; ++j)
1860 ResultMask.push_back(DAG.getConstant(0,MVT::i8));
1863 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
1864 &ResultMask[0], ResultMask.size());
1865 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
1869 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
1870 SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
1871 DebugLoc dl = Op.getDebugLoc();
1873 if (Op0.getNode()->getOpcode() == ISD::Constant) {
1874 // For a constant, build the appropriate constant vector, which will
1875 // eventually simplify to a vector register load.
1877 ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
1878 SmallVector<SDValue, 16> ConstVecValues;
1882 // Create a constant vector:
1883 switch (Op.getValueType().getSimpleVT().SimpleTy) {
1884 default: llvm_unreachable("Unexpected constant value type in "
1885 "LowerSCALAR_TO_VECTOR");
1886 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1887 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1888 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1889 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1890 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1891 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1892 case MVT::v2i32: n_copies = 2; VT = MVT::i32; break;
1895 SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
1896 for (size_t j = 0; j < n_copies; ++j)
1897 ConstVecValues.push_back(CValue);
1899 return DAG.getNode(ISD::BUILD_VECTOR, dl, Op.getValueType(),
1900 &ConstVecValues[0], ConstVecValues.size());
1902 // Otherwise, copy the value from one register to another:
1903 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
1904 default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
1911 return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
1918 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
1919 EVT VT = Op.getValueType();
1920 SDValue N = Op.getOperand(0);
1921 SDValue Elt = Op.getOperand(1);
1922 DebugLoc dl = Op.getDebugLoc();
1925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1926 // Constant argument:
1927 int EltNo = (int) C->getZExtValue();
1930 if (VT == MVT::i8 && EltNo >= 16)
1931 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
1932 else if (VT == MVT::i16 && EltNo >= 8)
1933 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
1934 else if (VT == MVT::i32 && EltNo >= 4)
1935 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
1936 else if (VT == MVT::i64 && EltNo >= 2)
1937 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
1939 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
1940 // i32 and i64: Element 0 is the preferred slot
1941 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
1944 // Need to generate shuffle mask and extract:
1945 int prefslot_begin = -1, prefslot_end = -1;
1946 int elt_byte = EltNo * VT.getSizeInBits() / 8;
1948 switch (VT.getSimpleVT().SimpleTy) {
1950 assert(false && "Invalid value type!");
1952 prefslot_begin = prefslot_end = 3;
1956 prefslot_begin = 2; prefslot_end = 3;
1961 prefslot_begin = 0; prefslot_end = 3;
1966 prefslot_begin = 0; prefslot_end = 7;
1971 assert(prefslot_begin != -1 && prefslot_end != -1 &&
1972 "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
1974 unsigned int ShufBytes[16] = {
1975 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1977 for (int i = 0; i < 16; ++i) {
1978 // zero fill uppper part of preferred slot, don't care about the
1980 unsigned int mask_val;
1981 if (i <= prefslot_end) {
1983 ((i < prefslot_begin)
1985 : elt_byte + (i - prefslot_begin));
1987 ShufBytes[i] = mask_val;
1989 ShufBytes[i] = ShufBytes[i % (prefslot_end + 1)];
1992 SDValue ShufMask[4];
1993 for (unsigned i = 0; i < sizeof(ShufMask)/sizeof(ShufMask[0]); ++i) {
1994 unsigned bidx = i * 4;
1995 unsigned int bits = ((ShufBytes[bidx] << 24) |
1996 (ShufBytes[bidx+1] << 16) |
1997 (ShufBytes[bidx+2] << 8) |
1999 ShufMask[i] = DAG.getConstant(bits, MVT::i32);
2002 SDValue ShufMaskVec =
2003 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2004 &ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
2006 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2007 DAG.getNode(SPUISD::SHUFB, dl, N.getValueType(),
2008 N, N, ShufMaskVec));
2010 // Variable index: Rotate the requested element into slot 0, then replicate
2011 // slot 0 across the vector
2012 EVT VecVT = N.getValueType();
2013 if (!VecVT.isSimple() || !VecVT.isVector()) {
2014 report_fatal_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
2018 // Make life easier by making sure the index is zero-extended to i32
2019 if (Elt.getValueType() != MVT::i32)
2020 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
2022 // Scale the index to a bit/byte shift quantity
2024 APInt(32, uint64_t(16 / N.getValueType().getVectorNumElements()), false);
2025 unsigned scaleShift = scaleFactor.logBase2();
2028 if (scaleShift > 0) {
2029 // Scale the shift factor:
2030 Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
2031 DAG.getConstant(scaleShift, MVT::i32));
2034 vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
2036 // Replicate the bytes starting at byte 0 across the entire vector (for
2037 // consistency with the notion of a unified register set)
2040 switch (VT.getSimpleVT().SimpleTy) {
2042 report_fatal_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
2046 SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
2047 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2048 factor, factor, factor, factor);
2052 SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
2053 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2054 factor, factor, factor, factor);
2059 SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
2060 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2061 factor, factor, factor, factor);
2066 SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
2067 SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
2068 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2069 loFactor, hiFactor, loFactor, hiFactor);
2074 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2075 DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2076 vecShift, vecShift, replicate));
2082 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2083 SDValue VecOp = Op.getOperand(0);
2084 SDValue ValOp = Op.getOperand(1);
2085 SDValue IdxOp = Op.getOperand(2);
2086 DebugLoc dl = Op.getDebugLoc();
2087 EVT VT = Op.getValueType();
2089 // use 0 when the lane to insert to is 'undef'
2091 if (IdxOp.getOpcode() != ISD::UNDEF) {
2092 ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
2093 assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
2094 Idx = (CN->getSExtValue());
2097 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2098 // Use $sp ($1) because it's always 16-byte aligned and it's available:
2099 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
2100 DAG.getRegister(SPU::R1, PtrVT),
2101 DAG.getConstant(Idx, PtrVT));
2102 SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
2105 DAG.getNode(SPUISD::SHUFB, dl, VT,
2106 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
2108 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
2113 static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
2114 const TargetLowering &TLI)
2116 SDValue N0 = Op.getOperand(0); // Everything has at least one operand
2117 DebugLoc dl = Op.getDebugLoc();
2118 EVT ShiftVT = TLI.getShiftAmountTy();
2120 assert(Op.getValueType() == MVT::i8);
2123 llvm_unreachable("Unhandled i8 math operator");
2127 // 8-bit addition: Promote the arguments up to 16-bits and truncate
2129 SDValue N1 = Op.getOperand(1);
2130 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2131 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2132 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2133 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2138 // 8-bit subtraction: Promote the arguments up to 16-bits and truncate
2140 SDValue N1 = Op.getOperand(1);
2141 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2142 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2143 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2144 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2148 SDValue N1 = Op.getOperand(1);
2149 EVT N1VT = N1.getValueType();
2151 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2152 if (!N1VT.bitsEq(ShiftVT)) {
2153 unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
2156 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2159 // Replicate lower 8-bits into upper 8:
2161 DAG.getNode(ISD::OR, dl, MVT::i16, N0,
2162 DAG.getNode(ISD::SHL, dl, MVT::i16,
2163 N0, DAG.getConstant(8, MVT::i32)));
2165 // Truncate back down to i8
2166 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2167 DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
2171 SDValue N1 = Op.getOperand(1);
2172 EVT N1VT = N1.getValueType();
2174 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2175 if (!N1VT.bitsEq(ShiftVT)) {
2176 unsigned N1Opc = ISD::ZERO_EXTEND;
2178 if (N1.getValueType().bitsGT(ShiftVT))
2179 N1Opc = ISD::TRUNCATE;
2181 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2184 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2185 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2188 SDValue N1 = Op.getOperand(1);
2189 EVT N1VT = N1.getValueType();
2191 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2192 if (!N1VT.bitsEq(ShiftVT)) {
2193 unsigned N1Opc = ISD::SIGN_EXTEND;
2195 if (N1VT.bitsGT(ShiftVT))
2196 N1Opc = ISD::TRUNCATE;
2197 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2200 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2201 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2204 SDValue N1 = Op.getOperand(1);
2206 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2207 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2208 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2209 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2217 //! Lower byte immediate operations for v16i8 vectors:
2219 LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
2222 EVT VT = Op.getValueType();
2223 DebugLoc dl = Op.getDebugLoc();
2225 ConstVec = Op.getOperand(0);
2226 Arg = Op.getOperand(1);
2227 if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
2228 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2229 ConstVec = ConstVec.getOperand(0);
2231 ConstVec = Op.getOperand(1);
2232 Arg = Op.getOperand(0);
2233 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2234 ConstVec = ConstVec.getOperand(0);
2239 if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
2240 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(ConstVec.getNode());
2241 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerByteImmed");
2243 APInt APSplatBits, APSplatUndef;
2244 unsigned SplatBitSize;
2246 unsigned minSplatBits = VT.getVectorElementType().getSizeInBits();
2248 if (BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2249 HasAnyUndefs, minSplatBits)
2250 && minSplatBits <= SplatBitSize) {
2251 uint64_t SplatBits = APSplatBits.getZExtValue();
2252 SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
2254 SmallVector<SDValue, 16> tcVec;
2255 tcVec.assign(16, tc);
2256 return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
2257 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &tcVec[0], tcVec.size()));
2261 // These operations (AND, OR, XOR) are legal, they just couldn't be custom
2262 // lowered. Return the operation, rather than a null SDValue.
2266 //! Custom lowering for CTPOP (count population)
2268 Custom lowering code that counts the number ones in the input
2269 operand. SPU has such an instruction, but it counts the number of
2270 ones per byte, which then have to be accumulated.
2272 static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
2273 EVT VT = Op.getValueType();
2274 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
2275 VT, (128 / VT.getSizeInBits()));
2276 DebugLoc dl = Op.getDebugLoc();
2278 switch (VT.getSimpleVT().SimpleTy) {
2280 assert(false && "Invalid value type!");
2282 SDValue N = Op.getOperand(0);
2283 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2285 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2286 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2288 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
2292 MachineFunction &MF = DAG.getMachineFunction();
2293 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2295 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
2297 SDValue N = Op.getOperand(0);
2298 SDValue Elt0 = DAG.getConstant(0, MVT::i16);
2299 SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
2300 SDValue Shift1 = DAG.getConstant(8, MVT::i32);
2302 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2303 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2305 // CNTB_result becomes the chain to which all of the virtual registers
2306 // CNTB_reg, SUM1_reg become associated:
2307 SDValue CNTB_result =
2308 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
2310 SDValue CNTB_rescopy =
2311 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2313 SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
2315 return DAG.getNode(ISD::AND, dl, MVT::i16,
2316 DAG.getNode(ISD::ADD, dl, MVT::i16,
2317 DAG.getNode(ISD::SRL, dl, MVT::i16,
2324 MachineFunction &MF = DAG.getMachineFunction();
2325 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2327 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2328 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2330 SDValue N = Op.getOperand(0);
2331 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2332 SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
2333 SDValue Shift1 = DAG.getConstant(16, MVT::i32);
2334 SDValue Shift2 = DAG.getConstant(8, MVT::i32);
2336 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2337 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2339 // CNTB_result becomes the chain to which all of the virtual registers
2340 // CNTB_reg, SUM1_reg become associated:
2341 SDValue CNTB_result =
2342 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
2344 SDValue CNTB_rescopy =
2345 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2348 DAG.getNode(ISD::SRL, dl, MVT::i32,
2349 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
2353 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
2354 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
2356 SDValue Sum1_rescopy =
2357 DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
2360 DAG.getNode(ISD::SRL, dl, MVT::i32,
2361 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
2364 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
2365 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
2367 return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
2377 //! Lower ISD::FP_TO_SINT, ISD::FP_TO_UINT for i32
2379 f32->i32 passes through unchanged, whereas f64->i32 expands to a libcall.
2380 All conversions to i64 are expanded to a libcall.
2382 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2383 const SPUTargetLowering &TLI) {
2384 EVT OpVT = Op.getValueType();
2385 SDValue Op0 = Op.getOperand(0);
2386 EVT Op0VT = Op0.getValueType();
2388 if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
2389 || OpVT == MVT::i64) {
2390 // Convert f32 / f64 to i32 / i64 via libcall.
2392 (Op.getOpcode() == ISD::FP_TO_SINT)
2393 ? RTLIB::getFPTOSINT(Op0VT, OpVT)
2394 : RTLIB::getFPTOUINT(Op0VT, OpVT);
2395 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
2397 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2403 //! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
2405 i32->f32 passes through unchanged, whereas i32->f64 is expanded to a libcall.
2406 All conversions from i64 are expanded to a libcall.
2408 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2409 const SPUTargetLowering &TLI) {
2410 EVT OpVT = Op.getValueType();
2411 SDValue Op0 = Op.getOperand(0);
2412 EVT Op0VT = Op0.getValueType();
2414 if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
2415 || Op0VT == MVT::i64) {
2416 // Convert i32, i64 to f64 via libcall:
2418 (Op.getOpcode() == ISD::SINT_TO_FP)
2419 ? RTLIB::getSINTTOFP(Op0VT, OpVT)
2420 : RTLIB::getUINTTOFP(Op0VT, OpVT);
2421 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd int-to-fp conversion!");
2423 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2429 //! Lower ISD::SETCC
2431 This handles MVT::f64 (double floating point) condition lowering
2433 static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
2434 const TargetLowering &TLI) {
2435 CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2));
2436 DebugLoc dl = Op.getDebugLoc();
2437 assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n");
2439 SDValue lhs = Op.getOperand(0);
2440 SDValue rhs = Op.getOperand(1);
2441 EVT lhsVT = lhs.getValueType();
2442 assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
2444 EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
2445 APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2446 EVT IntVT(MVT::i64);
2448 // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
2449 // selected to a NOP:
2450 SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
2452 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2453 DAG.getNode(ISD::SRL, dl, IntVT,
2454 i64lhs, DAG.getConstant(32, MVT::i32)));
2455 SDValue lhsHi32abs =
2456 DAG.getNode(ISD::AND, dl, MVT::i32,
2457 lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
2459 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
2461 // SETO and SETUO only use the lhs operand:
2462 if (CC->get() == ISD::SETO) {
2463 // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of
2465 APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2466 return DAG.getNode(ISD::XOR, dl, ccResultVT,
2467 DAG.getSetCC(dl, ccResultVT,
2468 lhs, DAG.getConstantFP(0.0, lhsVT),
2470 DAG.getConstant(ccResultAllOnes, ccResultVT));
2471 } else if (CC->get() == ISD::SETUO) {
2472 // Evaluates to true if Op0 is [SQ]NaN
2473 return DAG.getNode(ISD::AND, dl, ccResultVT,
2474 DAG.getSetCC(dl, ccResultVT,
2476 DAG.getConstant(0x7ff00000, MVT::i32),
2478 DAG.getSetCC(dl, ccResultVT,
2480 DAG.getConstant(0, MVT::i32),
2484 SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
2486 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2487 DAG.getNode(ISD::SRL, dl, IntVT,
2488 i64rhs, DAG.getConstant(32, MVT::i32)));
2490 // If a value is negative, subtract from the sign magnitude constant:
2491 SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
2493 // Convert the sign-magnitude representation into 2's complement:
2494 SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2495 lhsHi32, DAG.getConstant(31, MVT::i32));
2496 SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
2498 DAG.getNode(ISD::SELECT, dl, IntVT,
2499 lhsSelectMask, lhsSignMag2TC, i64lhs);
2501 SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2502 rhsHi32, DAG.getConstant(31, MVT::i32));
2503 SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
2505 DAG.getNode(ISD::SELECT, dl, IntVT,
2506 rhsSelectMask, rhsSignMag2TC, i64rhs);
2510 switch (CC->get()) {
2513 compareOp = ISD::SETEQ; break;
2516 compareOp = ISD::SETGT; break;
2519 compareOp = ISD::SETGE; break;
2522 compareOp = ISD::SETLT; break;
2525 compareOp = ISD::SETLE; break;
2528 compareOp = ISD::SETNE; break;
2530 report_fatal_error("CellSPU ISel Select: unimplemented f64 condition");
2534 DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
2535 (ISD::CondCode) compareOp);
2537 if ((CC->get() & 0x8) == 0) {
2538 // Ordered comparison:
2539 SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
2540 lhs, DAG.getConstantFP(0.0, MVT::f64),
2542 SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
2543 rhs, DAG.getConstantFP(0.0, MVT::f64),
2545 SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
2547 result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result);
2553 //! Lower ISD::SELECT_CC
2555 ISD::SELECT_CC can (generally) be implemented directly on the SPU using the
2558 \note Need to revisit this in the future: if the code path through the true
2559 and false value computations is longer than the latency of a branch (6
2560 cycles), then it would be more advantageous to branch and insert a new basic
2561 block and branch on the condition. However, this code does not make that
2562 assumption, given the simplisitc uses so far.
2565 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2566 const TargetLowering &TLI) {
2567 EVT VT = Op.getValueType();
2568 SDValue lhs = Op.getOperand(0);
2569 SDValue rhs = Op.getOperand(1);
2570 SDValue trueval = Op.getOperand(2);
2571 SDValue falseval = Op.getOperand(3);
2572 SDValue condition = Op.getOperand(4);
2573 DebugLoc dl = Op.getDebugLoc();
2575 // NOTE: SELB's arguments: $rA, $rB, $mask
2577 // SELB selects bits from $rA where bits in $mask are 0, bits from $rB
2578 // where bits in $mask are 1. CCond will be inverted, having 1s where the
2579 // condition was true and 0s where the condition was false. Hence, the
2580 // arguments to SELB get reversed.
2582 // Note: Really should be ISD::SELECT instead of SPUISD::SELB, but LLVM's
2583 // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
2584 // with another "cannot select select_cc" assert:
2586 SDValue compare = DAG.getNode(ISD::SETCC, dl,
2587 TLI.getSetCCResultType(Op.getValueType()),
2588 lhs, rhs, condition);
2589 return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare);
2592 //! Custom lower ISD::TRUNCATE
2593 static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
2595 // Type to truncate to
2596 EVT VT = Op.getValueType();
2597 MVT simpleVT = VT.getSimpleVT();
2598 EVT VecVT = EVT::getVectorVT(*DAG.getContext(),
2599 VT, (128 / VT.getSizeInBits()));
2600 DebugLoc dl = Op.getDebugLoc();
2602 // Type to truncate from
2603 SDValue Op0 = Op.getOperand(0);
2604 EVT Op0VT = Op0.getValueType();
2606 if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
2607 // Create shuffle mask, least significant doubleword of quadword
2608 unsigned maskHigh = 0x08090a0b;
2609 unsigned maskLow = 0x0c0d0e0f;
2610 // Use a shuffle to perform the truncation
2611 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2612 DAG.getConstant(maskHigh, MVT::i32),
2613 DAG.getConstant(maskLow, MVT::i32),
2614 DAG.getConstant(maskHigh, MVT::i32),
2615 DAG.getConstant(maskLow, MVT::i32));
2617 SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2618 Op0, Op0, shufMask);
2620 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle);
2623 return SDValue(); // Leave the truncate unmolested
2627 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2628 * algorithm is to duplicate the sign bit using rotmai to generate at
2629 * least one byte full of sign bits. Then propagate the "sign-byte" into
2630 * the leftmost words and the i64/i32 into the rightmost words using shufb.
2632 * @param Op The sext operand
2633 * @param DAG The current DAG
2634 * @return The SDValue with the entire instruction sequence
2636 static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
2638 DebugLoc dl = Op.getDebugLoc();
2640 // Type to extend to
2641 MVT OpVT = Op.getValueType().getSimpleVT();
2643 // Type to extend from
2644 SDValue Op0 = Op.getOperand(0);
2645 MVT Op0VT = Op0.getValueType().getSimpleVT();
2647 // The type to extend to needs to be a i128 and
2648 // the type to extend from needs to be i64 or i32.
2649 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2650 "LowerSIGN_EXTEND: input and/or output operand have wrong size");
2652 // Create shuffle mask
2653 unsigned mask1 = 0x10101010; // byte 0 - 3 and 4 - 7
2654 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2655 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2656 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2657 DAG.getConstant(mask1, MVT::i32),
2658 DAG.getConstant(mask1, MVT::i32),
2659 DAG.getConstant(mask2, MVT::i32),
2660 DAG.getConstant(mask3, MVT::i32));
2662 // Word wise arithmetic right shift to generate at least one byte
2663 // that contains sign bits.
2664 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2665 SDValue sraVal = DAG.getNode(ISD::SRA,
2668 DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
2669 DAG.getConstant(31, MVT::i32));
2671 // Shuffle bytes - Copy the sign bits into the upper 64 bits
2672 // and the input value into the lower 64 bits.
2673 SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
2674 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
2676 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
2679 //! Custom (target-specific) lowering entry point
2681 This is where LLVM's DAG selection process calls to do target-specific
2685 SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
2687 unsigned Opc = (unsigned) Op.getOpcode();
2688 EVT VT = Op.getValueType();
2693 errs() << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
2694 errs() << "Op.getOpcode() = " << Opc << "\n";
2695 errs() << "*Op.getNode():\n";
2696 Op.getNode()->dump();
2698 llvm_unreachable(0);
2704 return LowerLOAD(Op, DAG, SPUTM.getSubtargetImpl());
2706 return LowerSTORE(Op, DAG, SPUTM.getSubtargetImpl());
2707 case ISD::ConstantPool:
2708 return LowerConstantPool(Op, DAG, SPUTM.getSubtargetImpl());
2709 case ISD::GlobalAddress:
2710 return LowerGlobalAddress(Op, DAG, SPUTM.getSubtargetImpl());
2711 case ISD::JumpTable:
2712 return LowerJumpTable(Op, DAG, SPUTM.getSubtargetImpl());
2713 case ISD::ConstantFP:
2714 return LowerConstantFP(Op, DAG);
2716 // i8, i64 math ops:
2725 return LowerI8Math(Op, DAG, Opc, *this);
2729 case ISD::FP_TO_SINT:
2730 case ISD::FP_TO_UINT:
2731 return LowerFP_TO_INT(Op, DAG, *this);
2733 case ISD::SINT_TO_FP:
2734 case ISD::UINT_TO_FP:
2735 return LowerINT_TO_FP(Op, DAG, *this);
2737 // Vector-related lowering.
2738 case ISD::BUILD_VECTOR:
2739 return LowerBUILD_VECTOR(Op, DAG);
2740 case ISD::SCALAR_TO_VECTOR:
2741 return LowerSCALAR_TO_VECTOR(Op, DAG);
2742 case ISD::VECTOR_SHUFFLE:
2743 return LowerVECTOR_SHUFFLE(Op, DAG);
2744 case ISD::EXTRACT_VECTOR_ELT:
2745 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2746 case ISD::INSERT_VECTOR_ELT:
2747 return LowerINSERT_VECTOR_ELT(Op, DAG);
2749 // Look for ANDBI, ORBI and XORBI opportunities and lower appropriately:
2753 return LowerByteImmed(Op, DAG);
2755 // Vector and i8 multiply:
2758 return LowerI8Math(Op, DAG, Opc, *this);
2761 return LowerCTPOP(Op, DAG);
2763 case ISD::SELECT_CC:
2764 return LowerSELECT_CC(Op, DAG, *this);
2767 return LowerSETCC(Op, DAG, *this);
2770 return LowerTRUNCATE(Op, DAG);
2772 case ISD::SIGN_EXTEND:
2773 return LowerSIGN_EXTEND(Op, DAG);
2779 void SPUTargetLowering::ReplaceNodeResults(SDNode *N,
2780 SmallVectorImpl<SDValue>&Results,
2781 SelectionDAG &DAG) const
2784 unsigned Opc = (unsigned) N->getOpcode();
2785 EVT OpVT = N->getValueType(0);
2789 errs() << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
2790 errs() << "Op.getOpcode() = " << Opc << "\n";
2791 errs() << "*Op.getNode():\n";
2799 /* Otherwise, return unchanged */
2802 //===----------------------------------------------------------------------===//
2803 // Target Optimization Hooks
2804 //===----------------------------------------------------------------------===//
2807 SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
2810 TargetMachine &TM = getTargetMachine();
2812 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
2813 SelectionDAG &DAG = DCI.DAG;
2814 SDValue Op0 = N->getOperand(0); // everything has at least one operand
2815 EVT NodeVT = N->getValueType(0); // The node's value type
2816 EVT Op0VT = Op0.getValueType(); // The first operand's result
2817 SDValue Result; // Initially, empty result
2818 DebugLoc dl = N->getDebugLoc();
2820 switch (N->getOpcode()) {
2823 SDValue Op1 = N->getOperand(1);
2825 if (Op0.getOpcode() == SPUISD::IndirectAddr
2826 || Op1.getOpcode() == SPUISD::IndirectAddr) {
2827 // Normalize the operands to reduce repeated code
2828 SDValue IndirectArg = Op0, AddArg = Op1;
2830 if (Op1.getOpcode() == SPUISD::IndirectAddr) {
2835 if (isa<ConstantSDNode>(AddArg)) {
2836 ConstantSDNode *CN0 = cast<ConstantSDNode > (AddArg);
2837 SDValue IndOp1 = IndirectArg.getOperand(1);
2839 if (CN0->isNullValue()) {
2840 // (add (SPUindirect <arg>, <arg>), 0) ->
2841 // (SPUindirect <arg>, <arg>)
2843 #if !defined(NDEBUG)
2844 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2846 << "Replace: (add (SPUindirect <arg>, <arg>), 0)\n"
2847 << "With: (SPUindirect <arg>, <arg>)\n";
2852 } else if (isa<ConstantSDNode>(IndOp1)) {
2853 // (add (SPUindirect <arg>, <const>), <const>) ->
2854 // (SPUindirect <arg>, <const + const>)
2855 ConstantSDNode *CN1 = cast<ConstantSDNode > (IndOp1);
2856 int64_t combinedConst = CN0->getSExtValue() + CN1->getSExtValue();
2857 SDValue combinedValue = DAG.getConstant(combinedConst, Op0VT);
2859 #if !defined(NDEBUG)
2860 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2862 << "Replace: (add (SPUindirect <arg>, " << CN1->getSExtValue()
2863 << "), " << CN0->getSExtValue() << ")\n"
2864 << "With: (SPUindirect <arg>, "
2865 << combinedConst << ")\n";
2869 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2870 IndirectArg, combinedValue);
2876 case ISD::SIGN_EXTEND:
2877 case ISD::ZERO_EXTEND:
2878 case ISD::ANY_EXTEND: {
2879 if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) {
2880 // (any_extend (SPUextract_elt0 <arg>)) ->
2881 // (SPUextract_elt0 <arg>)
2882 // Types must match, however...
2883 #if !defined(NDEBUG)
2884 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2885 errs() << "\nReplace: ";
2887 errs() << "\nWith: ";
2888 Op0.getNode()->dump(&DAG);
2897 case SPUISD::IndirectAddr: {
2898 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
2899 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1));
2900 if (CN != 0 && CN->isNullValue()) {
2901 // (SPUindirect (SPUaform <addr>, 0), 0) ->
2902 // (SPUaform <addr>, 0)
2904 DEBUG(errs() << "Replace: ");
2905 DEBUG(N->dump(&DAG));
2906 DEBUG(errs() << "\nWith: ");
2907 DEBUG(Op0.getNode()->dump(&DAG));
2908 DEBUG(errs() << "\n");
2912 } else if (Op0.getOpcode() == ISD::ADD) {
2913 SDValue Op1 = N->getOperand(1);
2914 if (ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(Op1)) {
2915 // (SPUindirect (add <arg>, <arg>), 0) ->
2916 // (SPUindirect <arg>, <arg>)
2917 if (CN1->isNullValue()) {
2919 #if !defined(NDEBUG)
2920 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2922 << "Replace: (SPUindirect (add <arg>, <arg>), 0)\n"
2923 << "With: (SPUindirect <arg>, <arg>)\n";
2927 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2928 Op0.getOperand(0), Op0.getOperand(1));
2934 case SPUISD::SHLQUAD_L_BITS:
2935 case SPUISD::SHLQUAD_L_BYTES:
2936 case SPUISD::ROTBYTES_LEFT: {
2937 SDValue Op1 = N->getOperand(1);
2939 // Kill degenerate vector shifts:
2940 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
2941 if (CN->isNullValue()) {
2947 case SPUISD::PREFSLOT2VEC: {
2948 switch (Op0.getOpcode()) {
2951 case ISD::ANY_EXTEND:
2952 case ISD::ZERO_EXTEND:
2953 case ISD::SIGN_EXTEND: {
2954 // (SPUprefslot2vec (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
2956 // but only if the SPUprefslot2vec and <arg> types match.
2957 SDValue Op00 = Op0.getOperand(0);
2958 if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
2959 SDValue Op000 = Op00.getOperand(0);
2960 if (Op000.getValueType() == NodeVT) {
2966 case SPUISD::VEC2PREFSLOT: {
2967 // (SPUprefslot2vec (SPUvec2prefslot <arg>)) ->
2969 Result = Op0.getOperand(0);
2977 // Otherwise, return unchanged.
2979 if (Result.getNode()) {
2980 DEBUG(errs() << "\nReplace.SPU: ");
2981 DEBUG(N->dump(&DAG));
2982 DEBUG(errs() << "\nWith: ");
2983 DEBUG(Result.getNode()->dump(&DAG));
2984 DEBUG(errs() << "\n");
2991 //===----------------------------------------------------------------------===//
2992 // Inline Assembly Support
2993 //===----------------------------------------------------------------------===//
2995 /// getConstraintType - Given a constraint letter, return the type of
2996 /// constraint it is for this target.
2997 SPUTargetLowering::ConstraintType
2998 SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const {
2999 if (ConstraintLetter.size() == 1) {
3000 switch (ConstraintLetter[0]) {
3007 return C_RegisterClass;
3010 return TargetLowering::getConstraintType(ConstraintLetter);
3013 std::pair<unsigned, const TargetRegisterClass*>
3014 SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3017 if (Constraint.size() == 1) {
3018 // GCC RS6000 Constraint Letters
3019 switch (Constraint[0]) {
3023 return std::make_pair(0U, SPU::R64CRegisterClass);
3024 return std::make_pair(0U, SPU::R32CRegisterClass);
3027 return std::make_pair(0U, SPU::R32FPRegisterClass);
3028 else if (VT == MVT::f64)
3029 return std::make_pair(0U, SPU::R64FPRegisterClass);
3032 return std::make_pair(0U, SPU::GPRCRegisterClass);
3036 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3039 //! Compute used/known bits for a SPU operand
3041 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3045 const SelectionDAG &DAG,
3046 unsigned Depth ) const {
3048 const uint64_t uint64_sizebits = sizeof(uint64_t) * CHAR_BIT;
3050 switch (Op.getOpcode()) {
3052 // KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3058 case SPUISD::PREFSLOT2VEC:
3059 case SPUISD::LDRESULT:
3060 case SPUISD::VEC2PREFSLOT:
3061 case SPUISD::SHLQUAD_L_BITS:
3062 case SPUISD::SHLQUAD_L_BYTES:
3063 case SPUISD::VEC_ROTL:
3064 case SPUISD::VEC_ROTR:
3065 case SPUISD::ROTBYTES_LEFT:
3066 case SPUISD::SELECT_MASK:
3073 SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
3074 unsigned Depth) const {
3075 switch (Op.getOpcode()) {
3080 EVT VT = Op.getValueType();
3082 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
3085 return VT.getSizeInBits();
3090 // LowerAsmOperandForConstraint
3092 SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3093 char ConstraintLetter,
3094 std::vector<SDValue> &Ops,
3095 SelectionDAG &DAG) const {
3096 // Default, for the time being, to the base class handler
3097 TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
3100 /// isLegalAddressImmediate - Return true if the integer value can be used
3101 /// as the offset of the target addressing mode.
3102 bool SPUTargetLowering::isLegalAddressImmediate(int64_t V,
3103 const Type *Ty) const {
3104 // SPU's addresses are 256K:
3105 return (V > -(1 << 18) && V < (1 << 18) - 1);
3108 bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3113 SPUTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3114 // The SPU target isn't yet aware of offsets.