2 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SPUTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUISelLowering.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUFrameInfo.h"
18 #include "SPUMachineFunction.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Function.h"
21 #include "llvm/Intrinsics.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/VectorExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
40 // Used in getTargetNodeName() below
42 std::map<unsigned, const char *> node_names;
44 //! EVT mapping to useful data for Cell SPU
45 struct valtype_map_s {
50 const valtype_map_s valtype_map[] = {
61 const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
63 const valtype_map_s *getValueTypeMapEntry(EVT VT) {
64 const valtype_map_s *retval = 0;
66 for (size_t i = 0; i < n_valtype_map; ++i) {
67 if (valtype_map[i].valtype == VT) {
68 retval = valtype_map + i;
75 report_fatal_error("getValueTypeMapEntry returns NULL for " +
76 Twine(VT.getEVTString()));
83 //! Expand a library call into an actual call DAG node
86 This code is taken from SelectionDAGLegalize, since it is not exposed as
87 part of the LLVM SelectionDAG API.
91 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
92 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
93 // The input chain to this libcall is the entry node of the function.
94 // Legalizing the call will automatically add the previous call to the
96 SDValue InChain = DAG.getEntryNode();
98 TargetLowering::ArgListTy Args;
99 TargetLowering::ArgListEntry Entry;
100 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
101 EVT ArgVT = Op.getOperand(i).getValueType();
102 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
103 Entry.Node = Op.getOperand(i);
105 Entry.isSExt = isSigned;
106 Entry.isZExt = !isSigned;
107 Args.push_back(Entry);
109 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
112 // Splice the libcall in wherever FindInputOutputChains tells us to.
114 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
115 std::pair<SDValue, SDValue> CallInfo =
116 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
117 0, TLI.getLibcallCallingConv(LC), false,
118 /*isReturnValueUsed=*/true,
119 Callee, Args, DAG, Op.getDebugLoc());
121 return CallInfo.first;
125 SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
126 : TargetLowering(TM, new TargetLoweringObjectFileELF()),
128 // Fold away setcc operations if possible.
131 // Use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(true);
133 setUseUnderscoreLongJmp(true);
135 // Set RTLIB libcall names as used by SPU:
136 setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
138 // Set up the SPU's register classes:
139 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
140 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
141 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
142 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
143 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
144 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
145 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
147 // SPU has no sign or zero extended loads for i1, i8, i16:
148 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
155 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
156 setTruncStoreAction(MVT::i128, MVT::i32, Expand);
157 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i128, MVT::i8, Expand);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 // SPU constant load actions are custom lowered:
163 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
164 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
166 // SPU's loads and stores have to be custom lowered:
167 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128;
169 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
171 setOperationAction(ISD::LOAD, VT, Custom);
172 setOperationAction(ISD::STORE, VT, Custom);
173 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
174 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
175 setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
177 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) {
178 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
179 setTruncStoreAction(VT, StoreVT, Expand);
183 for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64;
185 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
187 setOperationAction(ISD::LOAD, VT, Custom);
188 setOperationAction(ISD::STORE, VT, Custom);
190 for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) {
191 MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype;
192 setTruncStoreAction(VT, StoreVT, Expand);
196 // Expand the jumptable branches
197 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
198 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
200 // Custom lower SELECT_CC for most cases, but expand by default
201 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
202 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
203 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
204 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
205 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
207 // SPU has no intrinsics for these particular operations:
208 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
210 // SPU has no division/remainder instructions
211 setOperationAction(ISD::SREM, MVT::i8, Expand);
212 setOperationAction(ISD::UREM, MVT::i8, Expand);
213 setOperationAction(ISD::SDIV, MVT::i8, Expand);
214 setOperationAction(ISD::UDIV, MVT::i8, Expand);
215 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
216 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
217 setOperationAction(ISD::SREM, MVT::i16, Expand);
218 setOperationAction(ISD::UREM, MVT::i16, Expand);
219 setOperationAction(ISD::SDIV, MVT::i16, Expand);
220 setOperationAction(ISD::UDIV, MVT::i16, Expand);
221 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
222 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
223 setOperationAction(ISD::SREM, MVT::i32, Expand);
224 setOperationAction(ISD::UREM, MVT::i32, Expand);
225 setOperationAction(ISD::SDIV, MVT::i32, Expand);
226 setOperationAction(ISD::UDIV, MVT::i32, Expand);
227 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
228 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
229 setOperationAction(ISD::SREM, MVT::i64, Expand);
230 setOperationAction(ISD::UREM, MVT::i64, Expand);
231 setOperationAction(ISD::SDIV, MVT::i64, Expand);
232 setOperationAction(ISD::UDIV, MVT::i64, Expand);
233 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
234 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
235 setOperationAction(ISD::SREM, MVT::i128, Expand);
236 setOperationAction(ISD::UREM, MVT::i128, Expand);
237 setOperationAction(ISD::SDIV, MVT::i128, Expand);
238 setOperationAction(ISD::UDIV, MVT::i128, Expand);
239 setOperationAction(ISD::SDIVREM, MVT::i128, Expand);
240 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
242 // We don't support sin/cos/sqrt/fmod
243 setOperationAction(ISD::FSIN , MVT::f64, Expand);
244 setOperationAction(ISD::FCOS , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f64, Expand);
246 setOperationAction(ISD::FSIN , MVT::f32, Expand);
247 setOperationAction(ISD::FCOS , MVT::f32, Expand);
248 setOperationAction(ISD::FREM , MVT::f32, Expand);
250 // Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt
252 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
253 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
258 // SPU can do rotate right and left, so legalize it... but customize for i8
259 // because instructions don't exist.
261 // FIXME: Change from "expand" to appropriate type once ROTR is supported in
263 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
264 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
265 setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/);
267 setOperationAction(ISD::ROTL, MVT::i32, Legal);
268 setOperationAction(ISD::ROTL, MVT::i16, Legal);
269 setOperationAction(ISD::ROTL, MVT::i8, Custom);
271 // SPU has no native version of shift left/right for i8
272 setOperationAction(ISD::SHL, MVT::i8, Custom);
273 setOperationAction(ISD::SRL, MVT::i8, Custom);
274 setOperationAction(ISD::SRA, MVT::i8, Custom);
276 // Make these operations legal and handle them during instruction selection:
277 setOperationAction(ISD::SHL, MVT::i64, Legal);
278 setOperationAction(ISD::SRL, MVT::i64, Legal);
279 setOperationAction(ISD::SRA, MVT::i64, Legal);
281 // Custom lower i8, i32 and i64 multiplications
282 setOperationAction(ISD::MUL, MVT::i8, Custom);
283 setOperationAction(ISD::MUL, MVT::i32, Legal);
284 setOperationAction(ISD::MUL, MVT::i64, Legal);
286 // Expand double-width multiplication
287 // FIXME: It would probably be reasonable to support some of these operations
288 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
289 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
290 setOperationAction(ISD::MULHU, MVT::i8, Expand);
291 setOperationAction(ISD::MULHS, MVT::i8, Expand);
292 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
293 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
294 setOperationAction(ISD::MULHU, MVT::i16, Expand);
295 setOperationAction(ISD::MULHS, MVT::i16, Expand);
296 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
297 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
298 setOperationAction(ISD::MULHU, MVT::i32, Expand);
299 setOperationAction(ISD::MULHS, MVT::i32, Expand);
300 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
301 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
302 setOperationAction(ISD::MULHU, MVT::i64, Expand);
303 setOperationAction(ISD::MULHS, MVT::i64, Expand);
305 // Need to custom handle (some) common i8, i64 math ops
306 setOperationAction(ISD::ADD, MVT::i8, Custom);
307 setOperationAction(ISD::ADD, MVT::i64, Legal);
308 setOperationAction(ISD::SUB, MVT::i8, Custom);
309 setOperationAction(ISD::SUB, MVT::i64, Legal);
311 // SPU does not have BSWAP. It does have i32 support CTLZ.
312 // CTPOP has to be custom lowered.
313 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
314 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
316 setOperationAction(ISD::CTPOP, MVT::i8, Custom);
317 setOperationAction(ISD::CTPOP, MVT::i16, Custom);
318 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
319 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
320 setOperationAction(ISD::CTPOP, MVT::i128, Expand);
322 setOperationAction(ISD::CTTZ , MVT::i8, Expand);
323 setOperationAction(ISD::CTTZ , MVT::i16, Expand);
324 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
325 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
326 setOperationAction(ISD::CTTZ , MVT::i128, Expand);
328 setOperationAction(ISD::CTLZ , MVT::i8, Promote);
329 setOperationAction(ISD::CTLZ , MVT::i16, Promote);
330 setOperationAction(ISD::CTLZ , MVT::i32, Legal);
331 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
332 setOperationAction(ISD::CTLZ , MVT::i128, Expand);
334 // SPU has a version of select that implements (a&~c)|(b&c), just like
335 // select ought to work:
336 setOperationAction(ISD::SELECT, MVT::i8, Legal);
337 setOperationAction(ISD::SELECT, MVT::i16, Legal);
338 setOperationAction(ISD::SELECT, MVT::i32, Legal);
339 setOperationAction(ISD::SELECT, MVT::i64, Legal);
341 setOperationAction(ISD::SETCC, MVT::i8, Legal);
342 setOperationAction(ISD::SETCC, MVT::i16, Legal);
343 setOperationAction(ISD::SETCC, MVT::i32, Legal);
344 setOperationAction(ISD::SETCC, MVT::i64, Legal);
345 setOperationAction(ISD::SETCC, MVT::f64, Custom);
347 // Custom lower i128 -> i64 truncates
348 setOperationAction(ISD::TRUNCATE, MVT::i64, Custom);
350 // Custom lower i32/i64 -> i128 sign extend
351 setOperationAction(ISD::SIGN_EXTEND, MVT::i128, Custom);
353 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
354 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
355 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
357 // SPU has a legal FP -> signed INT instruction for f32, but for f64, need
358 // to expand to a libcall, hence the custom lowering:
359 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
361 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
362 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
363 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
364 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand);
366 // FDIV on SPU requires custom lowering
367 setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall
369 // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64:
370 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
371 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
372 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
373 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
380 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
381 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
382 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
384 // We cannot sextinreg(i1). Expand to shifts.
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
387 // We want to legalize GlobalAddress and ConstantPool nodes into the
388 // appropriate instructions to materialize the address.
389 for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128;
391 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
393 setOperationAction(ISD::GlobalAddress, VT, Custom);
394 setOperationAction(ISD::ConstantPool, VT, Custom);
395 setOperationAction(ISD::JumpTable, VT, Custom);
398 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
399 setOperationAction(ISD::VASTART , MVT::Other, Custom);
401 // Use the default implementation.
402 setOperationAction(ISD::VAARG , MVT::Other, Expand);
403 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
404 setOperationAction(ISD::VAEND , MVT::Other, Expand);
405 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
406 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
407 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
408 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
410 // Cell SPU has instructions for converting between i64 and fp.
411 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
412 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
414 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
415 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
417 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
418 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
420 // First set operation action for all vector types to expand. Then we
421 // will selectively turn on ones that can be effectively codegen'd.
422 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
423 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
424 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
425 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
426 addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
427 addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
429 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
430 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
431 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
433 // add/sub are legal for all supported vector VT's.
434 setOperationAction(ISD::ADD, VT, Legal);
435 setOperationAction(ISD::SUB, VT, Legal);
436 // mul has to be custom lowered.
437 setOperationAction(ISD::MUL, VT, Legal);
439 setOperationAction(ISD::AND, VT, Legal);
440 setOperationAction(ISD::OR, VT, Legal);
441 setOperationAction(ISD::XOR, VT, Legal);
442 setOperationAction(ISD::LOAD, VT, Legal);
443 setOperationAction(ISD::SELECT, VT, Legal);
444 setOperationAction(ISD::STORE, VT, Legal);
446 // These operations need to be expanded:
447 setOperationAction(ISD::SDIV, VT, Expand);
448 setOperationAction(ISD::SREM, VT, Expand);
449 setOperationAction(ISD::UDIV, VT, Expand);
450 setOperationAction(ISD::UREM, VT, Expand);
452 // Custom lower build_vector, constant pool spills, insert and
453 // extract vector elements:
454 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
455 setOperationAction(ISD::ConstantPool, VT, Custom);
456 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
457 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
458 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
459 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
462 setOperationAction(ISD::AND, MVT::v16i8, Custom);
463 setOperationAction(ISD::OR, MVT::v16i8, Custom);
464 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
465 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
467 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setShiftAmountType(MVT::i32);
470 setBooleanContents(ZeroOrNegativeOneBooleanContent);
472 setStackPointerRegisterToSaveRestore(SPU::R1);
474 // We have target-specific dag combine patterns for the following nodes:
475 setTargetDAGCombine(ISD::ADD);
476 setTargetDAGCombine(ISD::ZERO_EXTEND);
477 setTargetDAGCombine(ISD::SIGN_EXTEND);
478 setTargetDAGCombine(ISD::ANY_EXTEND);
480 computeRegisterProperties();
482 // Set pre-RA register scheduler default to BURR, which produces slightly
483 // better code than the default (could also be TDRR, but TargetLowering.h
484 // needs a mod to support that model):
485 setSchedulingPreference(Sched::RegPressure);
489 SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
491 if (node_names.empty()) {
492 node_names[(unsigned) SPUISD::RET_FLAG] = "SPUISD::RET_FLAG";
493 node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi";
494 node_names[(unsigned) SPUISD::Lo] = "SPUISD::Lo";
495 node_names[(unsigned) SPUISD::PCRelAddr] = "SPUISD::PCRelAddr";
496 node_names[(unsigned) SPUISD::AFormAddr] = "SPUISD::AFormAddr";
497 node_names[(unsigned) SPUISD::IndirectAddr] = "SPUISD::IndirectAddr";
498 node_names[(unsigned) SPUISD::LDRESULT] = "SPUISD::LDRESULT";
499 node_names[(unsigned) SPUISD::CALL] = "SPUISD::CALL";
500 node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB";
501 node_names[(unsigned) SPUISD::SHUFFLE_MASK] = "SPUISD::SHUFFLE_MASK";
502 node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
503 node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC";
504 node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT";
505 node_names[(unsigned) SPUISD::SHLQUAD_L_BITS] = "SPUISD::SHLQUAD_L_BITS";
506 node_names[(unsigned) SPUISD::SHLQUAD_L_BYTES] = "SPUISD::SHLQUAD_L_BYTES";
507 node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL";
508 node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR";
509 node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
510 node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] =
511 "SPUISD::ROTBYTES_LEFT_BITS";
512 node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK";
513 node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB";
514 node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER";
515 node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER";
516 node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER";
519 std::map<unsigned, const char *>::iterator i = node_names.find(Opcode);
521 return ((i != node_names.end()) ? i->second : 0);
524 /// getFunctionAlignment - Return the Log2 alignment of this function.
525 unsigned SPUTargetLowering::getFunctionAlignment(const Function *) const {
529 //===----------------------------------------------------------------------===//
530 // Return the Cell SPU's SETCC result type
531 //===----------------------------------------------------------------------===//
533 MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const {
534 // i16 and i32 are valid SETCC result types
535 return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ?
536 VT.getSimpleVT().SimpleTy :
540 //===----------------------------------------------------------------------===//
541 // Calling convention code:
542 //===----------------------------------------------------------------------===//
544 #include "SPUGenCallingConv.inc"
546 //===----------------------------------------------------------------------===//
547 // LowerOperation implementation
548 //===----------------------------------------------------------------------===//
550 /// Custom lower loads for CellSPU
552 All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
553 within a 16-byte block, we have to rotate to extract the requested element.
555 For extending loads, we also want to ensure that the following sequence is
556 emitted, e.g. for MVT::f32 extending load to MVT::f64:
560 %2 v16i8,ch = rotate %1
561 %3 v4f8, ch = bitconvert %2
562 %4 f32 = vec2perfslot %3
563 %5 f64 = fp_extend %4
567 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
568 LoadSDNode *LN = cast<LoadSDNode>(Op);
569 SDValue the_chain = LN->getChain();
570 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
571 EVT InVT = LN->getMemoryVT();
572 EVT OutVT = Op.getValueType();
573 ISD::LoadExtType ExtType = LN->getExtensionType();
574 unsigned alignment = LN->getAlignment();
575 const valtype_map_s *vtm = getValueTypeMapEntry(InVT);
576 DebugLoc dl = Op.getDebugLoc();
578 switch (LN->getAddressingMode()) {
579 case ISD::UNINDEXED: {
581 SDValue basePtr = LN->getBasePtr();
584 if (alignment == 16) {
587 // Special cases for a known aligned load to simplify the base pointer
588 // and the rotation amount:
589 if (basePtr.getOpcode() == ISD::ADD
590 && (CN = dyn_cast<ConstantSDNode > (basePtr.getOperand(1))) != 0) {
591 // Known offset into basePtr
592 int64_t offset = CN->getSExtValue();
593 int64_t rotamt = int64_t((offset & 0xf) - vtm->prefslot_byte);
598 rotate = DAG.getConstant(rotamt, MVT::i16);
600 // Simplify the base pointer for this case:
601 basePtr = basePtr.getOperand(0);
602 if ((offset & ~0xf) > 0) {
603 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
605 DAG.getConstant((offset & ~0xf), PtrVT));
607 } else if ((basePtr.getOpcode() == SPUISD::AFormAddr)
608 || (basePtr.getOpcode() == SPUISD::IndirectAddr
609 && basePtr.getOperand(0).getOpcode() == SPUISD::Hi
610 && basePtr.getOperand(1).getOpcode() == SPUISD::Lo)) {
611 // Plain aligned a-form address: rotate into preferred slot
612 // Same for (SPUindirect (SPUhi ...), (SPUlo ...))
613 int64_t rotamt = -vtm->prefslot_byte;
616 rotate = DAG.getConstant(rotamt, MVT::i16);
618 // Offset the rotate amount by the basePtr and the preferred slot
620 int64_t rotamt = -vtm->prefslot_byte;
623 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
625 DAG.getConstant(rotamt, PtrVT));
628 // Unaligned load: must be more pessimistic about addressing modes:
629 if (basePtr.getOpcode() == ISD::ADD) {
630 MachineFunction &MF = DAG.getMachineFunction();
631 MachineRegisterInfo &RegInfo = MF.getRegInfo();
632 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
635 SDValue Op0 = basePtr.getOperand(0);
636 SDValue Op1 = basePtr.getOperand(1);
638 if (isa<ConstantSDNode>(Op1)) {
639 // Convert the (add <ptr>, <const>) to an indirect address contained
640 // in a register. Note that this is done because we need to avoid
641 // creating a 0(reg) d-form address due to the SPU's block loads.
642 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
643 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
644 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
646 // Convert the (add <arg1>, <arg2>) to an indirect address, which
647 // will likely be lowered as a reg(reg) x-form address.
648 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
651 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
653 DAG.getConstant(0, PtrVT));
656 // Offset the rotate amount by the basePtr and the preferred slot
658 rotate = DAG.getNode(ISD::ADD, dl, PtrVT,
660 DAG.getConstant(-vtm->prefslot_byte, PtrVT));
663 // Re-emit as a v16i8 vector load
664 result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr,
665 LN->getSrcValue(), LN->getSrcValueOffset(),
666 LN->isVolatile(), LN->isNonTemporal(), 16);
669 the_chain = result.getValue(1);
671 // Rotate into the preferred slot:
672 result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8,
673 result.getValue(0), rotate);
675 // Convert the loaded v16i8 vector to the appropriate vector type
676 // specified by the operand:
677 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
678 InVT, (128 / InVT.getSizeInBits()));
679 result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT,
680 DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result));
682 // Handle extending loads by extending the scalar result:
683 if (ExtType == ISD::SEXTLOAD) {
684 result = DAG.getNode(ISD::SIGN_EXTEND, dl, OutVT, result);
685 } else if (ExtType == ISD::ZEXTLOAD) {
686 result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result);
687 } else if (ExtType == ISD::EXTLOAD) {
688 unsigned NewOpc = ISD::ANY_EXTEND;
690 if (OutVT.isFloatingPoint())
691 NewOpc = ISD::FP_EXTEND;
693 result = DAG.getNode(NewOpc, dl, OutVT, result);
696 SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
697 SDValue retops[2] = {
702 result = DAG.getNode(SPUISD::LDRESULT, dl, retvts,
703 retops, sizeof(retops) / sizeof(retops[0]));
710 case ISD::LAST_INDEXED_MODE:
712 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
714 Twine((unsigned)LN->getAddressingMode()));
722 /// Custom lower stores for CellSPU
724 All CellSPU stores are aligned to 16-byte boundaries, so for elements
725 within a 16-byte block, we have to generate a shuffle to insert the
726 requested element into its place, then store the resulting block.
729 LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
730 StoreSDNode *SN = cast<StoreSDNode>(Op);
731 SDValue Value = SN->getValue();
732 EVT VT = Value.getValueType();
733 EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
734 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
735 DebugLoc dl = Op.getDebugLoc();
736 unsigned alignment = SN->getAlignment();
738 switch (SN->getAddressingMode()) {
739 case ISD::UNINDEXED: {
740 // The vector type we really want to load from the 16-byte chunk.
741 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
742 VT, (128 / VT.getSizeInBits()));
744 SDValue alignLoadVec;
745 SDValue basePtr = SN->getBasePtr();
746 SDValue the_chain = SN->getChain();
747 SDValue insertEltOffs;
749 if (alignment == 16) {
751 // Special cases for a known aligned load to simplify the base pointer
752 // and insertion byte:
753 if (basePtr.getOpcode() == ISD::ADD
754 && (CN = dyn_cast<ConstantSDNode>(basePtr.getOperand(1))) != 0) {
755 // Known offset into basePtr
756 int64_t offset = CN->getSExtValue();
758 // Simplify the base pointer for this case:
759 basePtr = basePtr.getOperand(0);
760 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
762 DAG.getConstant((offset & 0xf), PtrVT));
764 if ((offset & ~0xf) > 0) {
765 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
767 DAG.getConstant((offset & ~0xf), PtrVT));
770 // Otherwise, assume it's at byte 0 of basePtr
771 insertEltOffs = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
773 DAG.getConstant(0, PtrVT));
774 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
776 DAG.getConstant(0, PtrVT));
779 // Unaligned load: must be more pessimistic about addressing modes:
780 if (basePtr.getOpcode() == ISD::ADD) {
781 MachineFunction &MF = DAG.getMachineFunction();
782 MachineRegisterInfo &RegInfo = MF.getRegInfo();
783 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
786 SDValue Op0 = basePtr.getOperand(0);
787 SDValue Op1 = basePtr.getOperand(1);
789 if (isa<ConstantSDNode>(Op1)) {
790 // Convert the (add <ptr>, <const>) to an indirect address contained
791 // in a register. Note that this is done because we need to avoid
792 // creating a 0(reg) d-form address due to the SPU's block loads.
793 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
794 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
795 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
797 // Convert the (add <arg1>, <arg2>) to an indirect address, which
798 // will likely be lowered as a reg(reg) x-form address.
799 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Op0, Op1);
802 basePtr = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
804 DAG.getConstant(0, PtrVT));
807 // Insertion point is solely determined by basePtr's contents
808 insertEltOffs = DAG.getNode(ISD::ADD, dl, PtrVT,
810 DAG.getConstant(0, PtrVT));
813 // Load the memory to which to store.
814 alignLoadVec = DAG.getLoad(vecVT, dl, the_chain, basePtr,
815 SN->getSrcValue(), SN->getSrcValueOffset(),
816 SN->isVolatile(), SN->isNonTemporal(), 16);
819 the_chain = alignLoadVec.getValue(1);
821 LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
822 SDValue theValue = SN->getValue();
826 && (theValue.getOpcode() == ISD::AssertZext
827 || theValue.getOpcode() == ISD::AssertSext)) {
828 // Drill down and get the value for zero- and sign-extended
830 theValue = theValue.getOperand(0);
833 // If the base pointer is already a D-form address, then just create
834 // a new D-form address with a slot offset and the orignal base pointer.
835 // Otherwise generate a D-form address with the slot offset relative
836 // to the stack pointer, which is always aligned.
838 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
839 errs() << "CellSPU LowerSTORE: basePtr = ";
840 basePtr.getNode()->dump(&DAG);
845 SDValue insertEltOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, vecVT,
847 SDValue vectorizeOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, vecVT,
850 result = DAG.getNode(SPUISD::SHUFB, dl, vecVT,
851 vectorizeOp, alignLoadVec,
852 DAG.getNode(ISD::BIT_CONVERT, dl,
853 MVT::v4i32, insertEltOp));
855 result = DAG.getStore(the_chain, dl, result, basePtr,
856 LN->getSrcValue(), LN->getSrcValueOffset(),
857 LN->isVolatile(), LN->isNonTemporal(),
860 #if 0 && !defined(NDEBUG)
861 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
862 const SDValue ¤tRoot = DAG.getRoot();
865 errs() << "------- CellSPU:LowerStore result:\n";
867 errs() << "-------\n";
868 DAG.setRoot(currentRoot);
879 case ISD::LAST_INDEXED_MODE:
881 report_fatal_error("LowerLOAD: Got a LoadSDNode with an addr mode other "
883 Twine((unsigned)SN->getAddressingMode()));
891 //! Generate the address of a constant pool entry.
893 LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
894 EVT PtrVT = Op.getValueType();
895 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
896 const Constant *C = CP->getConstVal();
897 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
898 SDValue Zero = DAG.getConstant(0, PtrVT);
899 const TargetMachine &TM = DAG.getTarget();
900 // FIXME there is no actual debug info here
901 DebugLoc dl = Op.getDebugLoc();
903 if (TM.getRelocationModel() == Reloc::Static) {
904 if (!ST->usingLargeMem()) {
905 // Just return the SDValue with the constant pool address in it.
906 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, CPI, Zero);
908 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, CPI, Zero);
909 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, CPI, Zero);
910 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
914 llvm_unreachable("LowerConstantPool: Relocation model other than static"
919 //! Alternate entry point for generating the address of a constant pool entry
921 SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) {
922 return ::LowerConstantPool(Op, DAG, TM.getSubtargetImpl());
926 LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
927 EVT PtrVT = Op.getValueType();
928 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
929 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
930 SDValue Zero = DAG.getConstant(0, PtrVT);
931 const TargetMachine &TM = DAG.getTarget();
932 // FIXME there is no actual debug info here
933 DebugLoc dl = Op.getDebugLoc();
935 if (TM.getRelocationModel() == Reloc::Static) {
936 if (!ST->usingLargeMem()) {
937 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, JTI, Zero);
939 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, JTI, Zero);
940 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, JTI, Zero);
941 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
945 llvm_unreachable("LowerJumpTable: Relocation model other than static"
951 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
952 EVT PtrVT = Op.getValueType();
953 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
954 const GlobalValue *GV = GSDN->getGlobal();
955 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
956 PtrVT, GSDN->getOffset());
957 const TargetMachine &TM = DAG.getTarget();
958 SDValue Zero = DAG.getConstant(0, PtrVT);
959 // FIXME there is no actual debug info here
960 DebugLoc dl = Op.getDebugLoc();
962 if (TM.getRelocationModel() == Reloc::Static) {
963 if (!ST->usingLargeMem()) {
964 return DAG.getNode(SPUISD::AFormAddr, dl, PtrVT, GA, Zero);
966 SDValue Hi = DAG.getNode(SPUISD::Hi, dl, PtrVT, GA, Zero);
967 SDValue Lo = DAG.getNode(SPUISD::Lo, dl, PtrVT, GA, Zero);
968 return DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, Hi, Lo);
971 report_fatal_error("LowerGlobalAddress: Relocation model other than static"
979 //! Custom lower double precision floating point constants
981 LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
982 EVT VT = Op.getValueType();
983 // FIXME there is no actual debug info here
984 DebugLoc dl = Op.getDebugLoc();
986 if (VT == MVT::f64) {
987 ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
990 "LowerConstantFP: Node is not ConstantFPSDNode");
992 uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
993 SDValue T = DAG.getConstant(dbits, MVT::i64);
994 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T);
995 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
996 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec));
1003 SPUTargetLowering::LowerFormalArguments(SDValue Chain,
1004 CallingConv::ID CallConv, bool isVarArg,
1005 const SmallVectorImpl<ISD::InputArg>
1007 DebugLoc dl, SelectionDAG &DAG,
1008 SmallVectorImpl<SDValue> &InVals)
1011 MachineFunction &MF = DAG.getMachineFunction();
1012 MachineFrameInfo *MFI = MF.getFrameInfo();
1013 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1014 SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>();
1016 unsigned ArgOffset = SPUFrameInfo::minStackSize();
1017 unsigned ArgRegIdx = 0;
1018 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1020 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1022 SmallVector<CCValAssign, 16> ArgLocs;
1023 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1025 // FIXME: allow for other calling conventions
1026 CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
1028 // Add DAG nodes to load the arguments or copy them out of registers.
1029 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1030 EVT ObjectVT = Ins[ArgNo].VT;
1031 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1033 CCValAssign &VA = ArgLocs[ArgNo];
1035 if (VA.isRegLoc()) {
1036 const TargetRegisterClass *ArgRegClass;
1038 switch (ObjectVT.getSimpleVT().SimpleTy) {
1040 report_fatal_error("LowerFormalArguments Unhandled argument type: " +
1041 Twine(ObjectVT.getEVTString()));
1043 ArgRegClass = &SPU::R8CRegClass;
1046 ArgRegClass = &SPU::R16CRegClass;
1049 ArgRegClass = &SPU::R32CRegClass;
1052 ArgRegClass = &SPU::R64CRegClass;
1055 ArgRegClass = &SPU::GPRCRegClass;
1058 ArgRegClass = &SPU::R32FPRegClass;
1061 ArgRegClass = &SPU::R64FPRegClass;
1069 ArgRegClass = &SPU::VECREGRegClass;
1073 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
1074 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1075 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1078 // We need to load the argument to a virtual register if we determined
1079 // above that we ran out of physical registers of the appropriate type
1080 // or we're forced to do vararg
1081 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
1082 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1083 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
1084 ArgOffset += StackSlotSize;
1087 InVals.push_back(ArgVal);
1089 Chain = ArgVal.getOperand(0);
1094 // FIXME: we should be able to query the argument registers from
1095 // tablegen generated code.
1096 static const unsigned ArgRegs[] = {
1097 SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
1098 SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
1099 SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
1100 SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
1101 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
1102 SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
1103 SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
1104 SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
1105 SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
1106 SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
1107 SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
1109 // size of ArgRegs array
1110 unsigned NumArgRegs = 77;
1112 // We will spill (79-3)+1 registers to the stack
1113 SmallVector<SDValue, 79-3+1> MemOps;
1115 // Create the frame slot
1116 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
1117 FuncInfo->setVarArgsFrameIndex(
1118 MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
1119 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1120 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
1121 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1122 SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0,
1124 Chain = Store.getOperand(0);
1125 MemOps.push_back(Store);
1127 // Increment address by stack slot size for the next stored argument
1128 ArgOffset += StackSlotSize;
1130 if (!MemOps.empty())
1131 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1132 &MemOps[0], MemOps.size());
1138 /// isLSAAddress - Return the immediate to use if the specified
1139 /// value is representable as a LSA address.
1140 static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
1141 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1144 int Addr = C->getZExtValue();
1145 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1146 (Addr << 14 >> 14) != Addr)
1147 return 0; // Top 14 bits have to be sext of immediate.
1149 return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
1153 SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1154 CallingConv::ID CallConv, bool isVarArg,
1156 const SmallVectorImpl<ISD::OutputArg> &Outs,
1157 const SmallVectorImpl<SDValue> &OutVals,
1158 const SmallVectorImpl<ISD::InputArg> &Ins,
1159 DebugLoc dl, SelectionDAG &DAG,
1160 SmallVectorImpl<SDValue> &InVals) const {
1161 // CellSPU target does not yet support tail call optimization.
1164 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
1165 unsigned NumOps = Outs.size();
1166 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
1168 SmallVector<CCValAssign, 16> ArgLocs;
1169 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1171 // FIXME: allow for other calling conventions
1172 CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
1174 const unsigned NumArgRegs = ArgLocs.size();
1177 // Handy pointer type
1178 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1180 // Set up a copy of the stack pointer for use loading and storing any
1181 // arguments that may not fit in the registers available for argument
1183 SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32);
1185 // Figure out which arguments are going to go in registers, and which in
1187 unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR]
1188 unsigned ArgRegIdx = 0;
1190 // Keep track of registers passing arguments
1191 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
1192 // And the arguments passed on the stack
1193 SmallVector<SDValue, 8> MemOpChains;
1195 for (; ArgRegIdx != NumOps; ++ArgRegIdx) {
1196 SDValue Arg = OutVals[ArgRegIdx];
1197 CCValAssign &VA = ArgLocs[ArgRegIdx];
1199 // PtrOff will be used to store the current argument to the stack if a
1200 // register cannot be found for it.
1201 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1202 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
1204 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
1205 default: llvm_unreachable("Unexpected ValueType for argument!");
1219 if (ArgRegIdx != NumArgRegs) {
1220 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1222 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
1224 ArgOffset += StackSlotSize;
1230 // Accumulate how many bytes are to be pushed on the stack, including the
1231 // linkage area, and parameter passing area. According to the SPU ABI,
1232 // we minimally need space for [LR] and [SP].
1233 unsigned NumStackBytes = ArgOffset - SPUFrameInfo::minStackSize();
1235 // Insert a call sequence start
1236 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes,
1239 if (!MemOpChains.empty()) {
1240 // Adjust the stack pointer for the stack arguments.
1241 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1242 &MemOpChains[0], MemOpChains.size());
1245 // Build a sequence of copy-to-reg nodes chained together with token chain
1246 // and flag operands which copy the outgoing args into the appropriate regs.
1248 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1249 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1250 RegsToPass[i].second, InFlag);
1251 InFlag = Chain.getValue(1);
1254 SmallVector<SDValue, 8> Ops;
1255 unsigned CallOpc = SPUISD::CALL;
1257 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1258 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1259 // node so that legalize doesn't hack it.
1260 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1261 const GlobalValue *GV = G->getGlobal();
1262 EVT CalleeVT = Callee.getValueType();
1263 SDValue Zero = DAG.getConstant(0, PtrVT);
1264 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, CalleeVT);
1266 if (!ST->usingLargeMem()) {
1267 // Turn calls to targets that are defined (i.e., have bodies) into BRSL
1268 // style calls, otherwise, external symbols are BRASL calls. This assumes
1269 // that declared/defined symbols are in the same compilation unit and can
1270 // be reached through PC-relative jumps.
1273 // This may be an unsafe assumption for JIT and really large compilation
1275 if (GV->isDeclaration()) {
1276 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, GA, Zero);
1278 Callee = DAG.getNode(SPUISD::PCRelAddr, dl, CalleeVT, GA, Zero);
1281 // "Large memory" mode: Turn all calls into indirect calls with a X-form
1283 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero);
1285 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1286 EVT CalleeVT = Callee.getValueType();
1287 SDValue Zero = DAG.getConstant(0, PtrVT);
1288 SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(),
1289 Callee.getValueType());
1291 if (!ST->usingLargeMem()) {
1292 Callee = DAG.getNode(SPUISD::AFormAddr, dl, CalleeVT, ExtSym, Zero);
1294 Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, ExtSym, Zero);
1296 } else if (SDNode *Dest = isLSAAddress(Callee, DAG)) {
1297 // If this is an absolute destination address that appears to be a legal
1298 // local store address, use the munged value.
1299 Callee = SDValue(Dest, 0);
1302 Ops.push_back(Chain);
1303 Ops.push_back(Callee);
1305 // Add argument registers to the end of the list so that they are known live
1307 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1308 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1309 RegsToPass[i].second.getValueType()));
1311 if (InFlag.getNode())
1312 Ops.push_back(InFlag);
1313 // Returns a chain and a flag for retval copy to use.
1314 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1315 &Ops[0], Ops.size());
1316 InFlag = Chain.getValue(1);
1318 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumStackBytes, true),
1319 DAG.getIntPtrConstant(0, true), InFlag);
1321 InFlag = Chain.getValue(1);
1323 // If the function returns void, just return the chain.
1327 // Now handle the return value(s)
1328 SmallVector<CCValAssign, 16> RVLocs;
1329 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
1330 RVLocs, *DAG.getContext());
1331 CCRetInfo.AnalyzeCallResult(Ins, CCC_SPU);
1334 // If the call has results, copy the values out of the ret val registers.
1335 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1336 CCValAssign VA = RVLocs[i];
1338 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1340 Chain = Val.getValue(1);
1341 InFlag = Val.getValue(2);
1342 InVals.push_back(Val);
1349 SPUTargetLowering::LowerReturn(SDValue Chain,
1350 CallingConv::ID CallConv, bool isVarArg,
1351 const SmallVectorImpl<ISD::OutputArg> &Outs,
1352 const SmallVectorImpl<SDValue> &OutVals,
1353 DebugLoc dl, SelectionDAG &DAG) const {
1355 SmallVector<CCValAssign, 16> RVLocs;
1356 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1357 RVLocs, *DAG.getContext());
1358 CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
1360 // If this is the first return lowered for this function, add the regs to the
1361 // liveout set for the function.
1362 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1363 for (unsigned i = 0; i != RVLocs.size(); ++i)
1364 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1369 // Copy the result values into the output registers.
1370 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1371 CCValAssign &VA = RVLocs[i];
1372 assert(VA.isRegLoc() && "Can only return in registers!");
1373 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1375 Flag = Chain.getValue(1);
1379 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1381 return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain);
1385 //===----------------------------------------------------------------------===//
1386 // Vector related lowering:
1387 //===----------------------------------------------------------------------===//
1389 static ConstantSDNode *
1390 getVecImm(SDNode *N) {
1391 SDValue OpVal(0, 0);
1393 // Check to see if this buildvec has a single non-undef value in its elements.
1394 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1395 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1396 if (OpVal.getNode() == 0)
1397 OpVal = N->getOperand(i);
1398 else if (OpVal != N->getOperand(i))
1402 if (OpVal.getNode() != 0) {
1403 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1411 /// get_vec_i18imm - Test if this vector is a vector filled with the same value
1412 /// and the value fits into an unsigned 18-bit constant, and if so, return the
1414 SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
1416 if (ConstantSDNode *CN = getVecImm(N)) {
1417 uint64_t Value = CN->getZExtValue();
1418 if (ValueType == MVT::i64) {
1419 uint64_t UValue = CN->getZExtValue();
1420 uint32_t upper = uint32_t(UValue >> 32);
1421 uint32_t lower = uint32_t(UValue);
1424 Value = Value >> 32;
1426 if (Value <= 0x3ffff)
1427 return DAG.getTargetConstant(Value, ValueType);
1433 /// get_vec_i16imm - Test if this vector is a vector filled with the same value
1434 /// and the value fits into a signed 16-bit constant, and if so, return the
1436 SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
1438 if (ConstantSDNode *CN = getVecImm(N)) {
1439 int64_t Value = CN->getSExtValue();
1440 if (ValueType == MVT::i64) {
1441 uint64_t UValue = CN->getZExtValue();
1442 uint32_t upper = uint32_t(UValue >> 32);
1443 uint32_t lower = uint32_t(UValue);
1446 Value = Value >> 32;
1448 if (Value >= -(1 << 15) && Value <= ((1 << 15) - 1)) {
1449 return DAG.getTargetConstant(Value, ValueType);
1456 /// get_vec_i10imm - Test if this vector is a vector filled with the same value
1457 /// and the value fits into a signed 10-bit constant, and if so, return the
1459 SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
1461 if (ConstantSDNode *CN = getVecImm(N)) {
1462 int64_t Value = CN->getSExtValue();
1463 if (ValueType == MVT::i64) {
1464 uint64_t UValue = CN->getZExtValue();
1465 uint32_t upper = uint32_t(UValue >> 32);
1466 uint32_t lower = uint32_t(UValue);
1469 Value = Value >> 32;
1471 if (isInt<10>(Value))
1472 return DAG.getTargetConstant(Value, ValueType);
1478 /// get_vec_i8imm - Test if this vector is a vector filled with the same value
1479 /// and the value fits into a signed 8-bit constant, and if so, return the
1482 /// @note: The incoming vector is v16i8 because that's the only way we can load
1483 /// constant vectors. Thus, we test to see if the upper and lower bytes are the
1485 SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
1487 if (ConstantSDNode *CN = getVecImm(N)) {
1488 int Value = (int) CN->getZExtValue();
1489 if (ValueType == MVT::i16
1490 && Value <= 0xffff /* truncated from uint64_t */
1491 && ((short) Value >> 8) == ((short) Value & 0xff))
1492 return DAG.getTargetConstant(Value & 0xff, ValueType);
1493 else if (ValueType == MVT::i8
1494 && (Value & 0xff) == Value)
1495 return DAG.getTargetConstant(Value, ValueType);
1501 /// get_ILHUvec_imm - Test if this vector is a vector filled with the same value
1502 /// and the value fits into a signed 16-bit constant, and if so, return the
1504 SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
1506 if (ConstantSDNode *CN = getVecImm(N)) {
1507 uint64_t Value = CN->getZExtValue();
1508 if ((ValueType == MVT::i32
1509 && ((unsigned) Value & 0xffff0000) == (unsigned) Value)
1510 || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value))
1511 return DAG.getTargetConstant(Value >> 16, ValueType);
1517 /// get_v4i32_imm - Catch-all for general 32-bit constant vectors
1518 SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) {
1519 if (ConstantSDNode *CN = getVecImm(N)) {
1520 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32);
1526 /// get_v4i32_imm - Catch-all for general 64-bit constant vectors
1527 SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) {
1528 if (ConstantSDNode *CN = getVecImm(N)) {
1529 return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64);
1535 //! Lower a BUILD_VECTOR instruction creatively:
1537 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
1538 EVT VT = Op.getValueType();
1539 EVT EltVT = VT.getVectorElementType();
1540 DebugLoc dl = Op.getDebugLoc();
1541 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(Op.getNode());
1542 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR");
1543 unsigned minSplatBits = EltVT.getSizeInBits();
1545 if (minSplatBits < 16)
1548 APInt APSplatBits, APSplatUndef;
1549 unsigned SplatBitSize;
1552 if (!BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
1553 HasAnyUndefs, minSplatBits)
1554 || minSplatBits < SplatBitSize)
1555 return SDValue(); // Wasn't a constant vector or splat exceeded min
1557 uint64_t SplatBits = APSplatBits.getZExtValue();
1559 switch (VT.getSimpleVT().SimpleTy) {
1561 report_fatal_error("CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " +
1562 Twine(VT.getEVTString()));
1565 uint32_t Value32 = uint32_t(SplatBits);
1566 assert(SplatBitSize == 32
1567 && "LowerBUILD_VECTOR: Unexpected floating point vector element.");
1568 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1569 SDValue T = DAG.getConstant(Value32, MVT::i32);
1570 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,
1571 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T));
1575 uint64_t f64val = uint64_t(SplatBits);
1576 assert(SplatBitSize == 64
1577 && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes.");
1578 // NOTE: pretend the constant is an integer. LLVM won't load FP constants
1579 SDValue T = DAG.getConstant(f64val, MVT::i64);
1580 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64,
1581 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T));
1585 // 8-bit constants have to be expanded to 16-bits
1586 unsigned short Value16 = SplatBits /* | (SplatBits << 8) */;
1587 SmallVector<SDValue, 8> Ops;
1589 Ops.assign(8, DAG.getConstant(Value16, MVT::i16));
1590 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
1591 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
1594 unsigned short Value16 = SplatBits;
1595 SDValue T = DAG.getConstant(Value16, EltVT);
1596 SmallVector<SDValue, 8> Ops;
1599 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1602 SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
1603 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
1606 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
1616 SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
1618 uint32_t upper = uint32_t(SplatVal >> 32);
1619 uint32_t lower = uint32_t(SplatVal);
1621 if (upper == lower) {
1622 // Magic constant that can be matched by IL, ILA, et. al.
1623 SDValue Val = DAG.getTargetConstant(upper, MVT::i32);
1624 return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1625 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1626 Val, Val, Val, Val));
1628 bool upper_special, lower_special;
1630 // NOTE: This code creates common-case shuffle masks that can be easily
1631 // detected as common expressions. It is not attempting to create highly
1632 // specialized masks to replace any and all 0's, 0xff's and 0x80's.
1634 // Detect if the upper or lower half is a special shuffle mask pattern:
1635 upper_special = (upper == 0 || upper == 0xffffffff || upper == 0x80000000);
1636 lower_special = (lower == 0 || lower == 0xffffffff || lower == 0x80000000);
1638 // Both upper and lower are special, lower to a constant pool load:
1639 if (lower_special && upper_special) {
1640 SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
1641 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
1642 SplatValCN, SplatValCN);
1647 SmallVector<SDValue, 16> ShufBytes;
1650 // Create lower vector if not a special pattern
1651 if (!lower_special) {
1652 SDValue LO32C = DAG.getConstant(lower, MVT::i32);
1653 LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1654 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1655 LO32C, LO32C, LO32C, LO32C));
1658 // Create upper vector if not a special pattern
1659 if (!upper_special) {
1660 SDValue HI32C = DAG.getConstant(upper, MVT::i32);
1661 HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT,
1662 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1663 HI32C, HI32C, HI32C, HI32C));
1666 // If either upper or lower are special, then the two input operands are
1667 // the same (basically, one of them is a "don't care")
1673 for (int i = 0; i < 4; ++i) {
1675 for (int j = 0; j < 4; ++j) {
1677 bool process_upper, process_lower;
1679 process_upper = (upper_special && (i & 1) == 0);
1680 process_lower = (lower_special && (i & 1) == 1);
1682 if (process_upper || process_lower) {
1683 if ((process_upper && upper == 0)
1684 || (process_lower && lower == 0))
1686 else if ((process_upper && upper == 0xffffffff)
1687 || (process_lower && lower == 0xffffffff))
1689 else if ((process_upper && upper == 0x80000000)
1690 || (process_lower && lower == 0x80000000))
1691 val |= (j == 0 ? 0xe0 : 0x80);
1693 val |= i * 4 + j + ((i & 1) * 16);
1696 ShufBytes.push_back(DAG.getConstant(val, MVT::i32));
1699 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32,
1700 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1701 &ShufBytes[0], ShufBytes.size()));
1705 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1706 /// which the Cell can operate. The code inspects V3 to ascertain whether the
1707 /// permutation vector, V3, is monotonically increasing with one "exception"
1708 /// element, e.g., (0, 1, _, 3). If this is the case, then generate a
1709 /// SHUFFLE_MASK synthetic instruction. Otherwise, spill V3 to the constant pool.
1710 /// In either case, the net result is going to eventually invoke SHUFB to
1711 /// permute/shuffle the bytes from V1 and V2.
1713 /// SHUFFLE_MASK is eventually selected as one of the C*D instructions, generate
1714 /// control word for byte/halfword/word insertion. This takes care of a single
1715 /// element move from V2 into V1.
1717 /// SPUISD::SHUFB is eventually selected as Cell's <i>shufb</i> instructions.
1718 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
1719 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
1720 SDValue V1 = Op.getOperand(0);
1721 SDValue V2 = Op.getOperand(1);
1722 DebugLoc dl = Op.getDebugLoc();
1724 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1726 // If we have a single element being moved from V1 to V2, this can be handled
1727 // using the C*[DX] compute mask instructions, but the vector elements have
1728 // to be monotonically increasing with one exception element, and the source
1729 // slot of the element to move must be the same as the destination.
1730 EVT VecVT = V1.getValueType();
1731 EVT EltVT = VecVT.getVectorElementType();
1732 unsigned EltsFromV2 = 0;
1733 unsigned V2EltOffset = 0;
1734 unsigned V2EltIdx0 = 0;
1735 unsigned CurrElt = 0;
1736 unsigned MaxElts = VecVT.getVectorNumElements();
1737 unsigned PrevElt = 0;
1738 bool monotonic = true;
1741 EVT maskVT; // which of the c?d instructions to use
1743 if (EltVT == MVT::i8) {
1745 maskVT = MVT::v16i8;
1746 } else if (EltVT == MVT::i16) {
1748 maskVT = MVT::v8i16;
1749 } else if (EltVT == MVT::i32 || EltVT == MVT::f32) {
1751 maskVT = MVT::v4i32;
1752 } else if (EltVT == MVT::i64 || EltVT == MVT::f64) {
1754 maskVT = MVT::v2i64;
1756 llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE");
1758 for (unsigned i = 0; i != MaxElts; ++i) {
1759 if (SVN->getMaskElt(i) < 0)
1762 unsigned SrcElt = SVN->getMaskElt(i);
1765 if (SrcElt >= V2EltIdx0) {
1766 // TODO: optimize for the monotonic case when several consecutive
1767 // elements are taken form V2. Do we ever get such a case?
1768 if (EltsFromV2 == 0 && CurrElt == (SrcElt - V2EltIdx0))
1769 V2EltOffset = (SrcElt - V2EltIdx0) * (EltVT.getSizeInBits()/8);
1773 } else if (CurrElt != SrcElt) {
1781 if (PrevElt > 0 && SrcElt < MaxElts) {
1782 if ((PrevElt == SrcElt - 1)
1783 || (PrevElt == MaxElts - 1 && SrcElt == 0)) {
1789 } else if (i == 0 || (PrevElt==0 && SrcElt==1)) {
1790 // First time or after a "wrap around"
1793 // This isn't a rotation, takes elements from vector 2
1799 if (EltsFromV2 == 1 && monotonic) {
1800 // Compute mask and shuffle
1801 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1803 // As SHUFFLE_MASK becomes a c?d instruction, feed it an address
1804 // R1 ($sp) is used here only as it is guaranteed to have last bits zero
1805 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
1806 DAG.getRegister(SPU::R1, PtrVT),
1807 DAG.getConstant(V2EltOffset, MVT::i32));
1808 SDValue ShufMaskOp = DAG.getNode(SPUISD::SHUFFLE_MASK, dl,
1811 // Use shuffle mask in SHUFB synthetic instruction:
1812 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
1814 } else if (rotate) {
1817 rotamt *= EltVT.getSizeInBits()/8;
1818 return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
1819 V1, DAG.getConstant(rotamt, MVT::i16));
1821 // Convert the SHUFFLE_VECTOR mask's input element units to the
1823 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
1825 SmallVector<SDValue, 16> ResultMask;
1826 for (unsigned i = 0, e = MaxElts; i != e; ++i) {
1827 unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i);
1829 for (unsigned j = 0; j < BytesPerElement; ++j)
1830 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8));
1832 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
1833 &ResultMask[0], ResultMask.size());
1834 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask);
1838 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
1839 SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
1840 DebugLoc dl = Op.getDebugLoc();
1842 if (Op0.getNode()->getOpcode() == ISD::Constant) {
1843 // For a constant, build the appropriate constant vector, which will
1844 // eventually simplify to a vector register load.
1846 ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
1847 SmallVector<SDValue, 16> ConstVecValues;
1851 // Create a constant vector:
1852 switch (Op.getValueType().getSimpleVT().SimpleTy) {
1853 default: llvm_unreachable("Unexpected constant value type in "
1854 "LowerSCALAR_TO_VECTOR");
1855 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1856 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1857 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1858 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1859 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1860 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1863 SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
1864 for (size_t j = 0; j < n_copies; ++j)
1865 ConstVecValues.push_back(CValue);
1867 return DAG.getNode(ISD::BUILD_VECTOR, dl, Op.getValueType(),
1868 &ConstVecValues[0], ConstVecValues.size());
1870 // Otherwise, copy the value from one register to another:
1871 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
1872 default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR");
1879 return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0);
1886 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
1887 EVT VT = Op.getValueType();
1888 SDValue N = Op.getOperand(0);
1889 SDValue Elt = Op.getOperand(1);
1890 DebugLoc dl = Op.getDebugLoc();
1893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1894 // Constant argument:
1895 int EltNo = (int) C->getZExtValue();
1898 if (VT == MVT::i8 && EltNo >= 16)
1899 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15");
1900 else if (VT == MVT::i16 && EltNo >= 8)
1901 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7");
1902 else if (VT == MVT::i32 && EltNo >= 4)
1903 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4");
1904 else if (VT == MVT::i64 && EltNo >= 2)
1905 llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2");
1907 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
1908 // i32 and i64: Element 0 is the preferred slot
1909 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
1912 // Need to generate shuffle mask and extract:
1913 int prefslot_begin = -1, prefslot_end = -1;
1914 int elt_byte = EltNo * VT.getSizeInBits() / 8;
1916 switch (VT.getSimpleVT().SimpleTy) {
1918 assert(false && "Invalid value type!");
1920 prefslot_begin = prefslot_end = 3;
1924 prefslot_begin = 2; prefslot_end = 3;
1929 prefslot_begin = 0; prefslot_end = 3;
1934 prefslot_begin = 0; prefslot_end = 7;
1939 assert(prefslot_begin != -1 && prefslot_end != -1 &&
1940 "LowerEXTRACT_VECTOR_ELT: preferred slots uninitialized");
1942 unsigned int ShufBytes[16] = {
1943 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1945 for (int i = 0; i < 16; ++i) {
1946 // zero fill uppper part of preferred slot, don't care about the
1948 unsigned int mask_val;
1949 if (i <= prefslot_end) {
1951 ((i < prefslot_begin)
1953 : elt_byte + (i - prefslot_begin));
1955 ShufBytes[i] = mask_val;
1957 ShufBytes[i] = ShufBytes[i % (prefslot_end + 1)];
1960 SDValue ShufMask[4];
1961 for (unsigned i = 0; i < sizeof(ShufMask)/sizeof(ShufMask[0]); ++i) {
1962 unsigned bidx = i * 4;
1963 unsigned int bits = ((ShufBytes[bidx] << 24) |
1964 (ShufBytes[bidx+1] << 16) |
1965 (ShufBytes[bidx+2] << 8) |
1967 ShufMask[i] = DAG.getConstant(bits, MVT::i32);
1970 SDValue ShufMaskVec =
1971 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
1972 &ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0]));
1974 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
1975 DAG.getNode(SPUISD::SHUFB, dl, N.getValueType(),
1976 N, N, ShufMaskVec));
1978 // Variable index: Rotate the requested element into slot 0, then replicate
1979 // slot 0 across the vector
1980 EVT VecVT = N.getValueType();
1981 if (!VecVT.isSimple() || !VecVT.isVector()) {
1982 report_fatal_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit"
1986 // Make life easier by making sure the index is zero-extended to i32
1987 if (Elt.getValueType() != MVT::i32)
1988 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt);
1990 // Scale the index to a bit/byte shift quantity
1992 APInt(32, uint64_t(16 / N.getValueType().getVectorNumElements()), false);
1993 unsigned scaleShift = scaleFactor.logBase2();
1996 if (scaleShift > 0) {
1997 // Scale the shift factor:
1998 Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt,
1999 DAG.getConstant(scaleShift, MVT::i32));
2002 vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt);
2004 // Replicate the bytes starting at byte 0 across the entire vector (for
2005 // consistency with the notion of a unified register set)
2008 switch (VT.getSimpleVT().SimpleTy) {
2010 report_fatal_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector"
2014 SDValue factor = DAG.getConstant(0x00000000, MVT::i32);
2015 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2016 factor, factor, factor, factor);
2020 SDValue factor = DAG.getConstant(0x00010001, MVT::i32);
2021 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2022 factor, factor, factor, factor);
2027 SDValue factor = DAG.getConstant(0x00010203, MVT::i32);
2028 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2029 factor, factor, factor, factor);
2034 SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32);
2035 SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32);
2036 replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2037 loFactor, hiFactor, loFactor, hiFactor);
2042 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2043 DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2044 vecShift, vecShift, replicate));
2050 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2051 SDValue VecOp = Op.getOperand(0);
2052 SDValue ValOp = Op.getOperand(1);
2053 SDValue IdxOp = Op.getOperand(2);
2054 DebugLoc dl = Op.getDebugLoc();
2055 EVT VT = Op.getValueType();
2056 EVT eltVT = ValOp.getValueType();
2058 // use 0 when the lane to insert to is 'undef'
2060 if (IdxOp.getOpcode() != ISD::UNDEF) {
2061 ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
2062 assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
2063 Offset = (CN->getSExtValue()) * eltVT.getSizeInBits()/8;
2066 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2067 // Use $sp ($1) because it's always 16-byte aligned and it's available:
2068 SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
2069 DAG.getRegister(SPU::R1, PtrVT),
2070 DAG.getConstant(Offset, PtrVT));
2071 // widen the mask when dealing with half vectors
2072 EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(),
2073 128/ VT.getVectorElementType().getSizeInBits());
2074 SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, maskVT, Pointer);
2077 DAG.getNode(SPUISD::SHUFB, dl, VT,
2078 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
2080 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask));
2085 static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc,
2086 const TargetLowering &TLI)
2088 SDValue N0 = Op.getOperand(0); // Everything has at least one operand
2089 DebugLoc dl = Op.getDebugLoc();
2090 EVT ShiftVT = TLI.getShiftAmountTy();
2092 assert(Op.getValueType() == MVT::i8);
2095 llvm_unreachable("Unhandled i8 math operator");
2099 // 8-bit addition: Promote the arguments up to 16-bits and truncate
2101 SDValue N1 = Op.getOperand(1);
2102 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2103 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2104 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2105 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2110 // 8-bit subtraction: Promote the arguments up to 16-bits and truncate
2112 SDValue N1 = Op.getOperand(1);
2113 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2114 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2115 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2116 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2120 SDValue N1 = Op.getOperand(1);
2121 EVT N1VT = N1.getValueType();
2123 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2124 if (!N1VT.bitsEq(ShiftVT)) {
2125 unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT)
2128 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2131 // Replicate lower 8-bits into upper 8:
2133 DAG.getNode(ISD::OR, dl, MVT::i16, N0,
2134 DAG.getNode(ISD::SHL, dl, MVT::i16,
2135 N0, DAG.getConstant(8, MVT::i32)));
2137 // Truncate back down to i8
2138 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2139 DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1));
2143 SDValue N1 = Op.getOperand(1);
2144 EVT N1VT = N1.getValueType();
2146 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0);
2147 if (!N1VT.bitsEq(ShiftVT)) {
2148 unsigned N1Opc = ISD::ZERO_EXTEND;
2150 if (N1.getValueType().bitsGT(ShiftVT))
2151 N1Opc = ISD::TRUNCATE;
2153 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2156 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2157 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2160 SDValue N1 = Op.getOperand(1);
2161 EVT N1VT = N1.getValueType();
2163 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2164 if (!N1VT.bitsEq(ShiftVT)) {
2165 unsigned N1Opc = ISD::SIGN_EXTEND;
2167 if (N1VT.bitsGT(ShiftVT))
2168 N1Opc = ISD::TRUNCATE;
2169 N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1);
2172 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2173 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2176 SDValue N1 = Op.getOperand(1);
2178 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0);
2179 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1);
2180 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8,
2181 DAG.getNode(Opc, dl, MVT::i16, N0, N1));
2189 //! Lower byte immediate operations for v16i8 vectors:
2191 LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
2194 EVT VT = Op.getValueType();
2195 DebugLoc dl = Op.getDebugLoc();
2197 ConstVec = Op.getOperand(0);
2198 Arg = Op.getOperand(1);
2199 if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
2200 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2201 ConstVec = ConstVec.getOperand(0);
2203 ConstVec = Op.getOperand(1);
2204 Arg = Op.getOperand(0);
2205 if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
2206 ConstVec = ConstVec.getOperand(0);
2211 if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
2212 BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(ConstVec.getNode());
2213 assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerByteImmed");
2215 APInt APSplatBits, APSplatUndef;
2216 unsigned SplatBitSize;
2218 unsigned minSplatBits = VT.getVectorElementType().getSizeInBits();
2220 if (BCN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2221 HasAnyUndefs, minSplatBits)
2222 && minSplatBits <= SplatBitSize) {
2223 uint64_t SplatBits = APSplatBits.getZExtValue();
2224 SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8);
2226 SmallVector<SDValue, 16> tcVec;
2227 tcVec.assign(16, tc);
2228 return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
2229 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &tcVec[0], tcVec.size()));
2233 // These operations (AND, OR, XOR) are legal, they just couldn't be custom
2234 // lowered. Return the operation, rather than a null SDValue.
2238 //! Custom lowering for CTPOP (count population)
2240 Custom lowering code that counts the number ones in the input
2241 operand. SPU has such an instruction, but it counts the number of
2242 ones per byte, which then have to be accumulated.
2244 static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
2245 EVT VT = Op.getValueType();
2246 EVT vecVT = EVT::getVectorVT(*DAG.getContext(),
2247 VT, (128 / VT.getSizeInBits()));
2248 DebugLoc dl = Op.getDebugLoc();
2250 switch (VT.getSimpleVT().SimpleTy) {
2252 assert(false && "Invalid value type!");
2254 SDValue N = Op.getOperand(0);
2255 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2257 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2258 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2260 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0);
2264 MachineFunction &MF = DAG.getMachineFunction();
2265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2267 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
2269 SDValue N = Op.getOperand(0);
2270 SDValue Elt0 = DAG.getConstant(0, MVT::i16);
2271 SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16);
2272 SDValue Shift1 = DAG.getConstant(8, MVT::i32);
2274 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2275 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2277 // CNTB_result becomes the chain to which all of the virtual registers
2278 // CNTB_reg, SUM1_reg become associated:
2279 SDValue CNTB_result =
2280 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0);
2282 SDValue CNTB_rescopy =
2283 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2285 SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16);
2287 return DAG.getNode(ISD::AND, dl, MVT::i16,
2288 DAG.getNode(ISD::ADD, dl, MVT::i16,
2289 DAG.getNode(ISD::SRL, dl, MVT::i16,
2296 MachineFunction &MF = DAG.getMachineFunction();
2297 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2299 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2300 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2302 SDValue N = Op.getOperand(0);
2303 SDValue Elt0 = DAG.getConstant(0, MVT::i32);
2304 SDValue Mask0 = DAG.getConstant(0xff, MVT::i32);
2305 SDValue Shift1 = DAG.getConstant(16, MVT::i32);
2306 SDValue Shift2 = DAG.getConstant(8, MVT::i32);
2308 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N);
2309 SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote);
2311 // CNTB_result becomes the chain to which all of the virtual registers
2312 // CNTB_reg, SUM1_reg become associated:
2313 SDValue CNTB_result =
2314 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0);
2316 SDValue CNTB_rescopy =
2317 DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result);
2320 DAG.getNode(ISD::SRL, dl, MVT::i32,
2321 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32),
2325 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1,
2326 DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32));
2328 SDValue Sum1_rescopy =
2329 DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1);
2332 DAG.getNode(ISD::SRL, dl, MVT::i32,
2333 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32),
2336 DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2,
2337 DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32));
2339 return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0);
2349 //! Lower ISD::FP_TO_SINT, ISD::FP_TO_UINT for i32
2351 f32->i32 passes through unchanged, whereas f64->i32 expands to a libcall.
2352 All conversions to i64 are expanded to a libcall.
2354 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2355 const SPUTargetLowering &TLI) {
2356 EVT OpVT = Op.getValueType();
2357 SDValue Op0 = Op.getOperand(0);
2358 EVT Op0VT = Op0.getValueType();
2360 if ((OpVT == MVT::i32 && Op0VT == MVT::f64)
2361 || OpVT == MVT::i64) {
2362 // Convert f32 / f64 to i32 / i64 via libcall.
2364 (Op.getOpcode() == ISD::FP_TO_SINT)
2365 ? RTLIB::getFPTOSINT(Op0VT, OpVT)
2366 : RTLIB::getFPTOUINT(Op0VT, OpVT);
2367 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
2369 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2375 //! Lower ISD::SINT_TO_FP, ISD::UINT_TO_FP for i32
2377 i32->f32 passes through unchanged, whereas i32->f64 is expanded to a libcall.
2378 All conversions from i64 are expanded to a libcall.
2380 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2381 const SPUTargetLowering &TLI) {
2382 EVT OpVT = Op.getValueType();
2383 SDValue Op0 = Op.getOperand(0);
2384 EVT Op0VT = Op0.getValueType();
2386 if ((OpVT == MVT::f64 && Op0VT == MVT::i32)
2387 || Op0VT == MVT::i64) {
2388 // Convert i32, i64 to f64 via libcall:
2390 (Op.getOpcode() == ISD::SINT_TO_FP)
2391 ? RTLIB::getSINTTOFP(Op0VT, OpVT)
2392 : RTLIB::getUINTTOFP(Op0VT, OpVT);
2393 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd int-to-fp conversion!");
2395 return ExpandLibCall(LC, Op, DAG, false, Dummy, TLI);
2401 //! Lower ISD::SETCC
2403 This handles MVT::f64 (double floating point) condition lowering
2405 static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG,
2406 const TargetLowering &TLI) {
2407 CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2));
2408 DebugLoc dl = Op.getDebugLoc();
2409 assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n");
2411 SDValue lhs = Op.getOperand(0);
2412 SDValue rhs = Op.getOperand(1);
2413 EVT lhsVT = lhs.getValueType();
2414 assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n");
2416 EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType());
2417 APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2418 EVT IntVT(MVT::i64);
2420 // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently
2421 // selected to a NOP:
2422 SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs);
2424 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2425 DAG.getNode(ISD::SRL, dl, IntVT,
2426 i64lhs, DAG.getConstant(32, MVT::i32)));
2427 SDValue lhsHi32abs =
2428 DAG.getNode(ISD::AND, dl, MVT::i32,
2429 lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32));
2431 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs);
2433 // SETO and SETUO only use the lhs operand:
2434 if (CC->get() == ISD::SETO) {
2435 // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of
2437 APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits());
2438 return DAG.getNode(ISD::XOR, dl, ccResultVT,
2439 DAG.getSetCC(dl, ccResultVT,
2440 lhs, DAG.getConstantFP(0.0, lhsVT),
2442 DAG.getConstant(ccResultAllOnes, ccResultVT));
2443 } else if (CC->get() == ISD::SETUO) {
2444 // Evaluates to true if Op0 is [SQ]NaN
2445 return DAG.getNode(ISD::AND, dl, ccResultVT,
2446 DAG.getSetCC(dl, ccResultVT,
2448 DAG.getConstant(0x7ff00000, MVT::i32),
2450 DAG.getSetCC(dl, ccResultVT,
2452 DAG.getConstant(0, MVT::i32),
2456 SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs);
2458 DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
2459 DAG.getNode(ISD::SRL, dl, IntVT,
2460 i64rhs, DAG.getConstant(32, MVT::i32)));
2462 // If a value is negative, subtract from the sign magnitude constant:
2463 SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT);
2465 // Convert the sign-magnitude representation into 2's complement:
2466 SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2467 lhsHi32, DAG.getConstant(31, MVT::i32));
2468 SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs);
2470 DAG.getNode(ISD::SELECT, dl, IntVT,
2471 lhsSelectMask, lhsSignMag2TC, i64lhs);
2473 SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT,
2474 rhsHi32, DAG.getConstant(31, MVT::i32));
2475 SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs);
2477 DAG.getNode(ISD::SELECT, dl, IntVT,
2478 rhsSelectMask, rhsSignMag2TC, i64rhs);
2482 switch (CC->get()) {
2485 compareOp = ISD::SETEQ; break;
2488 compareOp = ISD::SETGT; break;
2491 compareOp = ISD::SETGE; break;
2494 compareOp = ISD::SETLT; break;
2497 compareOp = ISD::SETLE; break;
2500 compareOp = ISD::SETNE; break;
2502 report_fatal_error("CellSPU ISel Select: unimplemented f64 condition");
2506 DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect,
2507 (ISD::CondCode) compareOp);
2509 if ((CC->get() & 0x8) == 0) {
2510 // Ordered comparison:
2511 SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT,
2512 lhs, DAG.getConstantFP(0.0, MVT::f64),
2514 SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT,
2515 rhs, DAG.getConstantFP(0.0, MVT::f64),
2517 SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN);
2519 result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result);
2525 //! Lower ISD::SELECT_CC
2527 ISD::SELECT_CC can (generally) be implemented directly on the SPU using the
2530 \note Need to revisit this in the future: if the code path through the true
2531 and false value computations is longer than the latency of a branch (6
2532 cycles), then it would be more advantageous to branch and insert a new basic
2533 block and branch on the condition. However, this code does not make that
2534 assumption, given the simplisitc uses so far.
2537 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2538 const TargetLowering &TLI) {
2539 EVT VT = Op.getValueType();
2540 SDValue lhs = Op.getOperand(0);
2541 SDValue rhs = Op.getOperand(1);
2542 SDValue trueval = Op.getOperand(2);
2543 SDValue falseval = Op.getOperand(3);
2544 SDValue condition = Op.getOperand(4);
2545 DebugLoc dl = Op.getDebugLoc();
2547 // NOTE: SELB's arguments: $rA, $rB, $mask
2549 // SELB selects bits from $rA where bits in $mask are 0, bits from $rB
2550 // where bits in $mask are 1. CCond will be inverted, having 1s where the
2551 // condition was true and 0s where the condition was false. Hence, the
2552 // arguments to SELB get reversed.
2554 // Note: Really should be ISD::SELECT instead of SPUISD::SELB, but LLVM's
2555 // legalizer insists on combining SETCC/SELECT into SELECT_CC, so we end up
2556 // with another "cannot select select_cc" assert:
2558 SDValue compare = DAG.getNode(ISD::SETCC, dl,
2559 TLI.getSetCCResultType(Op.getValueType()),
2560 lhs, rhs, condition);
2561 return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare);
2564 //! Custom lower ISD::TRUNCATE
2565 static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG)
2567 // Type to truncate to
2568 EVT VT = Op.getValueType();
2569 MVT simpleVT = VT.getSimpleVT();
2570 EVT VecVT = EVT::getVectorVT(*DAG.getContext(),
2571 VT, (128 / VT.getSizeInBits()));
2572 DebugLoc dl = Op.getDebugLoc();
2574 // Type to truncate from
2575 SDValue Op0 = Op.getOperand(0);
2576 EVT Op0VT = Op0.getValueType();
2578 if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) {
2579 // Create shuffle mask, least significant doubleword of quadword
2580 unsigned maskHigh = 0x08090a0b;
2581 unsigned maskLow = 0x0c0d0e0f;
2582 // Use a shuffle to perform the truncation
2583 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2584 DAG.getConstant(maskHigh, MVT::i32),
2585 DAG.getConstant(maskLow, MVT::i32),
2586 DAG.getConstant(maskHigh, MVT::i32),
2587 DAG.getConstant(maskLow, MVT::i32));
2589 SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT,
2590 Op0, Op0, shufMask);
2592 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle);
2595 return SDValue(); // Leave the truncate unmolested
2599 * Emit the instruction sequence for i64/i32 -> i128 sign extend. The basic
2600 * algorithm is to duplicate the sign bit using rotmai to generate at
2601 * least one byte full of sign bits. Then propagate the "sign-byte" into
2602 * the leftmost words and the i64/i32 into the rightmost words using shufb.
2604 * @param Op The sext operand
2605 * @param DAG The current DAG
2606 * @return The SDValue with the entire instruction sequence
2608 static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
2610 DebugLoc dl = Op.getDebugLoc();
2612 // Type to extend to
2613 MVT OpVT = Op.getValueType().getSimpleVT();
2615 // Type to extend from
2616 SDValue Op0 = Op.getOperand(0);
2617 MVT Op0VT = Op0.getValueType().getSimpleVT();
2619 // The type to extend to needs to be a i128 and
2620 // the type to extend from needs to be i64 or i32.
2621 assert((OpVT == MVT::i128 && (Op0VT == MVT::i64 || Op0VT == MVT::i32)) &&
2622 "LowerSIGN_EXTEND: input and/or output operand have wrong size");
2624 // Create shuffle mask
2625 unsigned mask1 = 0x10101010; // byte 0 - 3 and 4 - 7
2626 unsigned mask2 = Op0VT == MVT::i64 ? 0x00010203 : 0x10101010; // byte 8 - 11
2627 unsigned mask3 = Op0VT == MVT::i64 ? 0x04050607 : 0x00010203; // byte 12 - 15
2628 SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
2629 DAG.getConstant(mask1, MVT::i32),
2630 DAG.getConstant(mask1, MVT::i32),
2631 DAG.getConstant(mask2, MVT::i32),
2632 DAG.getConstant(mask3, MVT::i32));
2634 // Word wise arithmetic right shift to generate at least one byte
2635 // that contains sign bits.
2636 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32;
2637 SDValue sraVal = DAG.getNode(ISD::SRA,
2640 DAG.getNode(SPUISD::PREFSLOT2VEC, dl, mvt, Op0, Op0),
2641 DAG.getConstant(31, MVT::i32));
2643 // Shuffle bytes - Copy the sign bits into the upper 64 bits
2644 // and the input value into the lower 64 bits.
2645 SDValue extShuffle = DAG.getNode(SPUISD::SHUFB, dl, mvt,
2646 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i128, Op0), sraVal, shufMask);
2648 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i128, extShuffle);
2651 //! Custom (target-specific) lowering entry point
2653 This is where LLVM's DAG selection process calls to do target-specific
2657 SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
2659 unsigned Opc = (unsigned) Op.getOpcode();
2660 EVT VT = Op.getValueType();
2665 errs() << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
2666 errs() << "Op.getOpcode() = " << Opc << "\n";
2667 errs() << "*Op.getNode():\n";
2668 Op.getNode()->dump();
2670 llvm_unreachable(0);
2676 return LowerLOAD(Op, DAG, SPUTM.getSubtargetImpl());
2678 return LowerSTORE(Op, DAG, SPUTM.getSubtargetImpl());
2679 case ISD::ConstantPool:
2680 return LowerConstantPool(Op, DAG, SPUTM.getSubtargetImpl());
2681 case ISD::GlobalAddress:
2682 return LowerGlobalAddress(Op, DAG, SPUTM.getSubtargetImpl());
2683 case ISD::JumpTable:
2684 return LowerJumpTable(Op, DAG, SPUTM.getSubtargetImpl());
2685 case ISD::ConstantFP:
2686 return LowerConstantFP(Op, DAG);
2688 // i8, i64 math ops:
2697 return LowerI8Math(Op, DAG, Opc, *this);
2701 case ISD::FP_TO_SINT:
2702 case ISD::FP_TO_UINT:
2703 return LowerFP_TO_INT(Op, DAG, *this);
2705 case ISD::SINT_TO_FP:
2706 case ISD::UINT_TO_FP:
2707 return LowerINT_TO_FP(Op, DAG, *this);
2709 // Vector-related lowering.
2710 case ISD::BUILD_VECTOR:
2711 return LowerBUILD_VECTOR(Op, DAG);
2712 case ISD::SCALAR_TO_VECTOR:
2713 return LowerSCALAR_TO_VECTOR(Op, DAG);
2714 case ISD::VECTOR_SHUFFLE:
2715 return LowerVECTOR_SHUFFLE(Op, DAG);
2716 case ISD::EXTRACT_VECTOR_ELT:
2717 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2718 case ISD::INSERT_VECTOR_ELT:
2719 return LowerINSERT_VECTOR_ELT(Op, DAG);
2721 // Look for ANDBI, ORBI and XORBI opportunities and lower appropriately:
2725 return LowerByteImmed(Op, DAG);
2727 // Vector and i8 multiply:
2730 return LowerI8Math(Op, DAG, Opc, *this);
2733 return LowerCTPOP(Op, DAG);
2735 case ISD::SELECT_CC:
2736 return LowerSELECT_CC(Op, DAG, *this);
2739 return LowerSETCC(Op, DAG, *this);
2742 return LowerTRUNCATE(Op, DAG);
2744 case ISD::SIGN_EXTEND:
2745 return LowerSIGN_EXTEND(Op, DAG);
2751 void SPUTargetLowering::ReplaceNodeResults(SDNode *N,
2752 SmallVectorImpl<SDValue>&Results,
2753 SelectionDAG &DAG) const
2756 unsigned Opc = (unsigned) N->getOpcode();
2757 EVT OpVT = N->getValueType(0);
2761 errs() << "SPUTargetLowering::ReplaceNodeResults(): need to fix this!\n";
2762 errs() << "Op.getOpcode() = " << Opc << "\n";
2763 errs() << "*Op.getNode():\n";
2771 /* Otherwise, return unchanged */
2774 //===----------------------------------------------------------------------===//
2775 // Target Optimization Hooks
2776 //===----------------------------------------------------------------------===//
2779 SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
2782 TargetMachine &TM = getTargetMachine();
2784 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
2785 SelectionDAG &DAG = DCI.DAG;
2786 SDValue Op0 = N->getOperand(0); // everything has at least one operand
2787 EVT NodeVT = N->getValueType(0); // The node's value type
2788 EVT Op0VT = Op0.getValueType(); // The first operand's result
2789 SDValue Result; // Initially, empty result
2790 DebugLoc dl = N->getDebugLoc();
2792 switch (N->getOpcode()) {
2795 SDValue Op1 = N->getOperand(1);
2797 if (Op0.getOpcode() == SPUISD::IndirectAddr
2798 || Op1.getOpcode() == SPUISD::IndirectAddr) {
2799 // Normalize the operands to reduce repeated code
2800 SDValue IndirectArg = Op0, AddArg = Op1;
2802 if (Op1.getOpcode() == SPUISD::IndirectAddr) {
2807 if (isa<ConstantSDNode>(AddArg)) {
2808 ConstantSDNode *CN0 = cast<ConstantSDNode > (AddArg);
2809 SDValue IndOp1 = IndirectArg.getOperand(1);
2811 if (CN0->isNullValue()) {
2812 // (add (SPUindirect <arg>, <arg>), 0) ->
2813 // (SPUindirect <arg>, <arg>)
2815 #if !defined(NDEBUG)
2816 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2818 << "Replace: (add (SPUindirect <arg>, <arg>), 0)\n"
2819 << "With: (SPUindirect <arg>, <arg>)\n";
2824 } else if (isa<ConstantSDNode>(IndOp1)) {
2825 // (add (SPUindirect <arg>, <const>), <const>) ->
2826 // (SPUindirect <arg>, <const + const>)
2827 ConstantSDNode *CN1 = cast<ConstantSDNode > (IndOp1);
2828 int64_t combinedConst = CN0->getSExtValue() + CN1->getSExtValue();
2829 SDValue combinedValue = DAG.getConstant(combinedConst, Op0VT);
2831 #if !defined(NDEBUG)
2832 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2834 << "Replace: (add (SPUindirect <arg>, " << CN1->getSExtValue()
2835 << "), " << CN0->getSExtValue() << ")\n"
2836 << "With: (SPUindirect <arg>, "
2837 << combinedConst << ")\n";
2841 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2842 IndirectArg, combinedValue);
2848 case ISD::SIGN_EXTEND:
2849 case ISD::ZERO_EXTEND:
2850 case ISD::ANY_EXTEND: {
2851 if (Op0.getOpcode() == SPUISD::VEC2PREFSLOT && NodeVT == Op0VT) {
2852 // (any_extend (SPUextract_elt0 <arg>)) ->
2853 // (SPUextract_elt0 <arg>)
2854 // Types must match, however...
2855 #if !defined(NDEBUG)
2856 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2857 errs() << "\nReplace: ";
2859 errs() << "\nWith: ";
2860 Op0.getNode()->dump(&DAG);
2869 case SPUISD::IndirectAddr: {
2870 if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) {
2871 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1));
2872 if (CN != 0 && CN->isNullValue()) {
2873 // (SPUindirect (SPUaform <addr>, 0), 0) ->
2874 // (SPUaform <addr>, 0)
2876 DEBUG(errs() << "Replace: ");
2877 DEBUG(N->dump(&DAG));
2878 DEBUG(errs() << "\nWith: ");
2879 DEBUG(Op0.getNode()->dump(&DAG));
2880 DEBUG(errs() << "\n");
2884 } else if (Op0.getOpcode() == ISD::ADD) {
2885 SDValue Op1 = N->getOperand(1);
2886 if (ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(Op1)) {
2887 // (SPUindirect (add <arg>, <arg>), 0) ->
2888 // (SPUindirect <arg>, <arg>)
2889 if (CN1->isNullValue()) {
2891 #if !defined(NDEBUG)
2892 if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
2894 << "Replace: (SPUindirect (add <arg>, <arg>), 0)\n"
2895 << "With: (SPUindirect <arg>, <arg>)\n";
2899 return DAG.getNode(SPUISD::IndirectAddr, dl, Op0VT,
2900 Op0.getOperand(0), Op0.getOperand(1));
2906 case SPUISD::SHLQUAD_L_BITS:
2907 case SPUISD::SHLQUAD_L_BYTES:
2908 case SPUISD::ROTBYTES_LEFT: {
2909 SDValue Op1 = N->getOperand(1);
2911 // Kill degenerate vector shifts:
2912 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1)) {
2913 if (CN->isNullValue()) {
2919 case SPUISD::PREFSLOT2VEC: {
2920 switch (Op0.getOpcode()) {
2923 case ISD::ANY_EXTEND:
2924 case ISD::ZERO_EXTEND:
2925 case ISD::SIGN_EXTEND: {
2926 // (SPUprefslot2vec (any|zero|sign_extend (SPUvec2prefslot <arg>))) ->
2928 // but only if the SPUprefslot2vec and <arg> types match.
2929 SDValue Op00 = Op0.getOperand(0);
2930 if (Op00.getOpcode() == SPUISD::VEC2PREFSLOT) {
2931 SDValue Op000 = Op00.getOperand(0);
2932 if (Op000.getValueType() == NodeVT) {
2938 case SPUISD::VEC2PREFSLOT: {
2939 // (SPUprefslot2vec (SPUvec2prefslot <arg>)) ->
2941 Result = Op0.getOperand(0);
2949 // Otherwise, return unchanged.
2951 if (Result.getNode()) {
2952 DEBUG(errs() << "\nReplace.SPU: ");
2953 DEBUG(N->dump(&DAG));
2954 DEBUG(errs() << "\nWith: ");
2955 DEBUG(Result.getNode()->dump(&DAG));
2956 DEBUG(errs() << "\n");
2963 //===----------------------------------------------------------------------===//
2964 // Inline Assembly Support
2965 //===----------------------------------------------------------------------===//
2967 /// getConstraintType - Given a constraint letter, return the type of
2968 /// constraint it is for this target.
2969 SPUTargetLowering::ConstraintType
2970 SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const {
2971 if (ConstraintLetter.size() == 1) {
2972 switch (ConstraintLetter[0]) {
2979 return C_RegisterClass;
2982 return TargetLowering::getConstraintType(ConstraintLetter);
2985 std::pair<unsigned, const TargetRegisterClass*>
2986 SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2989 if (Constraint.size() == 1) {
2990 // GCC RS6000 Constraint Letters
2991 switch (Constraint[0]) {
2995 return std::make_pair(0U, SPU::R64CRegisterClass);
2996 return std::make_pair(0U, SPU::R32CRegisterClass);
2999 return std::make_pair(0U, SPU::R32FPRegisterClass);
3000 else if (VT == MVT::f64)
3001 return std::make_pair(0U, SPU::R64FPRegisterClass);
3004 return std::make_pair(0U, SPU::GPRCRegisterClass);
3008 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3011 //! Compute used/known bits for a SPU operand
3013 SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3017 const SelectionDAG &DAG,
3018 unsigned Depth ) const {
3020 const uint64_t uint64_sizebits = sizeof(uint64_t) * CHAR_BIT;
3022 switch (Op.getOpcode()) {
3024 // KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3030 case SPUISD::PREFSLOT2VEC:
3031 case SPUISD::LDRESULT:
3032 case SPUISD::VEC2PREFSLOT:
3033 case SPUISD::SHLQUAD_L_BITS:
3034 case SPUISD::SHLQUAD_L_BYTES:
3035 case SPUISD::VEC_ROTL:
3036 case SPUISD::VEC_ROTR:
3037 case SPUISD::ROTBYTES_LEFT:
3038 case SPUISD::SELECT_MASK:
3045 SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
3046 unsigned Depth) const {
3047 switch (Op.getOpcode()) {
3052 EVT VT = Op.getValueType();
3054 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
3057 return VT.getSizeInBits();
3062 // LowerAsmOperandForConstraint
3064 SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3065 char ConstraintLetter,
3066 std::vector<SDValue> &Ops,
3067 SelectionDAG &DAG) const {
3068 // Default, for the time being, to the base class handler
3069 TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
3072 /// isLegalAddressImmediate - Return true if the integer value can be used
3073 /// as the offset of the target addressing mode.
3074 bool SPUTargetLowering::isLegalAddressImmediate(int64_t V,
3075 const Type *Ty) const {
3076 // SPU's addresses are 256K:
3077 return (V > -(1 << 18) && V < (1 << 18) - 1);
3080 bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3085 SPUTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3086 // The SPU target isn't yet aware of offsets.