1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_ISELLOWERING_H
16 #define SPU_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END+SPU::INSTRUCTION_LIST_END,
28 // Pseudo instructions:
29 RET_FLAG, ///< Return with flag, matched by bi instruction
31 Hi, ///< High address component (upper 16)
32 Lo, ///< Low address component (lower 16)
33 PCRelAddr, ///< Program counter relative address
34 AFormAddr, ///< A-form address (local store)
35 IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
37 LDRESULT, ///< Load result (value, chain)
38 CALL, ///< CALL instruction
39 SHUFB, ///< Vector shuffle (permute)
40 INSERT_MASK, ///< Insert element shuffle mask
41 CNTB, ///< Count leading ones in bytes
42 PROMOTE_SCALAR, ///< Promote scalar->vector
43 EXTRACT_ELT0, ///< Extract element 0
44 EXTRACT_ELT0_CHAINED, ///< Extract element 0, with chain
45 EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend
46 EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend
47 EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend
48 EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend
49 MPY, ///< 16-bit Multiply (low parts of a 32-bit)
50 MPYU, ///< Multiply Unsigned
51 MPYH, ///< Multiply High
52 MPYHH, ///< Multiply High-High
53 VEC_SHL, ///< Vector shift left
54 VEC_SRL, ///< Vector shift right (logical)
55 VEC_SRA, ///< Vector shift right (arithmetic)
56 VEC_ROTL, ///< Vector rotate left
57 VEC_ROTR, ///< Vector rotate right
58 ROTBYTES_RIGHT_Z, ///< Vector rotate right, by bytes, zero fill
59 ROTBYTES_RIGHT_S, ///< Vector rotate right, by bytes, sign fill
60 ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
61 ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
62 FSMBI, ///< Form Select Mask for Bytes, Immediate
63 SELB, ///< Select bits -> (b & mask) | (a & ~mask)
64 SFPConstant, ///< Single precision floating point constant
65 FPInterp, ///< Floating point interpolate
66 FPRecipEst, ///< Floating point reciprocal estimate
67 SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits
68 LAST_SPUISD ///< Last user-defined instruction
72 /// Predicates that are used for node matching:
74 SDOperand get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
75 MVT::ValueType ValueType);
76 SDOperand get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
77 MVT::ValueType ValueType);
78 SDOperand get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
79 MVT::ValueType ValueType);
80 SDOperand get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
81 MVT::ValueType ValueType);
82 SDOperand get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
83 MVT::ValueType ValueType);
84 SDOperand get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
85 SDOperand get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
88 class SPUTargetMachine; // forward dec'l.
90 class SPUTargetLowering :
93 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
94 int ReturnAddrIndex; // FrameIndex for return slot.
95 SPUTargetMachine &SPUTM;
98 SPUTargetLowering(SPUTargetMachine &TM);
100 /// getTargetNodeName() - This method returns the name of a target specific
102 virtual const char *getTargetNodeName(unsigned Opcode) const;
104 /// LowerOperation - Provide custom lowering hooks for some operations.
106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
110 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
114 const SelectionDAG &DAG,
115 unsigned Depth = 0) const;
117 ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
119 std::pair<unsigned, const TargetRegisterClass*>
120 getRegForInlineAsmConstraint(const std::string &Constraint,
121 MVT::ValueType VT) const;
123 void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
124 std::vector<SDOperand> &Ops,
127 /// isLegalAddressImmediate - Return true if the integer value can be used
128 /// as the offset of the target addressing mode.
129 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
130 virtual bool isLegalAddressImmediate(GlobalValue *) const;