1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_ISELLOWERING_H
16 #define SPU_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Pseudo instructions:
29 RET_FLAG, ///< Return with flag, matched by bi instruction
31 Hi, ///< High address component (upper 16)
32 Lo, ///< Low address component (lower 16)
33 PCRelAddr, ///< Program counter relative address
34 AFormAddr, ///< A-form address (local store)
35 IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
37 LDRESULT, ///< Load result (value, chain)
38 CALL, ///< CALL instruction
39 SHUFB, ///< Vector shuffle (permute)
40 SHUFFLE_MASK, ///< Shuffle mask
41 CNTB, ///< Count leading ones in bytes
42 PREFSLOT2VEC, ///< Promote scalar->vector
43 VEC2PREFSLOT, ///< Extract element 0
44 SHLQUAD_L_BITS, ///< Rotate quad left, by bits
45 SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
46 VEC_ROTL, ///< Vector rotate left
47 VEC_ROTR, ///< Vector rotate right
48 ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
49 ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
50 SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
51 SELB, ///< Select bits -> (b & mask) | (a & ~mask)
52 // Markers: These aren't used to generate target-dependent nodes, but
53 // are used during instruction selection.
54 ADD64_MARKER, ///< i64 addition marker
55 SUB64_MARKER, ///< i64 subtraction marker
56 MUL64_MARKER, ///< i64 multiply marker
57 HALF2VEC, ///< Promote 64 bit vector to 128 bits
58 VEC2HALF, ///< Extract first 64 bits from 128 bit vector
59 LAST_SPUISD ///< Last user-defined instruction
63 //! Utility functions specific to CellSPU:
65 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
67 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
69 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
71 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
73 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
75 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
76 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
78 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
79 const SPUTargetMachine &TM);
80 //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
81 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
85 class SPUTargetMachine; // forward dec'l.
87 class SPUTargetLowering :
90 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
91 SPUTargetMachine &SPUTM;
94 //! The venerable constructor
96 This is where the CellSPU backend sets operation handling (i.e., legal,
97 custom, expand or promote.)
99 SPUTargetLowering(SPUTargetMachine &TM);
101 //! Get the target machine
102 SPUTargetMachine &getSPUTargetMachine() {
106 /// getTargetNodeName() - This method returns the name of a target specific
108 virtual const char *getTargetNodeName(unsigned Opcode) const;
110 /// getSetCCResultType - Return the ValueType for ISD::SETCC
111 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
113 //! Custom lowering hooks
114 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
116 //! Custom lowering hook for nodes with illegal result types.
117 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
118 SelectionDAG &DAG) const;
120 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
122 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
126 const SelectionDAG &DAG,
127 unsigned Depth = 0) const;
129 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
130 unsigned Depth = 0) const;
132 ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
134 std::pair<unsigned, const TargetRegisterClass*>
135 getRegForInlineAsmConstraint(const std::string &Constraint,
138 void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
139 std::vector<SDValue> &Ops,
140 SelectionDAG &DAG) const;
142 /// isLegalAddressImmediate - Return true if the integer value can be used
143 /// as the offset of the target addressing mode.
144 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
145 virtual bool isLegalAddressImmediate(GlobalValue *) const;
147 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
149 /// getFunctionAlignment - Return the Log2 alignment of this function.
150 virtual unsigned getFunctionAlignment(const Function *F) const;
153 LowerFormalArguments(SDValue Chain,
154 CallingConv::ID CallConv, bool isVarArg,
155 const SmallVectorImpl<ISD::InputArg> &Ins,
156 DebugLoc dl, SelectionDAG &DAG,
157 SmallVectorImpl<SDValue> &InVals) const;
160 LowerCall(SDValue Chain, SDValue Callee,
161 CallingConv::ID CallConv, bool isVarArg,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<SDValue> &OutVals,
165 const SmallVectorImpl<ISD::InputArg> &Ins,
166 DebugLoc dl, SelectionDAG &DAG,
167 SmallVectorImpl<SDValue> &InVals) const;
170 LowerReturn(SDValue Chain,
171 CallingConv::ID CallConv, bool isVarArg,
172 const SmallVectorImpl<ISD::OutputArg> &Outs,
173 const SmallVectorImpl<SDValue> &OutVals,
174 DebugLoc dl, SelectionDAG &DAG) const;