1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_ISELLOWERING_H
16 #define SPU_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Pseudo instructions:
29 RET_FLAG, ///< Return with flag, matched by bi instruction
31 Hi, ///< High address component (upper 16)
32 Lo, ///< Low address component (lower 16)
33 PCRelAddr, ///< Program counter relative address
34 AFormAddr, ///< A-form address (local store)
35 IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
37 LDRESULT, ///< Load result (value, chain)
38 CALL, ///< CALL instruction
39 SHUFB, ///< Vector shuffle (permute)
40 SHUFFLE_MASK, ///< Shuffle mask
41 CNTB, ///< Count leading ones in bytes
42 PREFSLOT2VEC, ///< Promote scalar->vector
43 VEC2PREFSLOT, ///< Extract element 0
44 SHL_BITS, ///< Shift quad left, by bits
45 SHL_BYTES, ///< Shift quad left, by bytes
46 SRL_BYTES, ///< Shift quad right, by bytes. Insert zeros.
47 VEC_ROTL, ///< Vector rotate left
48 VEC_ROTR, ///< Vector rotate right
49 ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
50 ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
51 SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
52 SELB, ///< Select bits -> (b & mask) | (a & ~mask)
53 // Markers: These aren't used to generate target-dependent nodes, but
54 // are used during instruction selection.
55 ADD64_MARKER, ///< i64 addition marker
56 SUB64_MARKER, ///< i64 subtraction marker
57 MUL64_MARKER, ///< i64 multiply marker
58 LAST_SPUISD ///< Last user-defined instruction
62 //! Utility functions specific to CellSPU:
64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
78 const SPUTargetMachine &TM);
79 //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
80 SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
84 class SPUTargetMachine; // forward dec'l.
86 class SPUTargetLowering :
89 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
90 SPUTargetMachine &SPUTM;
93 //! The venerable constructor
95 This is where the CellSPU backend sets operation handling (i.e., legal,
96 custom, expand or promote.)
98 SPUTargetLowering(SPUTargetMachine &TM);
100 //! Get the target machine
101 SPUTargetMachine &getSPUTargetMachine() {
105 /// getTargetNodeName() - This method returns the name of a target specific
107 virtual const char *getTargetNodeName(unsigned Opcode) const;
109 /// getSetCCResultType - Return the ValueType for ISD::SETCC
110 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
112 //! Custom lowering hooks
113 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
115 //! Custom lowering hook for nodes with illegal result types.
116 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
117 SelectionDAG &DAG) const;
119 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
121 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
125 const SelectionDAG &DAG,
126 unsigned Depth = 0) const;
128 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
129 unsigned Depth = 0) const;
131 ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
133 /// Examine constraint string and operand type and determine a weight value.
134 /// The operand object must already have been set up with the operand type.
135 ConstraintWeight getSingleConstraintMatchWeight(
136 AsmOperandInfo &info, const char *constraint) const;
138 std::pair<unsigned, const TargetRegisterClass*>
139 getRegForInlineAsmConstraint(const std::string &Constraint,
142 void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
143 std::vector<SDValue> &Ops,
144 SelectionDAG &DAG) const;
146 /// isLegalAddressImmediate - Return true if the integer value can be used
147 /// as the offset of the target addressing mode.
148 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
149 virtual bool isLegalAddressImmediate(GlobalValue *) const;
151 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
153 /// getFunctionAlignment - Return the Log2 alignment of this function.
154 virtual unsigned getFunctionAlignment(const Function *F) const;
157 LowerFormalArguments(SDValue Chain,
158 CallingConv::ID CallConv, bool isVarArg,
159 const SmallVectorImpl<ISD::InputArg> &Ins,
160 DebugLoc dl, SelectionDAG &DAG,
161 SmallVectorImpl<SDValue> &InVals) const;
164 LowerCall(SDValue Chain, SDValue Callee,
165 CallingConv::ID CallConv, bool isVarArg,
167 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<SDValue> &OutVals,
169 const SmallVectorImpl<ISD::InputArg> &Ins,
170 DebugLoc dl, SelectionDAG &DAG,
171 SmallVectorImpl<SDValue> &InVals) const;
174 LowerReturn(SDValue Chain,
175 CallingConv::ID CallConv, bool isVarArg,
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
177 const SmallVectorImpl<SDValue> &OutVals,
178 DebugLoc dl, SelectionDAG &DAG) const;
180 virtual bool isLegalICmpImmediate(int64_t Imm) const;
182 virtual bool isLegalAddressingMode(const AddrMode &AM,
183 const Type *Ty) const;