1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_ISELLOWERING_H
16 #define SPU_ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Pseudo instructions:
29 RET_FLAG, ///< Return with flag, matched by bi instruction
31 Hi, ///< High address component (upper 16)
32 Lo, ///< Low address component (lower 16)
33 PCRelAddr, ///< Program counter relative address
34 AFormAddr, ///< A-form address (local store)
35 IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
37 LDRESULT, ///< Load result (value, chain)
38 CALL, ///< CALL instruction
39 SHUFB, ///< Vector shuffle (permute)
40 SHUFFLE_MASK, ///< Shuffle mask
41 CNTB, ///< Count leading ones in bytes
42 PROMOTE_SCALAR, ///< Promote scalar->vector
43 VEC2PREFSLOT, ///< Extract element 0
44 VEC2PREFSLOT_CHAINED, ///< Extract element 0, with chain
45 EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend
46 EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend
47 EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend
48 EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend
49 MPY, ///< 16-bit Multiply (low parts of a 32-bit)
50 MPYU, ///< Multiply Unsigned
51 MPYH, ///< Multiply High
52 MPYHH, ///< Multiply High-High
53 SHLQUAD_L_BITS, ///< Rotate quad left, by bits
54 SHLQUAD_L_BYTES, ///< Rotate quad left, by bytes
55 VEC_SHL, ///< Vector shift left
56 VEC_SRL, ///< Vector shift right (logical)
57 VEC_SRA, ///< Vector shift right (arithmetic)
58 VEC_ROTL, ///< Vector rotate left
59 VEC_ROTR, ///< Vector rotate right
60 ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill
61 ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill
62 ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
63 ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
64 ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
65 SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
66 SELB, ///< Select bits -> (b & mask) | (a & ~mask)
67 ADD_EXTENDED, ///< Add extended, with carry
68 CARRY_GENERATE, ///< Carry generate for ADD_EXTENDED
69 SUB_EXTENDED, ///< Subtract extended, with borrow
70 BORROW_GENERATE, ///< Borrow generate for SUB_EXTENDED
71 FPInterp, ///< Floating point interpolate
72 FPRecipEst, ///< Floating point reciprocal estimate
73 SEXT32TO64, ///< Sign-extended 32-bit const -> 64-bits
74 LAST_SPUISD ///< Last user-defined instruction
78 /// Predicates that are used for node matching:
80 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
82 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
84 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
86 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
88 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
90 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
91 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
94 class SPUTargetMachine; // forward dec'l.
96 class SPUTargetLowering :
99 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
100 int ReturnAddrIndex; // FrameIndex for return slot.
101 SPUTargetMachine &SPUTM;
104 SPUTargetLowering(SPUTargetMachine &TM);
106 /// getTargetNodeName() - This method returns the name of a target specific
108 virtual const char *getTargetNodeName(unsigned Opcode) const;
110 /// getSetCCResultType - Return the ValueType for ISD::SETCC
111 virtual MVT getSetCCResultType(const SDValue &) const;
113 //! Custom lowering hooks
114 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
116 //! Custom lowering hook for nodes with illegal result types.
117 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
120 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
122 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
126 const SelectionDAG &DAG,
127 unsigned Depth = 0) const;
129 ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
131 std::pair<unsigned, const TargetRegisterClass*>
132 getRegForInlineAsmConstraint(const std::string &Constraint,
135 void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
137 std::vector<SDValue> &Ops,
138 SelectionDAG &DAG) const;
140 /// isLegalAddressImmediate - Return true if the integer value can be used
141 /// as the offset of the target addressing mode.
142 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
143 virtual bool isLegalAddressImmediate(GlobalValue *) const;
145 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;