1 //==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // Cell SPU instruction formats. Note that these are notationally similar to
14 // PowerPC, like "A-Form". But the sizes of operands and fields differ.
16 // This was kiped from the PPC instruction formats (seemed like a good idea...)
18 class I<dag OOL, dag IOL, string asmstr, InstrItinClass itin>
23 let Namespace = "SPU";
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
31 class RRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
32 InstrItinClass itin, list<dag> pattern>
33 : I<OOL, IOL, asmstr, itin> {
38 let Pattern = pattern;
40 let Inst{0-10} = opcode;
47 // RR Format, where RB is zeroed (dont care):
48 class RRForm_1<bits<11> opcode, dag OOL, dag IOL, string asmstr,
49 InstrItinClass itin, list<dag> pattern>
50 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
54 // RR Format, where RA and RB are zeroed (dont care):
55 // Used for reads from status control registers (see FPSCRRr32)
56 class RRForm_2<bits<11> opcode, dag OOL, dag IOL, string asmstr,
57 InstrItinClass itin, list<dag> pattern>
58 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
64 // RR Format, where RT is zeroed (don't care), or as the instruction handbook
65 // says, "RT is a false target." Used in "Halt if" instructions
66 class RRForm_3<bits<11> opcode, dag OOL, dag IOL, string asmstr,
67 InstrItinClass itin, list<dag> pattern>
68 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
73 class RRRForm<bits<4> opcode, dag OOL, dag IOL, string asmstr,
74 InstrItinClass itin, list<dag> pattern>
75 : I<OOL, IOL, asmstr, itin>
82 let Pattern = pattern;
84 let Inst{0-3} = opcode;
92 class RI7Form<bits<11> opcode, dag OOL, dag IOL, string asmstr,
93 InstrItinClass itin, list<dag> pattern>
94 : I<OOL, IOL, asmstr, itin>
100 let Pattern = pattern;
102 let Inst{0-10} = opcode;
103 let Inst{11-17} = i7;
104 let Inst{18-24} = RA;
105 let Inst{25-31} = RT;
109 class CVTIntFPForm<bits<10> opcode, dag OOL, dag IOL, string asmstr,
110 InstrItinClass itin, list<dag> pattern>
111 : I<OOL, IOL, asmstr, itin>
116 let Pattern = pattern;
118 let Inst{0-9} = opcode;
120 let Inst{18-24} = RA;
121 let Inst{25-31} = RT;
125 class BICondForm<bits<11> opcode, string asmstr, list<dag> pattern>
126 : RRForm<opcode, (outs), (ins R32C:$rA, R32C:$func), asmstr,
127 BranchResolv, pattern>
131 // Branch instruction format (without D/E flag settings)
132 class BRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
133 InstrItinClass itin, list<dag> pattern>
134 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
137 class BIForm<bits<11> opcode, string asmstr, list<dag> pattern>
138 : RRForm<opcode, (outs), (ins R32C:$func), asmstr, BranchResolv,
143 // Return instruction (bi, branch indirect), RA is zero (LR):
144 class RETForm<string asmstr, list<dag> pattern>
145 : BRForm<0b00010101100, (outs), (ins), asmstr, BranchResolv,
152 // Branch indirect external data forms:
153 class BISLEDForm<bits<2> DE_flag, string asmstr, list<dag> pattern>
154 : I<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
158 let Pattern = pattern;
160 let Inst{0-10} = 0b11010101100;
162 let Inst{12-13} = DE_flag;
163 let Inst{14-17} = 0b0000;
164 let Inst{18-24} = Rcalldest;
165 let Inst{25-31} = 0b0000000;
169 class RI10Form<bits<8> opcode, dag OOL, dag IOL, string asmstr,
170 InstrItinClass itin, list<dag> pattern>
171 : I<OOL, IOL, asmstr, itin>
177 let Pattern = pattern;
179 let Inst{0-7} = opcode;
180 let Inst{8-17} = i10;
181 let Inst{18-24} = RA;
182 let Inst{25-31} = RT;
185 // RI10 Format, where the constant is zero (or effectively ignored by the
187 class RI10Form_1<bits<8> opcode, dag OOL, dag IOL, string asmstr,
188 InstrItinClass itin, list<dag> pattern>
189 : I<OOL, IOL, asmstr, itin>
194 let Pattern = pattern;
196 let Inst{0-7} = opcode;
198 let Inst{18-24} = RA;
199 let Inst{25-31} = RT;
202 // RI10 Format, where RT is ignored.
203 // This format is used primarily by the Halt If ... Immediate set of
205 class RI10Form_2<bits<8> opcode, dag OOL, dag IOL, string asmstr,
206 InstrItinClass itin, list<dag> pattern>
207 : I<OOL, IOL, asmstr, itin>
212 let Pattern = pattern;
214 let Inst{0-7} = opcode;
215 let Inst{8-17} = i10;
216 let Inst{18-24} = RA;
221 class RI16Form<bits<9> opcode, dag OOL, dag IOL, string asmstr,
222 InstrItinClass itin, list<dag> pattern>
223 : I<OOL, IOL, asmstr, itin>
228 let Pattern = pattern;
230 let Inst{0-8} = opcode;
231 let Inst{9-24} = i16;
232 let Inst{25-31} = RT;
235 // Specialized version of the RI16 Format for unconditional branch relative and
236 // branch absolute, branch and set link. Note that for branch and set link, the
237 // link register doesn't have to be $lr, but this is actually hard coded into
238 // the instruction pattern.
241 class UncondBranch<bits<9> opcode, dag OOL, dag IOL, string asmstr,
243 : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
246 class BranchSetLink<bits<9> opcode, dag OOL, dag IOL, string asmstr,
248 : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
253 class RI18Form<bits<7> opcode, dag OOL, dag IOL, string asmstr,
254 InstrItinClass itin, list<dag> pattern>
255 : I<OOL, IOL, asmstr, itin>
260 let Pattern = pattern;
262 let Inst{0-6} = opcode;
263 let Inst{7-24} = i18;
264 let Inst{25-31} = RT;
267 //===----------------------------------------------------------------------===//
268 // Instruction formats for intrinsics:
269 //===----------------------------------------------------------------------===//
271 // RI10 Format for v8i16 intrinsics
272 class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin,
274 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
275 !strconcat(opc, " $rT, $rA, $val"), itin,
276 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
277 i16ImmSExt10:$val))] >;
279 class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin,
281 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
282 !strconcat(opc, " $rT, $rA, $val"), itin,
283 [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
284 i32ImmSExt10:$val))] >;
286 // RR Format for v8i16 intrinsics
287 class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin,
289 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
290 !strconcat(opc, " $rT, $rA, $rB"), itin,
291 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
292 (v8i16 VECREG:$rB)))] >;
294 // RR Format for v4i32 intrinsics
295 class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin,
297 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
298 !strconcat(opc, " $rT, $rA, $rB"), itin,
299 [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
300 (v4i32 VECREG:$rB)))] >;
302 //===----------------------------------------------------------------------===//
303 // Pseudo instructions, like call frames:
304 //===----------------------------------------------------------------------===//
306 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
307 : I<OOL, IOL, asmstr, NoItinerary> {
308 let Pattern = pattern;